RU2781355C1 - Scalar-vector processor - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: technical solution relates to the field of microprocessor computing. The technical result is achieved by the scalar-vector processor containing a reduction unit connected with the scalar and vector channels of the processor and implementing the functions of interaction thereof in operations where the scalar channel forms and/or utilises the scalar required and/or formed by the vector channel of the processor; the reduction unit also executes operations on the vector in general, i.e., permutation operations (shuffle), LUT transformations, and histogram calculations; the scalar and vector channels of the processor are additionally combined by an annular bus enabling data exchange thereon simultaneously with the execution of computational operations in the scalar and vector channels of the processor and in the reduction unit.

EFFECT: increase in the operation speed and the volume of processed data due to the parallel scalar and vector calculations.

44 cl, 7 dwg, 20 tbl

Description

The invention relates to the field of microprocessors, namely to scalar-vector processors, and can be used to build the architecture of IP processor cores focused on solving digital signal processing tasks, including applications of artificial intelligence and neural networks.

The constant increase in the complexity of the tasks being solved in the field of digital signal processing and the increase in the volume of processed data lead to a continuous increase in the requirements for the computing performance of the microprocessor systems performing these tasks. The main method for improving the performance of computations is their parallelization. The possibility of parallelization is ensured by the fact that in many signal processing tasks, as a rule, the execution of a large amount of identical computational procedures is required in relation to large arrays of processed data. Arrays of the same type of data are vectorized, and further high-performance processing is no longer carried out on individual elements, but on vectors. Microprocessor architectures that perform such processing are known as SIMD architectures (SIMD - Single Instruction, Multiple Data).

The difficulty, however, lies in the fact that no real application can achieve 100% vectorization. Amdahl's law is known, according to which the total acceleration obtained as a result of vectorization on a vector processor with P processing elements, depending on the fraction of the code f that can be vectorized, is equal to 1/(1-f+f/P). Thus, in real applied problems, along with vector processing, there is always a scalar part of calculations.

In practice, various approaches are used to organize this kind of mixed computing. For example, to implement neural networks, heterogeneous computing systems are widely used, which include a central processing unit (CPU), which performs the upper level of tasks and related scalar calculations, and a graphic processor (GPU), whose function is to perform massively parallel data processing. The disadvantage of this approach is that the transfer of data from one processor to another is associated with significant time delays, which negatively affects the actual performance achieved.

This led to the emergence of architectures in which a number of scalar and vector computing sections (cores) are combined in one microprocessor. One of the main problems of such architectures is the organization of effective interaction between the scalar and vector channels of the microprocessor. The fact is that in many applied tasks related to the processing of vector data, there is a need to perform operations in which a scalar channel generates and/or consumes a scalar required and/or generated by the vector channel of the microprocessor. In this way, the processor's scalar channel can prepare or further process the scalars needed for the vector channel or created by the vector channel, ensuring that the vector channel can continue to stream vectors without undue lag.

An example of operations involving both scalar and vector channels of the processor are reduction operations - these include, in particular, the determination and output of the minimum or maximum value of a vector, the sum or product of vector elements, etc.

In image processing tasks, other operations performed on the vector as a whole are also widely used - operations of permutations (shuffle), calculation of histograms, table transformations (LUT, Look-Up Table). Known methods for implementing such procedures have their advantages and disadvantages. A software implementation based on a standard set of instructions does not allow achieving high performance, while a hardware implementation in the form of accelerators requires additional hardware costs and has limited flexibility. For these reasons, the search for efficient ways to perform such computational procedures remains relevant.

Known solution (patent US 5659706), which describes a scalar-vector processor with a separate scalar and vector channels. Each of the processor channels is divided into functional blocks. The disadvantage of this solution is that there is no close interaction between the functional blocks of the scalar and vector channel of the processor. Both channels work completely independently, and this leads to additional time losses when transferring data from one part of the processor to another, and, accordingly, to a deterioration in processor performance.

Another solution is known (patent US 5822606 A), which describes one of the first signal processor architectures containing simultaneously functioning scalar and vector computing cores. The disadvantage of this architecture is that, as in the previous case, the scalar and vector computing cores do not interact directly with each other, data exchanges between them are performed through external memory, which is associated with significant delays, respectively, to the deterioration of the processor speed.

US 2004015677 A1 describes a scalar vector digital signal processor architecture that performs some serial style reduction operations by passing data from one SIMD section to another. The disadvantage of this architecture is the low performance achieved with sequential organization of calculations.

Known architecture (patent US 2005/0240644 A1) scalar-vector processor, which includes a set of functional (computing) blocks containing interacting vector and scalar channels. The disadvantage of this architecture is that the interaction between the vector and scalar channels of the processor is limited to a particular function block. In addition, this solution does not provide support for reduction operations.

US 2020/142704 A1 describes the architecture of a scalar-vector processor, which, along with SIMD parallelization, also uses instruction-level parallelism according to the VLIW (Very Long Instruction Word) principle both in the scalar and in the vector channel of the processor, which increases overall performance. However, there are no mechanisms for interaction between the scalar and vector channels of the processor.

Closest to the claimed invention is the architectural approach described in US 2021/0216318 A1. This patent proposes a whole family of scalar-vector processor architectures, including those that support the interaction of scalar and vector processor channels and provide for reduction operations. These architectures of the scalar vector processor are selected as prototypes of the claimed invention. However, the reduction operations in this patent are implemented on the basis of vector computing sections due to additional links between sections. This worsens the scalability of the architecture and makes it impossible to simultaneously perform reduction operations and other vector calculations. In addition, the proposed approach does not provide support for performing other operations on the vector as a whole - permutations, calculation of histograms, table transformations (LUT).

The technical result of the invention is the creation of a scalar-vector processor, which has increased efficiency, speed, functionality and versatility due to the fact that: it contains a reduction unit connected to the scalar and vector channels of the processor and realizing the functions of their interaction in various operations, in which the scalar channel generates and/or consumes a scalar required and/or generated by the vector channel of the processor; the reduction block performs, in addition, various operations on the vector as a whole - operations of permutations (shuffle), LUT-transformations, calculation of histograms; The scalar and vector channels of the processor are additionally united by a ring-shaped bus, which makes it possible to exchange data over it simultaneously with the execution of computational operations in the scalar and vector channels of the processor and in the reduction unit.

The set technical result is achieved by creating a scalar-vector processor 100 containing scalar and vector data processing channels 105 and 107 connected by a ring bus CDB 112, which are connected to the reduction unit VRED 104, as well as to the first-level data memory DMEM/L1D $ 103, which connected to the cache memory of the second level L2 $ 101, which is connected to the external interface of the processor, which has access to the external memory of the computing system, and is also connected to the program memory of the first level PMEM / L1I $ 102, the output of which is connected to the input of the FETCH command fetch unit 109, the output of which is connected to the input of the command decoding unit DECODE 110, the first output of which is connected to the inputs of the scalar and vector channels, and the second output is connected to the PCTRL 111 program control unit, the output of which is connected to the input of the program memory of the first level PMEM / L1I $ 102, and

- the program memory of the first level RMEM/L1I$ 102 and the data memory of the first level DMEM/L1D$ 103 are made with the possibility of generating calls and transferring them to

- cache memory of the second level L2$ 101, which is configured to serve calls from the program memory of the first level PMEM/L1I$ 102 and data memory of the first level DMEM/L1D$ 103, as well as to load data via an external interface from the external memory of the computer system and transferring data to the first level data memory DMEM/L1D$ 103 and the first level program memory PMEM/L1I$ 102;

- the FETCH 109 command fetch unit is configured to fetch commands from the PMEM/L1I$ 102 program memory and transfer them to

- a block for decoding commands DECODE software, configured to decode commands and generate software control commands for the executive devices of the processor and transfer them to

- a PCTRL block, which is configured to execute program control instructions.

In the preferred embodiment of the processor, the DMEM/L1D$ data memory 103 is implemented as an L1D$ cache or TCM (Tightly-Coupled Memory) DMEM static memory.

In the preferred embodiment of the processor, the first level program memory PMEM/L1I$ 102 is implemented as an L1I$ first cache memory or as a tightly coupled TCM (Tightly-Coupled Memory) PMEM static memory.

In the preferred embodiment, the processor at the level of the computing core has a Harvard architecture with the ability to simultaneously access the first level program memory PMEM/L1I$ 102 and the first level data memory DMEM/L1D$ 103 on separate buses.

In the preferred embodiment of the processor, the second level L2$ cache 101 has a von Neumann architecture.

In the preferred embodiment of the processor, the program control instructions are selected from an instruction set containing program jump instructions and program loop instructions.

In the preferred embodiment of the processor, the instructions are combined into instructions that are organized as a VLIW package 201 (VLIW - Very Long Instruction Word).

In the preferred embodiment of the processor, the VLIW packet 201 contains up to eight instructions, of which up to four instructions are for scalar data channel agents and up to four instructions are for vector data channel agents.

In the preferred embodiment of the processor, VLIW package 201 contains up to two scalar data exchange instructions and up to two vector data exchange instructions with DMEM/L1D$ data memory 103.

In the preferred embodiment, the processor has an instruction set consisting of software control instructions, instructions for the execution units of the scalar data processing channel and the vector data processing channel, as well as commands for the reduction unit VRED 104.

In the preferred embodiment of the processor, scalar channel 105 contains one scalar compute section 106.

In the preferred embodiment of the processor, the scalar compute section 106 contains a scalar register file RF 301 that is multi-ported and stores scalar data to be processed.

In the preferred embodiment of the processor, the RF scalar register file 301 contains ports associated with the scalar data processing channel 105 and configured to communicate with the DMEM/L1D$ data memory 103.

In the preferred embodiment of the processor, the RF scalar register file 301 comprises ports associated with the scalar computing section 106 actuators of the scalar data processing channel 105, configured to transmit input data to perform computational operations and write the results of the operations back to the RF 301 scalar register file.

In the preferred embodiment of the processor, the scalar computing section 106 contains data processing units SLSE0 310, SLSE1 311, which are configured to provide data exchange between the DMEM/L1D $ 103 data memory and the RF 301 scalar register file, including executing data transfer commands between memory data DMEM/L1D$ 103 and scalar register file RF 301.

In the preferred embodiment of the processor, the scalar computing section 106 includes data processing units ALU0 302, ALU1 303, ALU2 304, ALU3 305 that perform arithmetic and logical operations on fixed-point numbers.

In the preferred embodiment of the processor, the scalar computing section 106 includes processing units FALU0 306, FALU1 307 that perform arithmetic and logical operations on floating point numbers.

In the preferred embodiment of the processor, the scalar computing section 106 includes data processing units SMU0 308, SMU1 309 that perform multiplication operations on fixed and floating point numbers.

In the preferred embodiment of the processor, the scalar computing section 106 includes a data processing unit SH 312 that performs logical and arithmetic shift operations.

In the preferred embodiment of the processor, the scalar computing section 106 includes a data processing unit CONV 315 that performs data type conversion operations.

In the preferred embodiment of the processor, the scalar compute section 106 includes a DIV 313 processing unit that performs division operations.

In the preferred embodiment of the processor, the scalar computing section 106 includes a data processing unit MF 314 that performs transcendental mathematical function calculation operations. The basic set of operations performed by the MF 314 block is shown in Table 9.

In the preferred embodiment of the processor, the vector channel 107 consists of several vector computing sections 108, the number of which corresponds to the bit width of the vector being processed.

In the preferred embodiment of the processor, vector computing section 108 contains a vector register file VRF 401, which is multi-port and multi-format, and which stores vector data to be processed.

In the preferred embodiment of the processor, the vector VRF register file 401 is multi-format such that each 64-bit register 500 of the vector VRF register file 401 can store either one 64-bit value 501, or two 32-bit values 502, or four 16-bit values. 503, or eight 8-bit 504 values.

In the preferred embodiment of the processor, the vector register file VRF 401 contains ports associated with the external interface of the vector channel 107 and configured to communicate with the data memory DMEM/L1D$ 103.

In the preferred embodiment of the processor, the vector register file VRF 401 contains ports associated with the execution units of the vector computing section 108, configured to transmit initial data to perform computational operations and write the results back.

In the preferred embodiment of the processor, the vector register file VRF 401 is configured to work with various data formats.

In the preferred embodiment of the processor, the vector computing section 108 contains blocks VLSE0 412, VLSE1 413, which are configured to provide data exchange between the data memory DMEM/L1D $ 103 and the vector register file VRF 401, including the execution of data transfer commands between the data memory DMEM/L1D$ 103 and vector register file VRF 401.

In the preferred embodiment of the processor, vector computing section 108 includes blocks VALU0 403, VALU1 404, VALU2 405, VALU3 406, configured to perform arithmetic and logical operations on fixed-point numbers.

In the preferred embodiment of the processor, vector computing section 108 includes blocks VFALU0 407, VFALU1 408, configured to perform arithmetic and logical operations on floating point numbers.

In the preferred embodiment of the processor, vector computing section 108 includes blocks VMU0 409, VMU1 410 configured to perform multiplication and multiplication-accumulate operations on fixed and floating point numbers.

In the preferred embodiment of the processor, vector computing section 108 contains a vector accumulator register file VAC 402 configured to store data obtained and used as a result of performing multiply-accumulate operations performed by vector multiplier units VMU0 409, VMU1 410.

In the preferred embodiment of the processor, vector computing section 108 includes a VSH 411 configured to perform logical and arithmetic shift operations on the vector operands.

In the preferred embodiment of the processor, vector computing section 108 includes a VCONV block 414 configured to perform a data type conversion operation on vector operands.

In the preferred embodiment of the processor, the reduction unit VRED 104 is configured to compute reduction functions while providing increased efficiency, speed, functionality, and versatility of the processor.

In the preferred embodiment of the processor, the reduction unit VRED 104 is configured to compute the reduction functions, while implementing the interaction functions of the scalar and vector parts of the processor in various operations in which the scalar channel 105 generates and/or consumes the scalar required and/or generated by the vector channel 107.

In the preferred embodiment of the processor, the reduction unit VRED 104 includes a RALU 601 configured to perform arithmetic-logical intersectional reduction operations.

In the preferred embodiment of the processor, the reduction unit VRED 104 includes a SHUFFLE 602 capable of performing cross-sectional permutation operations.

In the preferred embodiment of the processor, the VRED reducer 104 includes a LUT 603 configured to perform cross-section table transformations.

In the preferred embodiment of the processor, the VRED reducer 104 includes a HIST 604 configured to perform histogram calculation operations.

In the preferred embodiment of the processor, the CDB (Circular Data Bus) 112 is configured to exchange data simultaneously with computational operations in the scalar and vector channels 105, 107 and in the reduction unit VRED 104.

In the preferred embodiment of the processor, the ring bus CDB 112 is configured to execute cyclic shift instructions that shift the register Ri of the scalar register file RF 301 into the register Vj of the vector register file VRF 401 of the zero vector computing section 108: Vj.0=Ri; the register Vj of the vector register file VRF 401 of the senior (N-1) vector computing section 108 is shifted to the register Ri of the scalar register file RF 301: Ri=Vj.N-1; the registers Vj of the vector register files VRF 401 of the remaining vector computing sections 108 are shifted by one section towards the higher sections: Vj.k=Vj.k-1, k=1,2,…,N-1.

In the preferred embodiment of the processor, the ring bus CDB 112 is configured to sequentially move data from vector channel 107 to scalar channel 105 to perform operations only available in scalar channel 105, and then return the converted data to vector channel 107.

For a better understanding of the claimed invention, the following is a detailed description with the corresponding drawings.

Fig. 1. Structural diagram of a scalar-vector processor, made according to the invention.

Fig. 2. Block diagram of the VLIW instruction of the scalar vector processor, made according to the invention.

Fig. 3. Structural diagram of the scalar computing section of the scalar channel of the scalar vector processor, made according to the invention.

Fig. 4. Structural diagram of the vector computing section of the vector channel of the scalar vector processor, made according to the invention.

Fig. 5. Structural diagram of a multi-format vector register file as part of the computational section of a vector channel, made according to the invention.

Fig. 6. Structural diagram of the reduction block, made according to the invention.

Fig. 7. Ring bus for intersectional scalar-vector data exchange, made according to the invention.

Tab. 1. The basic set of commands of the program control device, made according to the invention.

Tab. 2. The basic set of commands of the block of exchanges with the memory of the scalar channel, made according to the invention.

Tab. 3. The basic set of commands of the block of arithmetic-logical operations with a fixed point of the scalar channel, made according to the invention.

Tab. 4. The basic set of commands of the block of floating-point arithmetic-logical operations of the scalar channel, made according to the invention.

Tab. 5. The basic set of commands of the multiplication unit with fixed and floating point of the scalar channel, made according to the invention.

Tab. 6. The basic set of commands of the scalar channel shift block, made according to the invention.

Tab. 7. The basic set of commands of the scalar channel type conversion block, made according to the invention.

Tab. 8. The basic set of commands for the division block of the scalar channel, made according to the invention.

Tab. 9. The basic set of commands for the block for calculating the transcendental functions of the scalar channel, made according to the invention.

Tab. 10. The basic set of commands of the block of exchanges with the memory of the vector channel, made according to the invention.

Tab. 11. The basic set of commands of the block of arithmetic-logical operations with a fixed point of the vector channel, made according to the invention.

Tab. 12. The basic set of instructions for the block of floating-point arithmetic-logical operations of the vector channel, made according to the invention.

Tab. 13. The basic set of instructions for the multiplication block with fixed and floating point of the vector channel.

Tab. 14. Basic vector channel shift block instruction set according to the invention.

Tab. 15. The basic set of commands of the vector channel type conversion block, made according to the invention.

Tab. 16. Basic set of commands for the arithmetic logic unit of intersectional reduction.

Tab. 17. The basic set of commands of the block of intersectional permutations, made according to the invention.

Tab. 18. The basic set of commands block intersectional table transformations (LUT-transformations), made according to the invention.

Tab. 19. The basic set of commands for the histogram calculation block, made according to the invention.

Tab. 20. Basic set of instructions for intersectional scalar-vector shift, made according to the invention.

The architecture of the claimed scalar vector processor is focused primarily on solving digital signal processing problems associated with massively parallel computing, including applications of artificial intelligence and neural networks.

The processor 100 (FIG. 1) includes a scalar channel 105 (Scalar Channel) and a vector channel 107 (Vector Channel) of data processing. The scalar channel 105 includes one scalar computing section 106 (Scalar Unit), while the vector channel includes several vector computing sections 108 (Vector Lane).

The interaction of the processor with memory is organized in the traditional way. At the level of the processor core, the Harvard architecture is implemented with the possibility of simultaneous access to program memory and data via separate buses. At the same time, program and data memory can be implemented both in the form of a first-level cache memory (L1I$ 102 and L1D$ 103, respectively), and in the form of tightly coupled (Tightly-Coupled Memory, TCM) static memory (RMEM 102 and DMEM, respectively). 103). At the top level, a von Neumann architecture is implemented, in which the L2 $ 101 cache memory of the second level serves the cache memory of programs and data of the first level, and through the external interface has access to the external memory of the system.

Instructions read from the program memory PMEM/L1I$ 102 using the fetch device FETCH 109 are sent to the DECODE 110 block, which decodes them and generates control signals for the processor's actuators.

Instructions are organized in the form of VLIW-packages (VLIW - Very Long Instruction Word), containing several simultaneously executable commands for both scalar and vector channels 105, 107 of the processor. On FIG. 2 shows the structure of the VLIW packet 201. Each instruction in the VLIW packet 201 has a location called a slot. In total, the VLIW package has four slots 202-205 for scalar channel 105 instructions and four slots 206-209 for vector channel 107 instructions. Thus, up to eight instructions can be executed simultaneously. Each of the eight slots 202-209 of the VLIW package 201 may contain commands of a certain type, intended for the corresponding set of actuators 210-217. The composition and total number of commands for each VLIW package may be different.

Program control instructions, which include program jump instructions and program loop instructions, are executed using the PCTRL 111 program control unit.

Table 1 shows the basic set of program control commands executed using the PCTRL 111 block.

The commands of the scalar channel 105 of the processor include commands for scalar accesses to the data memory (SLSE0 310, SLSE1 311) and commands for performing scalar computational operations - fixed-point arithmetic-logical operations (ALU0 302, ALU1 303, ALU2 304, ALU3 305), arithmetic -logical floating point operations (FALU0 306, FALU1 307), fixed and floating point multiplication (SMU0 308, SMU1 309), shift (SH 312), type conversion (CONV 315), division (DIV 313), transcendental mathematical calculations functions (MF 314).

The instructions of the vector channel 107 of the processor include instructions for vector access to data memory (VLSE0 412, VLSE 413) and instructions for performing vector computing operations - fixed-point arithmetic-logical operations (VALU0 403, VALU1 404, VALU2 405, VALU3 406), arithmetic -logical floating point operations (VFALU0 407, VFALU1 408), fixed and floating point multiplication (VMU0 409, VMU1 410), shift (VSH 411), type conversion (VCONV 414), and reduction operations (VRED 104).

Together, the program control commands, the commands of the actuators of the scalar and vector channels 105, 107 of the processor, as well as the commands of the reduction unit 104 form a complete system of processor commands.

The structure of the scalar computing section 106 of the scalar channel 105 of the processor is shown in FIG. 3. The centerpiece of the scalar computational section 106 is the multi-port scalar register file RF 301, which stores the scalar data to be processed. Through the ports RF 301 connected to the external interface of the scalar channel 105 of the processor using the controllers of scalar accesses to the data memory SLSE1 311, SLSE2 data exchanges occur between the data memory DMEM/L1D $ 103 and the scalar channel 105 of the processor. Through the RF ports 301 associated with the executive devices of the scalar computing section 106 of the processor, transmit the initial data for the computational operations performed and record their results. Among the executive devices of the scalar computing section 106 of the processor are: four blocks of fixed-point arithmetic logic units ALU0 302, ALU1 303, ALU2 304, ALU3 305; two units of floating-point arithmetic logic units FALU0 306, FALU1 307; two blocks of multipliers with fixed and floating point SMU0 308, SMU1 309; shear block SH 312; type converter unit CONV 315; divider block DIV 313; block for calculating transcendental mathematical functions MF 314. Each of these blocks performs a corresponding set of scalar computational operations. At the same time, with the specified structure of the VLIW package, up to four scalar computational operations can be performed, including two operations of scalar data exchanges with the data memory of the first level DMEM/L1D$ 103.

Table 2 shows the basic set of instructions for scalar accesses to data memory 103, performed by blocks SLSE0 310, SLSE1 311.

Table 3 shows the basic set of instructions for fixed-point scalar arithmetic-logical operations performed by blocks ALU0 302, ALU1 303, ALU2 304, ALU3 305.

Table 4 shows the basic set of instructions for floating-point scalar arithmetic-logical operations performed by blocks FALU0 306, FALU1 307.

Table 5 shows the basic set of fixed and floating point scalar multiply instructions executed by SMU0 308, SMU1 309.

Table 6 lists the basic set of scalar shift commands executed by the SH 312 block.

Table 7 lists the basic set of scalar type conversion instructions performed by the CONV 315 block.

Table 8 shows the basic set of scalar division instructions executed with the DIV 313 block.

Table 9 shows the basic set of scalar commands for calculating transcendental mathematical functions performed using the MF 314 block.

Tables 1-20 use the following designations:

R, Ri, Ra, Rt, Rs, Rd - scalar data registers;

V, Vi, Va, Vt, Vs, Vd - vector data registers;

VAi - vector accumulator registers;

.b, .h, .l, .d - data format specifiers:

.b - byte (8 bits);

.h - halfword (16 bits);

.l - long (32 bits);

.d - double (64 bits);

i8, i16, i32, i64 - signed integer 8/16/32/64-bit formats;

u8, u16, u32, u64 - integer unsigned 8/16/32/64-bit formats;

#imm - immediate value;

#N - immediate N-bit value;

trunk _N - clipping up to N bits;

zext _N→M - extension of the number from N to M digits by filling in the missing high digits with zeros;

sext _N→M - extension of the number from N to M bits by filling in the missing high bits with a sign bit;

{,} - concatenation (union) of several operands;

T[i], S[i], D[i], V[i] - elements of vectors.

The vector channel 107 of the processor includes several vector computing sections 108, the total number of which is determined by the bit length of the processed vector. The structure of vector computing section 108 of vector channel 107 is shown in FIG. 4. It includes a multi-port multi-format vector register file VRF 401, designed to store processed vector data. Through the VRF 401 ports associated with the external interface of the vector channel 107 of the processor using the vector data memory access controllers VLSE0 412, VLSE1 413, data is loaded / unloaded from / to the data memory DMEM / L1D$ 103. Through the VRF 401 ports associated with the executive vector computing section 108 of the processor, the vector data is transmitted to the execution units, and the results are again written to the vector register file VRF 401.

A feature of the VRF 401 vector register file is the ability to work with various data formats, as shown in FIG. 5. Each 64-bit register 500 of the VRF vector register file 401 can store either one 64-bit value 501, or two 32-bit values 502, or four 16-bit values 503, or eight 8-bit values 504.

The composition of the vector computing section 108 of the vector channel 107 also includes a vector register file of accumulator registers VAC 402, designed to store data obtained and used as a result of performing multiplication and accumulation operations performed by two blocks of vector multipliers VMU0 409, VMU1 410.

The execution units of the computing section 108 of the vector channel 107 of the processor also include: four blocks of vector fixed-point arithmetic logic units VALU0 403, VALU1 404, VALU2 405, VALU3 406; two units of floating-point vector arithmetic-logical units VFALU0 407, VFALU1 408; vector shift block VSH 411; VCONV 414 type converter block; reduction function calculation unit VRED 104. Each of these units performs a corresponding set of vector computing operations. At the same time, with the specified structure of the VLIW package, up to four vector computing operations are performed, including two operations of vector data exchanges with DMEM/L1D $ 103 memory.

Table 10 shows the basic set of instructions for vector data memory accesses performed by the VLSE0 412, VLSE1 413 blocks.

Table 11 shows the basic set of instructions for fixed-point vector arithmetic-logical operations performed by blocks VALU0 403, VALU1 404, VALU2 405, VALU3 406.

Table 12 shows the basic set of floating-point vector arithmetic-logical operations performed by VFALU0 407, VFALU1 408 blocks.

Table 13 shows the basic set of fixed and floating point vector multiplication instructions executed by VMU0 409, VMU1 410.

Table 14 lists the basic set of vector shift commands that can be executed using the VSH 411 block.

Table 15 lists the basic set of vector type conversion instructions performed by the VCONV 414 block.

The most important feature of the considered architecture of the scalar-vector processor is the presence in its composition of the reduction unit VRED 104, which connects the scalar and vector channels 105, 107 of the processor, and is intended both for organizing exchanges between them and for performing operations that use and / or form both scalar and vector data. The block diagram of the reduction unit VRED 104 is shown in Fig. 6. It consists of the following actuators: RALU 601 block of arithmetic-logical intersectional reduction operations, block of intersectional permutations SHUFFLE 602, block of intersectional table transformations LUT 603, block of calculation of histograms HIST 604.

Table 16 shows the basic set of commands for the arithmetic logic unit of the intersectional reduction RALU 601, which is part of the reduction unit VRED 104.

Table 17 shows the basic set of commands for the SHUFFLE 602 inter-sectional permutation block, which is part of the VRED 104 reduction block.

Table 18 shows the basic set of commands of the LUT 603 intersectional table transformation block, which is part of the VRED 104 reduction block.

Table 19 shows the basic set of commands for the histogram calculation block HIST 604, which is part of the reduction block VRED 104.

Another mechanism that combines the scalar and vector channels of the processor is the CDB (Circular Data Bus) 112 shown in FIG. 7.

One of the instructions executed by the ring bus CDB 112 is the cyclic shift instruction VPUSHRD Ri, Vj, as a result of which the scalar register Ri is moved to the vector register Vj of the zero vector computing section 108: Vj.0=Ri; the vector register Vj of the senior vector computing section 108 is moved to the scalar register Ri: Ri=Vj.N; in the remaining vector computing sections 108, the data of the vector registers are shifted by one section towards the higher sections: Vj.k=Vj.k-1, k=1,2,…,N. This mechanism can be used, for example, to sequentially transfer data from the vector channel 107 of the processor to the scalar channel 105 in order to perform specific operations that are available only in the scalar channel 105 (for example, to calculate transcendental mathematical functions), with the subsequent return of the transformed data to the vector channel 107 of the processor.

Table 20 shows the basic set of cross-sectional scalar-vector shift commands performed using the CDB 112 ring data bus.

Thus, the architecture under consideration, in comparison with the previously known architectures of scalar-vector processors, has much more opportunities for organizing effective interaction between the scalar and vector channels 105, 107 of the processor, thereby providing higher performance of the scalar-vector calculations performed.

The composition and functionality of the actuators of the scalar and vector channels 105, 107 of the processor can be supplemented or reduced depending on the application of the processor.

Although the embodiment of the claimed invention described above has been set forth for the purpose of illustrating the claimed invention, it will be clear to those skilled in the art that various modifications, additions and substitutions are possible without departing from the scope and spirit of the claimed invention as disclosed in the appended claims.

Command mnemonic Description B#16
B#32
B Ra.L Program jump to relative address #16, #32, Ra.L J#16
J#32
J Ra.L Soft jump to absolute address #16, #32, Ra.L BS #16 Ri.L
BS #32 Ri.L
BS Ra.L, Ri.L Soft jump to relative address #16, #32, Ra.L while saving return address to Ri.L register (all 32 RF registers) JS #16, Ri.L
JS #32, Ri.L
JS Ra.L, Ri.L Soft jump to absolute address #16, #32, Ra.L while saving return address to Ri.L register (all 32 RF registers) DO #4, #16
DO #16, #32 Loop start with relative end address #16, #32 and immediate number of repetitions D.O.R.L., #16
D.O.R.L., #32 Loop start with relative end address #16, #32 and number of repetitions from register R.L ENDDO Stop the loop by condition. There is an immediate interruption of the loop and exit to the instruction following the last instruction of the loop.

Tab. one.

Command mnemonic Description LDB(A),R Load i8 from memory, sign extension to i32 LDBU(A), R Load u8 from memory, zero-extend to u32 LDH(A),R Load i16 from memory, sign extension to i32 LDHU(A),R Load u16 from memory, zero-extend to u32 LDL(A), R Load i32 word from memory (no conversion) LDD(A),R Load i64 dword from memory (no conversion) STB R, (A) Saving u8 to memory STH R, (A) Saving u16 to memory STL R, (A) Saving u32 to memory STD R, (A) Saving u64 to memory

Tab. 2.

Command mnemonic Formula Description Scalar integer addition/subtraction operations ADDD Rt, Rs, Rd
ADDD #imm, Rs, Rd
ADDD.SAT Rt, Rs, Rd Rd.d = (Rt.d(#imm) + Rs.d)
Rd.d = sat64(Rt.d + Rs.d) Addition of two operands, signed, with optional saturation, i64+i64→i64 ADDL Rt, Rs, Rd
ADDL #imm, Rs, Rd
ADDL.SAT Rt, Rs, Rd Rd = (Rt(#imm) + Rs)
Rd = sat32(Rt + Rd) Addition of two operands, signed, with optional saturation, i32+i32→i32 ADDL.SCL Rt, Rs, Rd
ADDL.SCL.RND Rt,Rs,Rd Rd = (Rt + Rs)>>1
Rd = (Rt + Rs + 1) >>1 Shift addition, signed, with optional rounding, i32+i32→i32 ADDL.RND Rt, Rs, Rd Rd.l = (Rt.l + Rs.l).rnd Addition with rounding i32+i32→i32
The lower 16 bits are rounded off. Subd Rt, Rs, Rd
Subd #imm, Rs, Rd
SUBD.SAT Rt, Rs, Rd Rd.d = (Rs.d - Rt.d(#imm))
Rd.d = sat64(Rs.d - Rt.d) Subtraction of two operands, signed, with optional saturation, i64 - i64 → i64 SUBL.SCL Rt, Rs, Rd
SUBL.SCL.RND Rt,Rs,Rd Rd = (Rs - Rt)>>1
Rd = (Rs - Rt - 1) >>1 Shift subtraction, signed, with optional rounding i32+i32→i32 SUBL.RND Rt, Rs, Rd Rd.l = (Rs.l - Rt.l).rnd Subtraction with rounding i32+i32→i32
The lower 16 bits are rounded off. NEGD Rs, Rd
NEGD.SAT Rs, Rd Rd = -Rs
Rd = sat32(-Rs) Result negation with optional result saturation, i64 NEGL Rs, Rd
NEGL.SAT Rs, Rd Rd = -Rs
Rd = sat32(-Rs) Result negation with optional result saturation, i32 Scalar Absolute Value Calculation Operations ABSD Rs, Rd
ABSD.SAT Rs, Rd Rd = |Rs|
Rd = sat64(|Rs|) Modulo 64 bit integer, signed, with optional saturation ABSL Rs, Rd
ABSL.SAT Rs, Rd Rd = |Rs|
Rd = sat32(|Rs|) Modulo 32 bit integer, signed, with optional saturation Scalar Integer Maximum/Minimum Calculation Operations MAXD Rt, Rs, Rd Rd = max(Rt, Rs) Maximum of two elements, i64 → i64 MAXDU Rt, Rs, Rd Rd = maxu(Rt, Rs) Maximum of two elements, u64 → u64 MAXMD Rt, Rs, Rd Rd = maxm(Rt, Rs) Choosing a number with a large modulus, i64 → i64 MIND Rt, Rs, Rd Rd = min(Rt, Rs) Minimum of two elements, i64 → i64 MINDU Rt, Rs, Rd Rd = minu(Rt, Rs) Minimum of two elements, u64 → u64 MINMD Rt, Rs, Rd Rd = minm(Rt, Rs) Choosing a number with a smaller modulus, i64 → i64 MAXL Rt, Rs, Rd Rd = max(Rt, Rs) Maximum of two elements, i32 → i32 MAXLU Rt, Rs, Rd Rd = maxu(Rt, Rs) Maximum of two elements, u32 → u32 MAXML Rt, Rs, Rd Rd = maxm(Rt, Rs) Choosing a number with a large modulus, i32 → i32 MINL Rt, Rs, Rd Rd = min(Rt, Rs) Minimum of two elements, i32 → i32 MINLU Rt, Rs, Rd Rd = minu(Rt, Rs) Minimum of two elements, u32 → u32 MINML Rt, Rs, Rd Rd = minm(Rt, Rs) Choosing a number with a smaller modulus, i32 → i32 Scalar Boolean Operations ANDD Rt/#imm, Rs, Rd Rd = Rt(#imm) & Rs Element-by-element logical "AND" ORD Rt/#imm, Rs, Rd Rd = Rt(#imm) | Rs Element-by-element logical "OR" EORD Rt, Rs, Rd Rd = Rt^Rs Element-by-element logical exclusive "OR" INSD Rt, Rs, Rd Rd = (~Rt & Rs) | (Rt & Rd) Merge by mask ANDL Rt/#imm, Rs, Rd Rd = Rt(#imm) & Rs Element-by-element logical "AND" ORL Rt/#imm, Rs, Rd Rd = Rt(#imm) | Rs Element-by-element logical "OR" EORL Rt, Rs, Rd Rd = Rt^Rs Element-by-element logical exclusive "OR" INSL Rt, Rs, Rd Rd = (~Rt & Rs) | (Rt & Rd) Merge by mask NOTL Rs, Rd Rd = ~Rs Negative result

Tab. 3.

Command mnemonic Formula Description Scalar Floating-Point Add/Subtract FADD Rt, Rs, Rd Rd = Rt + Rs Adding two numbers, f32 + f32 → f32 DADD Rt, Rs, Rd Rd = Rt + Rs Adding two numbers, f64 + f64 → f64 FSUB Rt, Rs, Rd Rd = Rs - Rt Subtraction of two numbers, f32 - f32 → f32 DSUB Rt, Rs, Rd Rd = Rs - Rt Subtraction of two numbers, f64 - f64 → f64 Scalar maximum/minimum floating point operations FMAX Rt, Rs, Rd Rd = max(Rt, Rs) Maximum of two numbers, f32 DMAX Rt, Rs, Rd Rd = max(Rt, Rs) Maximum of two numbers, f64 FMIN Rt, Rs, Rd Rd = min(Rt, Rs) Minimum of two numbers, f32 DMIN Rt, Rs, Rd Rd.d = min(Rt, Rs) Minimum of two numbers, f64

Tab. four.

Command mnemonic Formula Description Scalar operations of integer multiplication MPYLLO Rt, Rs, Rd
MPYLLO #imm, Rs, Rd Rd = trunk ₃₂ (Rs * Rt)
Rd = trunk ₃₂ (Rs * #imm) Multiply i32*i32→i64, use lower 32 bits, i32 MPYLULO Rt, Rs, Rd
MPYLULO #imm, Rs, Rd Rd = trunk ₃₂ (Rs * Rt)
Rd = trunk ₃₂ (Rs * #imm) Multiply u32*u32→u64, use lower 32 bits, u32 MPYLHI Rt, Rs, Rd
MPYLHI #imm, Rs, Rd
MPYLHI.RND Rt, Rs, Rd Rd = (Rs * Rt)>>32
Rd = (Rs * #imm)>>32
Rd = (Rs * #imm + 0x8000_0000)>>32 Multiplication, high 32 bits, i32*i32→i64, with optional rounding MPYLUHI Rt, Rs, Rd
MPYLUHI #imm, Rs, Rd Rd = (Rs * Rt)>>32
Rd = (Rs * #imm)>>32 Multiplication, using high 32 bits, u32*u32→u32 MPYL Rt, Rs, Rdd
MPYL #imm, Rs, Rdd Rdd = Rs * Rt
Rdd = Rs * #imm Multiplication, write full result to pair register, i32*i32→i64 MPYLU Rt, Rs, Rdd
MPYLU #imm, Rs, Rdd Rdd = Rs * Rt
Rdd = Rs * #imm Multiplication, write full result to pair register, u32*u32→u64 MPYDLO Rt, Rs, Rd Rd = trunk ₆₄ (Rs * Rt) Multiply i64*i64→i128, use lower 64 bits, i64 MPYDHI Rt, Rs, Rd Rd = (Rs * Rt)>>128 Multiplication, using high 64 bits, i64*i64→i128 MPYDULO Rt, Rs, Rd Rd = trunk ₆₄ (Rs * Rt) Multiply u64*u64→u128, use lower 64 bits, u64 MPYDUHI Rt, Rs, Rd Rd = (Rs * Rt)>>128 Multiplication, high 64 bits, u64*u64→u128 Scalar Floating-Point Multiplications FMPY Rt, Rs, Rd Rd = Rt*Rs Multiplication of two numbers, f32*f32 → f32 DMPY Rt, Rs, Rd Rd.d = Rt.d*Rs.d Multiplication of two numbers, f64*f64 → f64 FMADD Rt, Rs, Rd
FMADD Rt, Rs, Rr, Rd Rd = Rd + Rt*Rs
Rd = Rr + Rt*Rs Product addition, f32*f32+f32→f32 FMSUB Rs, Rt, Rd Rd = Rd - Rt*Rs Product subtraction, f32*f32-f32→f32

Tab. 5.

Command mnemonic Formula Description Scalar shift operations ASRD Rt,Rs, Rd
ASRD #5u, Rs, Rd
ASRD1 #5u, Rs, Rd Rd.d = Rs.d >> Rt
Rd.d = Rs.d >>#5u
Rd.d = Rs.d >>(#5u+32) Arithmetic right shift LSLD Rt,Rs, Rd
LSLD #5u,Rs, Rd
LSLD1 #5u,Rs, Rd Rd.d = Rs.d <<< Rt
Rd.d = Rs.d <<<#5u
Rd.d = Rs.d <<<(#5u+32) Logical shift left LSRD Rt,Rs, Rd
LSRD #u5,Rs, Rd
LSRD1 #u5,Rs, Rd Rd.d = Rs.d >>> Rt
Rd.d = Rs.d >>>#5u
Rd.d = Rs.d >>>(#5u+32) Logical right shift LSLD.SAT Rt(#u5),Rs, Rd
LSLD1.SAT #u5,Rs, Rd Rd = sat64(Rs <<<(#5u))
Rd = sat64(Rs <<<(#5u+32)) Logical left shift with saturation. When leaving the bit grid of any single bit, the maximum unsigned value is set. ROLD Rt/#5u, Rs, Rd Rd = (Rs <<< Rt) | (Rs>>>(64-Rt)) Rotate left, 64-bit grid
Normal behavior when #5 = 0: result Rd = Rs. RORD Rt/#5u, Rs, Rd Rd = (Rs >>> Rt) | (Rs<<<(64-Rt)) Rotate right, 64-bit grid
Special behavior when #5 = 0: result Rd = {Rs.L[0], Rs.L[1]} (two 32-bit words are swapped). ASRL Rt(#u5),Rs, Rd Rd = Rs >> Rt Arithmetic right shift LSLL Rt(#u5),Rs, Rd Rd = Rs <<< Rt Logical shift left LSRL Rt(#u5),Rs, Rd Rd = Rs >>> Rt Logical right shift LSLL.SAT Rt(#u5),Rs, Rd Rd = sat32(Rs <<< Rt) Logical left shift with saturation. When leaving the bit grid of any single bit, the maximum unsigned value is set. ROLL Rt, Rs, Rd
ROLL #5u, Rs, Rd Rd = (Rs <<< Rt) | (Rs>>>(32-Rt)) Rotate left, 32-bit grid RORL Rt, Rs, Rd
RORL #5u, Rs, Rd Rd = (Rs >>> Rt) | (Rs<<<(32-RT)) Rotate right, 32 bit grid

Tab. 6.

Command mnemonic Formula Description Scalar Extension Operations of Integer Types CVBLU Rt, Rd
CVBL Rt, Rd Rd.l = zext _8→32 (Rt.b)
Rd.l = sext _8→32 (Rt.b) Byte to integer expansion, i8 → i32, signed and unsigned CVHLU Rt, Rd
CVHL Rt, Rd Rd.l = zext _16→32 (Rt.h)
Rd.l = sext _16→32 (Rt.h) Short integer to integer expansion, i16 → i32, signed and unsigned CVBDU Rt, Rs
CVBD Rt, Rd Rd.d= zext _8→64 (Rt.b)
Rd.d = sext _8→64 (Rt.b) Byte to integer expansion, i8 → i64, signed and unsigned CVHDU Rt, Rs
CVHD Rt, Rd Rd.d= zext _16→64 (Rt.h)
Rd.d = sext _16→64 (Rt.h) Byte to integer expansion, i16 → i64, signed and unsigned CVLDU Rt, Rs
CVLD Rt, Rd Rd.d= zext _32→64 (Rt.l)
Rd.d = sext _32→64 (Rt.l) Byte to integer expansion, i32 → i64, signed and unsigned Scalar Truncation of Integer Types CVLB Rt, Rd
CVLB.sat Rt, Rd
CVLBU.sat Rt, Rd
CVLH Rt, Rd
CVLH.sat Rt, Rd
CVLHU.sat Rt, Rd
CVDB Rt, Rd
CVDB.sat Rt, Rd
CVDBU.sat Rt, Rd
CVDH Rt, Rd
CVDH.sat Rt, Rd
CVDHU.sat Rt, Rd
CVDL Rt, Rd
CVDL.sat Rt, Rd
CVDLU.sat Rt, Rd (on the example of CVLB)
CVLB Rt, Rd Rd=sext _8→32 (trunk8(Rt))
CVLB.sat Rt, Rd
Rd=sext _8→32 (sat8(Rt))
CVLBU.sat Rt, Rd
Rd=zext _8→32 (usat8(Rt)) (on the example of CVLB)
Truncation of raw data (L) to the requested value (B), with optional saturation. The resulting number (B) is expanded by its sign (for signed extensions) or zero (for unsigned extensions - with the U suffix) to the original value (L) Scalar floating-point type conversions FDCV Rt, Rd Rd = float_to_double(RT) Convert float32 to float64 DFCV Rt, Rd Rd = double_to_float(RT) Convert float64 to float32 FHCV Rt, Rd Rd[0].h = float_to_halffloat(Rt)
Rd[1].h = 0 Convert float32 to float16
The upper 16 bits of register Rd are filled with zero. DHCV Rt, Rd Rd[0].h = double_to_halffloat(Rt)
Rd[1].h = 0 Convert float64 to float16
The upper 16 bits of register Rd are filled with zero. HFCV Rt, Rd Rd = halffloat_to_float(RT) Convert float16 to float32 HDCV Rt, Rd Rd = halffloat_to_doubleRt) Convert float16 to float64 Scalar type conversion operations INT->FLT CVDF Rt, Rd Rd.f32 = int64_to_float32(Rt.d) Convert int64 to float32 CVDFU Rt, Rd Rd.f32 = uint64_to_float32(Rt.d) Convert uint64 to float32 CVDD Rt, Rd Rd.f64= int64_to_float64(Rt.d) Convert int64 to float64 CVDDU Rt, Rd Rd.f64 = uint64_to_float64(Rt.d) Convert from uint64 to float64 CVIF Rt, Rd Rd.f32 = int32_to_float32(Rt.d) Convert from int32 to float32 CVIFU Rt, Rd Rd.f32 = uint32_to_float32(Rt.d) Convert from uint32 to float32 CVID Rt, Rd Rd.f64 = int32_to_float64(Rt.d) Convert from int32 to float64 CVIDU Rt, Rd Rd.f64 = uint32_to_float64(Rt.d) Convert from uint32 to float64 CVHF Rt, Rd Rd.f32 = int16_to_float32(Rt.d) Convert from int16 to float32 CVHFU Rt, Rd Rd.f32 = uint16_to_float32(Rt.d) Convert from uint16 to float16 Scalar type conversion operations FLT->INT FCVD Rt, Rd Rd.d = float32_to_int64(Rt.d) Convert from float32 to int64 FCVDU Rt, Rd Rd.ud = float32_to_uint64(Rt.d) Convert from float32 to uint64 FCVI Rt, Rd
FCVI.floor Rt, Rd
FCVI.round Rt, Rd
FCVI.ceil Rt, Rd
FCVI.trunc Rt, Rd Rd.l = float32_to_int32(Rt.d) Convert from float32 to int32
Optional rounding FCVIU Rt, Rd
FCVIU.floor Rt, Rd
FCVIU.round Rt, Rd
FCVIU.ceil Rt, Rd
FCVIU.trunc Rt, Rd Rd.ul = float32_to_uint32(Rt.d) Convert from float32 to uint32
Optional rounding DCVD Rt, Rd
DCVD.floor Rt, Rd
DCVD.round Rt, Rd
DCVD.ceil Rt, Rd
DCVD.trunc Rt, Rd Rd.d = float64_to_int64(Rt.d) Convert from float64 to int64
Optional rounding DCVDU Rt, Rd
DCVDU.floor Rt, Rd
DCVDU.round Rt, Rd
DCVDU.ceil Rt, Rd
DCVDU.trunc Rt, Rd Rd.ud = float64_to_uint64(Rt.d) Convert from float64 to uint64
Optional rounding DCVI Rt, Rd Rd.l = float64_to_int32(Rt.d) Convert from float64 to int32 DCVIU Rt, Rd Rd.ul = float64_to_uint32(Rt.d) Convert from float64 to uint32 FCVH Rt, Rd Rd.l = float32_to_int16(Rt.d) Convert from float32 to int16 FCVHU Rt, Rd Rd.ul = float32_to_uint16(Rt.d) Convert from float32 to uint16

Tab. 7.

Command mnemonic Formula Description Scalar integer division operations DIVL Rd.L = Rt.L/Rs.L Division i32:
if (Rs == 0)
REM = 0
DIV = (Rt >= 0)? 0x7FFFFFFF: 0x80000000
else
DIV = Rt / Rs
REM = Rt % Rs
Rd=DIV REML Rd.L = Rt.L%Rs.L Remainder from dividing i32:
if (Rs == 0)
REM = 0
DIV = (Rt >= 0)? 0x7FFFFFFF: 0x80000000
else
DIV = Rt / Rs
REM = Rt % Rs
Rd=REM DIVREML Rd.D = {Rt.L%Rs.L , Rt.L/Rs.L} Remainder of i32 division, i32 division:
if (Rs == 0)
REM = 0
DIV = (Rt >= 0)? 0x7FFFFFFF: 0x80000000
else
DIV = Rt / Rs
REM = Rt % Rs
Rd = {REM, DIV} DIVLU Rd.L = Rt.L/Rs.L Division u32:
if (Rs == 0)
DIV = 0xFFFFFFFF
REM = 0
else
DIV = Rt / Rs
REM = Rt % Rs
Rd=DIV REMLU Rd.L = Rt.L%Rs.L Remainder from dividing u32:
if (Rs == 0)
DIV = 0xFFFFFFFF
REM = 0
else
DIV = Rt / Rs
REM = Rt % Rs
Rd=REM DIVREMLU Rd.D = {Rt.L%Rs.L , Rt.L/Rs.L} Remainder from division u32, division u32:
if (Rs == 0)
DIV = 0xFFFFFFFF
REM = 0
else
DIV = Rt / Rs
REM = Rt % Rs
Rd = {REM, DIV}

Tab. eight.

Command mnemonic Formula Description Scalar operations for calculating transcendental mathematical functions FEXP2 Rt, Rd Rd.L = 2.0 ^Rt Calculation of the value of the exponential function with base 2: Z=2 ^X .
Input (X) and output (Z) are 32-bit floating point format: (float32)X, (float32)Z FLOG Rt, Rd Rd.L = ln(Rt) Calculating the value of the natural logarithm:
Z=LnX.
Input (X) and output (Z) are 32-bit floating point format: (float32)X, (float32)Z FSQRT Rt, Rd Rd.L = sqrt_approx(Rt) Extracting the square root:
Z=√X.
The input (X) and output (Z) are in 32-bit floating point format:
(float32)X, (float32)Z.
Restrictions and special cases:
FSQRT(0) = 0
FSQRT(-0) = -0
FSQRT(A) = NaN, A < 0 FISQRT Rt, Rd Rd.L = isqrt_approx(Rt) Calculating the reciprocal of the square root:
Z=1./√X.
Input (X) and output (Z) are 32-bit floating point format: (float32)X, (float32)Z FRECIP Rt, Rd Rd.L = recipe_approx(Rt) Calculating the reciprocal:
Z=1./X.
Input (X) and output (Z) are 32-bit floating point format: (float32)X, (float32)Z

Tab. 9.

Command mnemonic Description VLD Load without data type conversion VLDBH
VLDBHU Load data with data type extension sign or null, i8(u8) → i16(u16) VLDBL
VLDBL Load data with data type extension sign or null, i8(u8) → i32(u32) VLDHL
VLDHLU Load data with data type extension sign or null, i16(u16) → i32(u32) VLDLD
VLDLDU Load data with data type extension sign or null, i32(u32) → i64(u64) VST Saving without data type conversion VSTHBU Save with data type truncation, u16 → u8 VSTLBU Save with data type truncation, u32 → u8 VSTLHU Save with data type truncation, u32 → u16 VSTDLU Save with data type truncation, u64 → u32

Tab. ten.

Command mnemonic Formula Description Vector integer addition/subtraction operations VADDD Vt, Vs, Vd
VADDD.SAT Vt, Vs, Vd
VADDDU.SAT Vt, Vs, Vd D[i] = T[i] + S[i], i = 0
D[i] = sat32(T[i] + S[i]),i=0
D[i] = usat32(T[i] + S[i]), i = 0, unsigned Addition i64 = i64 + i64 signed (unsigned u64+u64→u64),
Optional saturation VADDD.SCL Vt, Vs, Vd
VADDD.SCL.RND Vt, Vs, Vd
VADDDU.SCL Vt, Vs, Vd
VADDDU.SCL.RND Vt, Vs, Vd D[i] = (T[i] + S[i]) >> 1, i=0
D[i] = rnd(T[i] + S[i]) >> 1, i = 0
D[i] = (T[i] + S[i]) >> 1, i = 0, unsigned
D[i] = rnd(T[i] + S[i]) >> 1, i = 0, unsigned Addition i64 = i64 + i64 signed (unsigned u64+u64→u64),
Optional rounding VADDL Vt, Vs, Vd
VADDL #32, Vs, Vd
VADDL.SAT Vt, Vs, Vd
VADDLU.SAT Vt, Vs, Vd D[i] = T[i] + S[i], i = 0:1
D[i] = #I2 + S[i], i = 0:1
D[i] = sat32(T[i] + S[i]), i = 0:1
D[i] = usat32(T[i] + S[i]), i = 0:1, unsigned Add i32 = i32 + i32 signed (unsigned u32+u32→u32),
Optional saturation VADDL.SCL Vt, Vs, Vd
VADDL.SCL.RND Vt, Vs, Vd
VADDLU.SCL Vt, Vs, Vd
VADDLU.SCL.RND Vt, Vs, Vd D[i] = (T[i] + S[i]) >> 1, i = 0:1
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:1
D[i] = (T[i] + S[i]) >> 1, i = 0:1, unsigned
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:1, unsigned Add i32 = i32 + i32 signed (unsigned u32+u32→u32),
Optional rounding VADDH Vt, Vs, Vd
VADDH #IMM16, Vs, Vd
VADDH.SAT Vt, Vs, Vd
VADDHU.SAT Vt, Vs, Vd D[i] = T[i] + S[i], i = 0:3
D[i] = #IMM16 + S[i], i = 0:3
D[i] = sat16(T[i] + S[i]), i = 0:3
D[i] = usat16(T[i] + S[i]), i = 0:3, unsigned Addition i16 = i16 + i16 signed (unsigned u32+u32→u32),
Optional saturation VADDH.SCL Vt, Vs, Vd
VADDH.SCL.RND Vt, Vs, Vd
VADDHU.SCL Vt, Vs, Vd
VADDHU.SCL.RND Vt, Vs, Vd D[i] = (T[i] + S[i]) >> 1, i = 0:3
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:3
D[i] = (T[i] + S[i]) >> 1, i = 0:3, unsigned
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:3, unsigned Addition i16 = i16 + i16 signed (unsigned u32+u32→u32),
Optional rounding VADDB Vt, Vs, Vd
VADDB #IMM8, Vs, Vd
VADDB.SAT Vt, Vs, Vd
VADDBU.SAT Vt, Vs, Vd D[i] = T[i] + S[i], i = 0:7
D[i] = #IMM8 + S[i], i = 0:7
D[i] = sat8(T[i] + S[i]), i = 0:7
D[i] = usat8(T[i] + S[i]), i = 0:7, unsigned Addition i8 = i8 + i8 signed (unsigned u8+u8→u8),
Optional saturation VADDB.SCL Vt, Vs, Vd
VADDB.SCL.RND Vt, Vs, Vd
VADDBU.SCL Vt, Vs, Vd
VADDBU.SCL.RND Vt, Vs, Vd D[i] = (T[i] + S[i]) >> 1, i = 0:7
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:7
D[i] = (T[i] + S[i]) >> 1, i = 0:7, unsigned
D[i] = rnd(T[i] + S[i]) >> 1, i = 0:7, unsigned Addition i8 = i8 + i8 signed (unsigned u8+u8→u8),
Optional rounding VSUBD Vt, Vs, Vd
VSUBD.SAT Vt, Vs, Vd
VSUBDU.SAT Vt, Vs, Vd D[i] = S[i] - S[i], i = 0
D[i] = sat64(S[i] - T[i]), i = 0
D[i] = usat64(S[i] - T[i]), i = 0, unsigned
Vt: = {T1, T0}, i64/u64, Vs = {S0, S0}, i64/u64
Vd = {D1, D0}, i64/u64 Subtraction i64 = i64 - i64 signed (unsigned u64-u64→u64),
Optional saturation VSUBL Vt, Vs, Vd
VSUBL #32, Vs, Vd
VSUBL.SAT Vt, Vs, Vd
VSUBLU.SAT Vt, Vs, Vd D[i] = S[i] - T[i], i = 0:1
D[i] = S[i] - #32, i = 0:1
D[i] = sat32(S[i] - T[i]), i = 0:1
D[i] = usat32(S[i] - T[i]), i = 0:1, unsigned Subtraction i32 = i32 - i32 signed (unsigned u32-u32→u32),
Optional saturation VSUBL.SCL Vt, Vs, Vd
VSUBL.SCL.RND Vt, Vs, Vd
VSUBL.SCL.RND.SAT Vt, Vs, Vd D[i] = (S[i] - T[i]) >> 1, i = 0:1
D[i] = rnd(S[i] - T[i] + 1) >> 1, i = 0:1
D[i] = sat32(rnd(S[i] - T[i]) >> 1), i = 0:1 Subtraction i32 = i32 - i32 signed,
Optional rounding and saturation VSUBH Vt, Vs, Vd
VSUBH #IMM16, Vs, Vd
VSUBH.SAT Vt, Vs, Vd
VSUBHU.SAT Vt, Vs, Vd D[i] = S[i] - S[i], i = 0:3
D[i] = S[i] - #IMM16, i = 0:1
D[i] = sat16(S[i] - T[i]), i = 0:1
D[i] = usat16(S[i] - T[i]), i = 0:3, unsigned Subtraction i16 = i16 - i16 signed (unsigned u16-u16→u16),
Optional saturation VSUBH.SCL Vt, Vs, Vd
VSUBH.SCL.RND Vt, Vs, Vd
VSUBH.SCL.RND.SAT Vt, Vs, Vd D[i] = (S[i] - T[i]) >> 1, i = 0:1
D[i] = rnd(S[i] - T[i]) >> 1, i = 0:1
D[i] = sat16(rnd(S[i] - T[i]) >> 1), i = 0:1 Subtraction i16 = i16 - i16 signed,
Optional rounding and saturation VSUBB Vt, Vs, Vd
VSUBB #IMM8, Vs, Vd
VSUBB.SAT Vt, Vs, Vd
VSUBBU.SAT Vt, Vs, Vd D[i] = S[i] - S[i], i = 0:7
D[i] = S[i] - #IMM8, i = 0:7
D[i] = sat8(S[i] - T[i]), i = 0:7
D[i] = usat8(S[i] - T[i]), i = 0:7, unsigned Subtraction i8 = i8 - i8 signed (unsigned u8-u8→u8),
Optional saturation VSUBB.SCL Vt, Vs, Vd
VSUBB.SCL.RND Vt, Vs, Vd
VSUBB.SCL.RND.SAT Vt, Vs, Vd D[i] = (S[i] - T[i]) >> 1, i = 0:7
D[i] = rnd(S[i] - T[i]) >> 1, i = 0:7
D[i] = sat8(rnd(S[i] - T[i]) >> 1), i = 0:7 Subtraction i8 = i8 - i8 signed,
Optional rounding and saturation Vector operations for calculating the absolute value VABSD Vs, Vd
VABSD.SAT Vs, Vd D[i] = abs(S[i]), i=0
D[i] = sat64(abs(S[i])), i=0 Whole module, i64, with optional saturation VABSL Vs, Vd
VABSL.SAT Vs, Vd D[i] = abs(S[i]), i=0:1
D[i] = sat32(abs(S[i])), i=0:1 Whole module, i32, with optional saturation VABSH Vs, Vd
VABSH.SAT Vs, Vd D[i] = abs(S[i]), i=0:3
D[i] = sat16(abs(S[i])), i=0:3 Whole module, i16, with optional saturation VABSB Vs, Vd
VABSB.SAT Vs, Vd D[i] = abs(S[i]), i=0:7
D[i] = sat8(abs(S[i])), i=0:7 Whole module, i8, with optional saturation Vector Integer Maximum/Minimum Operations VMAXD Vt, Vs, Vd
VMAXDU Vt, Vs, Vd D[i] = max(T[i], S[i]), i=0
D[i] = umax(T[i], S[i]), i=0 Element Max, i64, u64 VMAXL Vt, Vs, Vd
VMAXLU Vt, Vs, Vd D[i] = max(T[i], S[i]), i=0:1
D[i] = umax(T[i], S[i]), i=0:1 Element maximum, i32, u32 VMAXH Vt, Vs, Vd
VMAXHU Vt, Vs, Vd D[i] = max(T[i], S[i]), i=0:3
D[i] = umax(T[i], S[i]), i=0:3 Element maximum, i16, u16 VMAXB Vt, Vs, Vd
VMAXBU Vt, Vs, Vd D[i] = max(T[i], S[i]), i=0:7
D[i] = umax(T[i], S[i]), i=0:7 Element Max, i8, u8 VMIND Vt, Vs, Vd
VMINDU Vt, Vs, Vd D[i] = min(T[i], S[i]), i=0
D[i] = umin(T[i], S[i]), i=0 Element minimum, i64, u64 VMINL Vt, Vs, Vd
Vminlu Vt, Vs, Vd D[i] = min(T[i], S[i]), i=0:1
D[i] = umin(T[i], S[i]), i=0:1 Element minimum, i32, u32 VMINH Vt, Vs, Vd
VMINHU Vt, Vs, Vd D[i] = min(T[i], S[i]), i=0:3
D[i] = umin(T[i], S[i]), i=0:3 Element minimum, i16, u16 VMINB Vt, Vs, Vd
VMINBU Vt, Vs, Vd D[i] = min(T[i], S[i]), i=0:7
D[i] = umin(T[i], S[i]), i=0:7 Element minimum, i8, u8 VMAX2L Vt, Vs, Vd
VMAX2LU Vt, Vs, Vd D[0] = T[0]; then D[i] = max(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = maxu(D[0], S[i]), i=0, …, n-1 Search for current maximum, i32/u32, n=2 VMAX4H Vt, Vs, Vd
VMAX4HU Vt, Vs, Vd D[0] = T[0]; then D[i] = max(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = maxu(D[0], S[i]), i=0, …, n-1 Search for the current maximum, i16/u16, n=4 VMAX8B Vt, Vs, Vd
VMAX8BU Vt, Vs, Vd D[0] = T[0]; then D[i] = max(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = maxu(D[0], S[i]), i=0, …, n-1 Search for the current maximum, i8/u8, n=8 VMIN2L Vt, Vs, Vd
VMIN2LU Vt, Vs, Vd D[0] = T[0]; then D[i] = min(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = minu(D[0], S[i]), i=0, …, n-1 Current low search, i32/u32, n=2 VMIN4H Vt, Vs, Vd
VMIN4HU Vt, Vs, Vd D[0] = T[0]; then D[i] = min(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = minu(D[0], S[i]), i=0, …, n-1 Finding the current low, i16/u16, n=4 VMIN8B Vt, Vs, Vd
VMIN8BU Vt, Vs, Vd D[0] = T[0]; then D[i] = min(D[0], S[i]), i=0, …, n-1
D[0] = T[0]; then D[i] = minu(D[0], S[i]), i=0, …, n-1 Finding the current low, i8/u8, n=8 Vector boolean operations VAND Vt, Vs, Vd D=T&S Element-by-element logical "AND", i8 VANDC Vt, Vs, Vd
Vandi Vt, Vs, Vd D = ~T&S
D=~(T&S) Element-by-element logical "AND" with inversion
one of the operands or the result, i8 VOR Vt, Vs, Vd D= T | S Element-by-element logical "OR", i8 VORC Vt, Vs, Vd
VORI Vt, Vs, Vd D = ~T | S
D=~(T|S) Element-by-element logical "OR" with inversion
one of the operands or the result, i8 VEOR Vt, Vs, Vd D=T^S Element-by-element logical exclusive "OR", i8 VNOT Vs, Vd D = ~S Element-wise negation of the result, i8

Tab. eleven.

Command mnemonic Formula Description Vector Floating-Point Add/Subtract VHADD Vt, Vs, Vd VT = {T3, T2, T1, T0}
VS = {S3, S2, S1, S0}
VD = {S3 + T2, S2 + T3, S1 + T0, S0 + T1} Adding two numbers, f16 + f16 → f16 VFADD Vt, Vs, Vd VT = {T1, T0}
VS = {S1, S0}
Vd={S1 + T1, S0 + T0} Adding two numbers, f32 + f32 → f32 VDADD Vt, Vs, Vd VT = {T0}
VS = {S0}
Vd = {S0 + T0} Adding two numbers, f64 + f64 → f64 VHSUB Vt, Vs, Vd VT = {T3, T2, T1, T0}
VS = {S3, S2, S1, S0}
VD = {S3 - T2, S2 - T3, S1 - T0, S0 - T1} Subtraction of two numbers, f16 - f16 → f16 VFSUB Vt, Vs, Vd VT = {T1, T0}
VS = {S1, S0}
Vd = {S1 - T1, S0 - T0} Subtraction of two numbers, f32 ‒ f32 → f32 VDSUB Vt, Vs, Vd VT = {T0}
VS = {S0}
Vd = {S0 - T0} Subtraction of two numbers, f64 - f64 → f64 Floating Point Vector Maximum/Minimum Operations VHMAX Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, i=0…3
D[i] = max(T[i], S[i]) Maximum of two numbers, f16 VFMAX Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, i=0…1
D[i] = max(T[i], S[i]) Maximum of two numbers, f32 VDMAX Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, i=0
D[i] = max(T[i], S[i]) Maximum of two numbers, f64 VHMIN Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, f16, i=0…3
D[i] = min(T[i], S[i]) Minimum of two numbers, f16 VFMIN Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, i=0…1
D[i] = min(T[i], S[i]) Minimum of two numbers, f32 VDMIN Vt, Vs, Vd Vt={T[i]}, Vs={S[i]}, Vd={D[i]}, i=0
D[i] = min(T[i], S[i]) Minimum of two numbers, f64

Tab. 12.

Command mnemonic Formula Description Vector operations of integer multiplication VMPYB T, S, D T = {8{i8}} = {T7,…,T0};
S = {8{i8}} = {S7,…,S0};
D = {8{i16}} = {D7,…,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0:7; Multiplication, integer, signed.
[i16 = i8 ⋅ i8] VMPYBU T, S, D T = {8{u8}} = {T7,…,T0};
S = {8{u8}} = {S7,…,S0};
D = {8{u16}} = {D7,…,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0:7; Multiplication, integer, unsigned.
[u16 = u8 ⋅ u8] VMPYH T, S, D T = {4{i16}} = {T3,…,T0};
S = {4{i16}} = {S3,…,S0};
D = {4{i32}} = {D3,…,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0:3; Multiplication, integer, signed.
[i32 = i16 ⋅ i16] VMPYHU T, S, D T = {4{u16}} = {T3,…,T0};
S = {4{u16}} = {S3,…,S0};
D = {4{u32}} = {D3,…,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0:3; Multiplication, integer, unsigned.
[u32 = u16 ⋅ u16] VMPYL T, S, D T = {2{i32}} = {T1,T0};
S = {2{i32}} = {S1,S0};
D = {2{i64}} = {D1,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0.1; Multiplication, integer, signed.
[i64 = i32 ⋅ i32] VMPYLU T, S, D T = {2{u32}} = {T1,T0};
S = {2{u32}} = {S1,S0};
D = {2{u64}} = {D1,D0} = {D1,D0};
Di = Ti ⋅ Si; i = 0.1; Multiplication, integer, unsigned.
[u64 = u32 ⋅ u32] VMPYD T, S, D T = {i64};
S = {i64};
D = {i128} = {D1,D0};
D = T ⋅ S; Multiplication, integer, signed.
[i128 = i64 ⋅ i64] VMPYDU T, S, D T = {u64};
S = {u64};
D = {u128} = {D1,D0};
D = T ⋅ S; Multiplication, integer, unsigned.
[u128 = u64 ⋅ u64] Vector operations of integer multiplication with accumulation in the accumulator VMPACBB T, S
VMPACBB T, S, VAd T = {8{i8}} = {T7,…,T0};
S = {8{i8}} = {S7,…,S0};
AC = {8{i32}} = {AC7,…,AC0};
ACi += Ti ⋅ Si; i = 0:7; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i32 += i8 ⋅ i8] VMPACBB T, S
VMPACBB T, S, VAd T = {8{u8}} = {T7,…,T0};
S = {8{i8}} = {S7,…,S0};
AC = {8{i32}} = {AC7,…,AC0};
ACi += Ti ⋅ Si; i = 0:7; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i32 += u8 ⋅ i8] VMPACBH T, S
VMPACBH T, S, VAd T = {4{0, i8}} = {0,T3,…,0,T0};
S = {4{i16}} = {S3,…,S0};
AC = {4{i64}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0:3; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i64 += i8 ⋅ i16] VMPACBUH T, S
VMPACBUH T, S, VAd T = {4{0,u8}} = {0,T3,…,0,T0};
S = {4{i16}} = {S3,…,S0};
AC = {4{i64}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0:3; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i64 += u8 ⋅ i16] VMPACHH T, S
VMPACHH T, S, VAd T = {4{i16}} = {T3,…,T0};
S = {4{i16}} = {S3,…,S0};
AC = {4{i64}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0:3; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i64 += i16 ⋅ i16] VMPACHUH T, S
VMPACHUH T, S, VAd T = {4{u16}} = {T3,…,T0};
S = {4{i16}} = {S3,…,S0};
AC = {4{i64}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0:3; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i64 += u16 ⋅ i16] VMPACLL T, S
VMPACLL T, S, VAd T = {2{i32}} = {T1,T0};
S = {2{i32}} = {S1,S0};
AC = {4{i64}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0.2; Multiplication with accumulation in the accumulator, integer, signed.
The two-address form implicitly uses VA0.
[i64 += i32 ⋅ i32] Vector floating point multiplications VHMPY T, S, D T = {4{f16}} = {T3,…,T0};
S = {4{f16}} = {S3,…,S0};
D = {4{f16}} = {D3,…,D0};
Di = Ti ⋅ Si; i = 0:3; Multiplication, half precision floating point numbers.
[f16 = f16 ⋅ f16] VFMPY T, S, D T = {2{f32}} = {T1,T0};
S = {2{f32}} = {S1,S0};
D = {2{f32}} = {D1,D0};
Di = Ti ⋅ Si; i = 0.1; Multiplication, single precision floating point numbers.
[f32 = f32 ⋅ f32] VDMPY T, S, D T = {f64};
S = {f64};
D = {f64};
D = T ⋅ S; Multiplication, double precision floating point numbers.
[f64 = f64 ⋅ f64] Vector Floating Point Multiplications with Accumulator Accumulator VHMPAC T, S
VHMPAC T, S, VAd T = {4{f16}} = {T3,…,T0};
S = {4{f16}} = {S3,…,S0};
AC = {4{f32}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0:3;
[f32 += f32(f16 ⋅ f16)] Multiplication with accumulation, half-precision floating point numbers. Multiplication and addition of products is performed in the f16 bit grid, then the result is expanded to f32 and accumulated in the f32 accumulator.
The two-address form implicitly uses VA0. VFMPAC T, S
VFMPAC T, S, VAd T = {2{f32}} = {T1,T0};
S = {2{f32}} = {S1,S0};
AC = {2{f32}} = {AC1,AC0};
ACi += Ti ⋅ Si; i = 0.1; Multiplication with accumulation, single precision floating point numbers.
The two-address form implicitly uses VA0.
[f32 += f32 ⋅ f32] VFMPAC4 T, S
VFMPAC4 T, S, VAd T = {T', T} = {4{f32}} = {T3,T2,T1,T0};
S = {S', S} = {4{f32}} = {S3,S2,S1,S0};
AC = {4{f32}} = {AC3,…,AC0};
ACi += Ti ⋅ Si; i = 0.3; Multiplication with accumulation, single precision floating point numbers.
The two-address form implicitly uses VA0.
[f32 += f32 ⋅ f32]
Adjacent input registers are used: R'[i] = R[i^1]. VDMPAC T, S
VDMPAC T, S, VAd T = {1{f64}} = {T0};
S = {1{f64}} = {S0};
AC = {1{f64}} = {AC0};
ACi += Ti ⋅ Si; i = 0; Multiplication with accumulation, double precision floating point numbers.
The two-address form implicitly uses VA0.
[f64 += f64 ⋅ f64] VDMPAC2 T, S
VDMPAC2 T, S, VAd T = {T', T} = {2{f64}} = {T1, T0};
S = {S', S} = {2{f64}} = {S1, S0};
AC = {2{f64}} = {AC1,AC0};
ACi += Ti ⋅ Si; i = 0…1; Multiplication with accumulation, double precision floating point numbers.
The two-address form implicitly uses VA0.
[f64 += f64 ⋅ f64]
Adjacent input registers are used: R'[i] = R[i^1].

Tab. 13.

Command mnemonic Formula Description Vector shift operations VASRD Vt(#u5),Vs, Vd D[i] = S[i] >> T[i], i=0
D[i] = S[i] >>#IMM5, i=0 Arithmetic right shift, i64 VLSLD Vt(#u5),Vs, Vd D[i] = S[i] << T[i], i=0
D[i] = S[i] <<#IMM5, i=0 Shift left, i64 VLSRD Vt(#u5),Vs, Vd D[i] = S[i] >>> T[i], i=0
D[i] = S[i] >>>#IMM5, i=0 Logical shift right, i64 VASRD.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >> T[i]) Arithmetic right shift with rounding, i64 VLSRD.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >>> T[i]) Logical right shift with rounding, i64 VASRL Vt(#u5),Vs, Vd D[i] = S[i] >> T[i], i=0:1
D[i] = S[i] >>#IMM5, i=0:1 Arithmetic right shift, i32 VLSLL Vt(#u5),Vs, Vd D[i] = S[i] << T[i], i=0:1
D[i] = S[i] <<#IMM5, i=0:1 Shift left, i32 VLSRL Vt(#u5),Vs, Vd D[i] = S[i] >>> T[i], i=0:1
D[i] = S[i] >>>#IMM5, i=0:1 Logical right shift, i32 VASRL.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >> T[i]), i=0…1 Arithmetic right shift with rounding, i32 VLSRL.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >>> T[i]), i=0…1 Logical right shift with rounding, i32 VASRH Vt(#u5),Vs, Vd D[i] = S[i] >> T[i], i=0:3
D[i] = S[i] >>#IMM5, i=0:3 Arithmetic right shift, i16 VLSLH Vt(#u5),Vs, Vd D[i] = S[i] << T[i], i=0:3
D[i] = S[i] <<#IMM5, i=0:3 Shift left, i16 VLSRH Vt(#u5),Vs, Vd D[i] = S[i] >>> T[i], i=0:3
D[i] = S[i] >>>#IMM5, i=0:3 Logical shift right, i16 VASRH.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >> T[i]), i=0:3 Arithmetic right shift with rounding, i16 VLSRH.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(S[i] >>> T[i]), i=0:3 Logical right shift with rounding, i16 VASRB Vt(#u5),Vs, Vd D[i] = S[i] >> T[i], i=0:7
D[i] = S[i] >>#IMM5, i=0:7 Arithmetic right shift, i8 VLSLB Vt(#u5),Vs, Vd D[i] = S[i] << T[i], i=0:7
D[i] = S[i] <<#IMM5, i=0:7 Shift left, i8 VLSRB Vt(#u5),Vs, Vd D[i] = S[i] >>> T[i], i=0:7
D[i] = S[i] >>>#IMM5, i=0:7 Logical shift right, i8 VASRB.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(D[i] >> T[i]), i=0:7 Arithmetic right shift with rounding, i8 VLSRB.RND Vt(#u5),Vs, Vd If(T[i] == 0) D[i]= S[i]
Else D[i] = RND(D[i] >>> T[i]), i=0:7 Logical right shift with rounding, i8

Tab. fourteen.

Command mnemonic Formula Description Vector extension operations of integer types VCVBHEU Vs, Vd
VCVBHOU Vs, Vd
VCVBHE Vs, Vd
VCVBHO Vs, Vd Vs = {S7…S0}, i8
Vd = {D3…D0}, i16
D[i]=zext _8→16 (S[2i+0]), i=0…3
D[i]=zext _8→16 (S[2i+1]), i=0…3
D[i] = sext _8→16 (S[2i+0]), i=0…3
D[i] = sext _8→16 (S[2i+1]), i=0…3 Sign expansion i8→i16 or zero expansion u8→u16. The even or odd elements of the first operand are used as the source. VCVHLEU Vs, Vd
VCVHLOU Vs, Vd
VCVHLE Vs, Vd
VCVHLO Vs, Vd Vs = {S3…S0}, i16
Vd = {D1…D0}, i32
D[i]=zext _16→32 (S[2i+0]), i=0…1
D[i]=zext _16→32 (S[2i+1]), i=0…1
D[i]=sext _16→32 (S[2i+0]), i=0…1
D[i]=sext _16→32 (S[2i+1]), i=0…1 Sign expansion i16→i32 or zero expansion u16→u32. The even or odd elements of the first operand are used as the source. VCVLDEU Vs, Vd
VCVLDOU Vs, Vd
VCVLDE Vs, Vd
VCVLDO Vs, Vd Vs = {S1…S0}, i32
Vd = {D0}, i64
D[i]=zext _32→64 (S[2i+0]), i=0…1
D[i]=zext _32→64 (S[2i+1]), i=0…1
D[i]=sext _32→64 (S[2i+0]), i=0…1
D[i]=sext _32→64 (S[2i+1]), i=0…1 Sign expansion i32→i64 or zero expansion u32→u64. The even or odd elements of the first operand are used as the source. Vector Truncation Operations on Integer Types VSATDL Vt, Vs, Vd Vt = {T0}, i64
Vs = {S0}, i64
Vd = {sat32(S0), sat32(T0)}, i32 Forced saturation, i64 → i32 VSATDLU Vt, Vs, Vd Vt = {T0}, i64
Vs = {S0}, i64
Vd = {usat32(S0), usat32(T0)}, u32 Forced saturation, i64 → u32 VSATLH Vt, Vs, Vd Vt = {T1, T0}, i32
Vs = {S1, S0}, i32
Vd = {sat16(S1), sat16(T1), sat16(S0), sat16(T0)}, i16 Forced saturation, i32 → i16 VSATLHU Vt, Vs, Vd Vt = {T1, T0}, i32
Vs = {S1, S0}, i32
Vd = {usat16(S1), usat16(T1), usat16(S0), usat16(T0)}, u16 Forced saturation, i32 → u16 VSATHB Vt, Vs, Vd Vt = {T3, T2, T1, T0}, i16
Vs = {S3, S2, S1, S0}, i16
Vd = {sat8(S3), sat8(T3), …, sat8(S0), sat8(T0)}, i8 Forced saturation, i16 → i8 VSATHBU Vt, Vs, Vd Vt = {T3, T2, T1, T0}, i16
Vs = {S3, S2, S1, S0}, i16
Vd = {usat8(S3), usat8(T3), …,u sat8(S0), usat8(T0)},u8 Forced saturation, i16 → u8 Vector floating-point type conversions VFDCV Vt, VVd Vt = {T1, T0}, f32
VVd = {Vd', Vd} = {{D1}, {D0}}, f64
Di = Ti, i = 0…1 Convert from float32 to float64 VDFCV Vt, Vs, Vd Vt = {T0}, f64
Vs = {S0}, f64
Vd = {D1, D0}, f32
D1 = S0, D0 = T0 Convert from float64 to float32 VHFCV Vt, VVd Vt = {T3, T2, T1, T0}, f16
VVd = {Vd', Vd} = {{D3, D1}, {D2, D0}}, f32
Di = Ti, i = 0…1 Convert from float16 to float32 VFHCV Vt, Vs, Vd Vt = {T1, T0}, f64
Vs = {S1, S0}, f64
Vd = {D3, D2, D1, D0}, f32
D3=S1, D2=T1, D1=S0, D0=T0 Convert from float32 to float16 Vector Type Conversion Operations INT->FLT VCVDF Vt, Vs, Vd Vt = {T0}, i64
Vs = {S0}, i64
Vd = {D1, D0}, f32
D1 = S0, D0 = T0 Convert from i64 to float32 VCVDFU Vt, Vs, Vd Vt = {T0}, u64
Vs = {S0}, u64
Vd = {D1, D0}, f32
D1 = S0, D0 = T0 Convert from u64 to float32 VCVDD Vt, Vd Vt = {T0}, i64
Vd = {D0}, f64
D0 = T0 Convert from i64 to float64 VCVDDU Vt, Vd Vt = {T0}, u64
Vd = {D0}, f64
D0 = T0 Convert from u64 to float64 VCVIF Vt, Vd Vt = {T1, T0}, i32
Vd = {D1, D0}, f32
D1=T1, D0=T0 Convert from i32 to float32 VCVIFU Vt, Vd Vt = {T1, T0}, u32
Vd = {D1, D0}, f32
D1=T1, D0=T0 Convert from u32 to float32 VCVID Vt, VVd Vt = {T1, T0}, i32
Vd = {Vd', Vd] = {{D1}, {D0}}, f64
D1=T1, D0=T0 Convert from int32 to float64 VCVIDU Vt, VVd Vt = {T1, T0}, u32
Vd = {Vd', Vd] = {{D1}, {D0}}, f64
D1=T1, D0=T0 Convert from uint32 to float64 VCVHF Vt, VVd Vt = {T3, T2, T1, T0}, i16
Vd = {Vd', Vd] = {{D3, D1}, {D2, D0}}, f64
D3=T3, D2=T2, D1=T1, D0=T0 Convert from i16 to float32 VCVHFU Vt, VVd Vt = {T3, T2, T1, T0}, u16
Vd = {Vd', Vd} = {{D3, D1}, {D2, D0}}, f64
D3=T3, D2=T2, D1=T1, D0=T0 Convert from u16 to float32 VCVIH Vt, Vs, Vd Vt = {T1, T0}, i32
Vs = {S1, S0}, i32
Vd = {D3, D2, D1, D0}, f16
D3=S1, D2=T1, D1=S0, D0=T0 Convert from i32 to float16 VCVIHU Vt, Vs, Vd Vt = {T1, T0}, u32
Vs = {S1, S0}, u32
Vd = {D3, D2, D1, D0}, f16
D3=S1, D2=T1, D1=S0, D0=T0 Convert from u32 to float16 VCVLINHF Vt, Vd Vt = {T3, T2, T1, T0}, i16
Vd = {Vd', Vd] = {{D3, D2}, {D1, D0}}, f64
D3=T3, D2=T2, D1=T1, D0=T0 Convert from i16 to float32 VCVLINHFU Vt, VVd Vt = {T3, T2, T1, T0}, u16
Vd = {Vd', Vd} = {{D3, D2}, {D1, D0}}, f64
D3=T3, D2=T2, D1=T1, D0=T0 Convert from u16 to float32 VCVHH Vt, Vd Vt = {T3, T2, T1, T0}, i16
Vd = {D3, D2, D1, D0}, f16
D3=T3, D2=T2, D1=T1, D0=T0 Convert from i16 to float16 VCVHHU Vt, Vd Vt = {T3, T2, T1, T0}, u16
Vd = {D3, D2, D1, D0}, f16
D3=T3, D2=T2, D1=T1, D0=T0 Convert from u16 to float16 Vector Type Conversion Operations FLT ->INT VHCVH Vt, Vd
VHCVH.floor Vt, Vd
VHCVH.round Vt, Vd
VHCVH.ceil Vt, Vd
VHCVH.trunc Vt, Vd Vt = {T3, T2, T1, T0}, f16
Vd = {D3, D2, D1, D0}, i16
D3=T3, D2=T2, D1=T1, D0=T0 Convert from float16 to i16
Optional rounding, forced saturation VHCVHU Vt, Vd
VHCVHU.floor Vt, Vd
VHCVHU.round Vt, Vd
VHCVHU.ceil Vt, Vd
VHCVHU.trunc Vt, Vd Vt = {T3, T2, T1, T0}, f16
Vd = {D3, D2, D1, D0}, u16
D3=T3, D2=T2, D1=T1, D0=T0 Convert from float16 to u16
Optional rounding, forced saturation VHCVI Vt, VVd Vt = {T3, T2, T1, T0}, f16
VVd = {Vd', Vd} = {{D3, D1}, {D2, D0}}, i32
D3=T3, D2=T2, D1=T1, D0=T0 Convert from float16 to i32, forced saturation VHCVIU Vt, VVd Vt = {T3, T2, T1, T0}, f16
VVd = {Vd', Vd} = {{D3, D1}, {D2, D0}}, u32
D3=T3, D2=T2, D1=T1, D0=T0 Float16 to u32 conversion, forced saturation VFCVD Vt, VVd Vt = {T1, T0}, f32
VVd = {Vd', Vd} = {{D1}, {D0}}, i64
D1=T1, D0=T0 float32 to i64 conversion, forced saturation VFCVDU Vt, VVd Vt = {T1, T0}, f32
VVd = {Vd', Vd} = {{D1}, {D0}}, u64
D1=T1, D0=T0 Float32 to u64 conversion, forced saturation VFCVI Vt, Vd
VFCVI.floor Vt, Vd
VFCVI.round Vt, Vd
VFCVI.ceil Vt, Vd
VFCVI.trunc Vt, Vd Vt = {T1, T0}, f32
VVd = {D1, D0}, i32
D1=T1, D0=T0 Convert from float32 to i32
Optional rounding, forced saturation VFCVIU Vt, Vd
VFCVIU.floor Vt, Vd
VFCVIU.round Vt, Vd
VFCVIU.ceil Vt, Vd
VFCVIU.trunc Vt, Vd Vt = {T1, T0}, f32
VVd = {D1, D0}, u32
D1=T1, D0=T0 Convert from float32 to u32
Optional rounding, forced saturation VDCVD Vt, Vd
VDCVD.floor Vt, Vd
VDCVD.round Vt, Vd
VDCVD.ceil Vt, Vd
VDCVD.trunc Vt, Vd Vt = {T0}, f64
VVd = {D0}, i64
D0 = T0 Convert from float64 to i64
Optional rounding, forced saturation VDCVDU Vt, Vd
VDCVDU.floor Vt, Vd
VDCVDU.round Vt, Vd
VDCVDU.ceil Vt, Vd
VDCVDU.trunc Vt, Vd Vt = {T0}, f64
VVd = {D0}, u64
D0 = T0 Convert from float64 to u64
Optional rounding, forced saturation VDCVI Vt, Vs, Vd Vt = {T0}, f64
Vs = {S0}, f64
VVd = {D1, D0}, i32
D1 = S0, D0 = T0 Convert from float64 to i32, forced saturation VDCVIU Vt, Vs, Vd Vt = {T0}, f64
Vs = {S0}, f64
VVd = {D1, D0}, u32
D1 = S0, D0 = T0 Float64 to u32 conversion, forced saturation VFCVH Vt, Vs, Vd
VFCVH.round Vt, Vs, Vd
VFCVH.trunc Vt, Vs, Vd
VFCVH.ceil Vt, Vs, Vd
VFCVH.floor Vt, Vs, Vd Vt = {T1, T0}, f32
Vs = {S1, S0}, f32
Vd = {D3, D2, D1, D0}, i16
D3=S1, D2=T1, D1=S0, D0=T0 Convert from float32 to i16
Optional rounding, forced saturation

Tab. fifteen.

Command mnemonic Description VREDD Vt, Vd Moving cross-section integer sum. In conditional execution, only the elements of the destination register highlighted by the predicate are written, while the summation proceeds sequentially over all elements.
Vt = {T[i].D}, Vd = {D[i].D}
D[i].D = sum(T[0].D, …, T[i].D), i=0…7 VREDRD Vt, Rd.D The operation of intersectional reduction by integer addition with the placement of the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the command is executed, zero is written to the result.
Vt = {T[i].D}, i=0…7
Rd.D = SUM(T[i]) VANDREDD Vt, Vd.D
VANDREDRD Vt, Rd.D The operation of cross-sectional reduction by logical "AND" with the reproduction of the result by the vector register or by placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = AND(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VORREDD Vt, Vd.D
VORREDRD Vt, Rd.D The operation of cross-sectional reduction by logical "OR" with the reproduction of the result in a vector register or placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = OR(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VEORREDD Vt, Vd.D
VEORREDRD Vt, Rd.D The operation of cross-sectional reduction by logical exclusive "OR" with the reproduction of the result in a vector register or placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = EOR(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VADDREDD Vt, Vd.D
VADDREDRD Vt, Rd.D The operation of intersectional reduction by integer addition with multiplication of the result in a vector register or placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = SUM(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VMAXREDD Vt, Vd.D
VMAXREDRD Vt, Rd.D The operation of intersectional reduction by an integer signed maximum with the result multiplied by a vector register or by placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = MAX(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VMINREDD Vt, Vd.D
VMINREDRD Vt, Rd.D The operation of intersectional reduction by an integer signed minimum with the result multiplied by a vector register or by placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = MIN(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VMAXREDDU Vt, Vd.D
VMAXREDRDU Vt, Rd.D The operation of intersectional reduction by an integer unsigned maximum with the result multiplied by a vector register or by placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = MAX(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VMINREDDU Vt, Vd.D
VMINREDRDU Vt, Rd.D The operation of intersectional reduction by an integer unsigned minimum with the result multiplied by a vector register or by placing the result in a scalar register. In conditional execution, only the elements selected by the predicate should be added, the rest should be ignored. If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].D}, i=0…7
R = MINU(T[i])
Vector option:
Vd = {D[i]}, D[i].D = R, i64, i=0…7
Scalar option:
Rd.D = R VFADDRED Vt, Vd.L
VFADDREDR Vt, Rd.L Intersectional reduction operation on floating-point addition with multiplication of the result in a vector register or placing the result in a scalar register. From each vector section, only the least significant element is used.
In conditional execution, only the lower elements of each vector section selected by the predicate are fed to the input, all the highlighted output elements are written (not only the lower ones). If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].L}, i=0…15
R = FSUM(T[j*2]), j=0…7
Vector option:
Vd = {D[i]}, D[i].L = R, f32, i=0…15
Scalar option:
Rd.L = R VFMAXRED Vt, Vd.L
VFMAXREDR Vt, Rd.L The operation of intersectional reduction by the maximum floating point with the result multiplied by a vector register or by placing the result in a scalar register. From each vector section, only the least significant element is used.
In conditional execution, only the lower elements of each vector section selected by the predicate are fed to the input, all the highlighted output elements are written (not only the lower ones). If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].L}, i=0…15
R = FMAX(T[j*2]), j=0…7
Vector option:
Vd = {D[i]}, D[i].L = R, f32, i=0…15
Scalar option:
Rd.L = R VFMINRED Vt, Vd.L
VFMINREDR Vt, Rd.L The operation of cross-sectional reduction by the minimum of the floating point with the result multiplied by the vector register or by placing the result in a scalar register. From each vector section, only the least significant element is used.
In conditional execution, only the lower elements of each vector section selected by the predicate are fed to the input, all the highlighted output elements are written (not only the lower ones). If the condition is zero, the scalar instruction is executed and zero is written to the result.
Vt = {T[i].L}, i=0…15
R = FMIN(T[j*2]), j=0…7
Vector option:
Vd = {D[i]}, D[i].L = R, f32, i=0…15
Scalar option:
Rd.L = R

Tab. 16.

Command mnemonic Description VSHUFBH Vt, Vs, Vd Vt: = {T63,…, T2, T1, T0}, i8
Vs = {S63,…, S2, S1, S0}, i8
Vdi:={R31,…, R2, R1, R0}, u16
Vdo:={D31,…, D2, D1, D0}, i16
VV = {S63, …, S0, T63, …, T0}
Di = sext _8→16 (VV[R[i] & 0x7F]), i=0,1,…,31
Generic Intersectional Fetch Operation with Data Type Extension VSHUFBL Vt, Vs, Vd Vt: = {T63,…, T2, T1, T0}, i8
Vs = {S63,…, S2, S1, S0}, i8
Vdi:={R15,…, R2, R1, R0}, u32
Vdo:={D15,…, D2, D1, D0}, i32
VV = {S63, …, S0, T63, …, T0}
Di = sext _8→32 (VV[R[i] & 0x7F]), i=0,1,…,31
Generic intersectional fetch operation with data type extension.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFHL Vt, Vs, Vd Vt = {T31,…, T2, T1, T0}, i16
Vs = {S31,…, S2, S1, S0}, i16
Vdi:={R15,…, R2, R1, R0}, u32
Vdo:={D15,…, D2, D1, D0}, i32
VV = {S31, …, S0, T31, …, T0}
Di = sext _16→32 (VV[R[i] & 0x3F]), i=0,1,…,15
Generic intersectional fetch operation with data type extension.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFBHU Vt, Vs, Vd Vt: = {T63,…, T2, T1, T0}, u8
Vs = {S63,…, S2, S1, S0}, u8
Vdi:={R31,…, R2, R1, R0}, u16
Vdo:={D31,…, D2, D1, D0}, u16
VV = {S63, …, S0, T63, …, T0}
Di = zext _8→16 (VV[R[i] & 0x7F]), i=0,1,…,31
Generic intersectional fetch operation with data type extension.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFBLU Vt, Vs, Vd Vt: = {T63,…, T2, T1, T0}, u8
Vs = {S63,…, S2, S1, S0}, u8
Vdi:={R15,…, R2, R1, R0}, u32
Vdo:={D15,…, D2, D1, D0}, u32
VV = {S63, …, S0, T63, …, T0}
Di = zext _8→32 (VV[R[i] & 0x7F]), i=0,1,…,31
Generic intersectional fetch operation with data type extension.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFHLU Vt, Vs, Vd Vt = {T31,…, T2, T1, T0}, u16
Vs = {S31,…, S2, S1, S0}, u16
Vdi:={R15,…, R2, R1, R0}, u32
Vdo:={D15,…, D2, D1, D0}, u32
VV = {S31, …, S0, T31, …, T0}
Di = zext _16→32 (VV[R[i] & 0x3F]), i=0,1,…,15
Generic intersectional fetch operation with data type extension.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFHB Vt, Vs, Vd Vt: = {T31…, T2, T1, T0}, i16
Vs = {S31…, S2, S1, S0}, i16
Vdi: = {R63…, R2, R1, R0}, u8
Vdo: = {D63…, D2, D1, D0}, i8
VV = {S31, …, S0, T31, …, T0}
Di = sat _i16→i8 (VV[R[i] & 0x3F]), i=0,1,…,63
A universal intersectional fetch operation with forced saturation signed → signed to a smaller data type.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFLB Vt, Vs, Vd Vt = {T15…, T2, T1, T0}, i31
Vs = {S15…, S2, S1, S0}, i31
Vdi: = {R63…, R2, R1, R0}, u8
Vdo: = {D63…, D2, D1, D0}, i8
VV = {S15, …, S0, T15, …, T0}
Di = sat _i32→u8 (VV[R[i] & 0x1F]), i=0,1,…,63
A universal intersectional fetch operation with forced saturation signed → signed to a smaller data type.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFLH Vt, Vs, Vd Vt: = {T15…, T2, T1, T0}, i32
Vs = {S15…, S2, S1, S0}, i32
Vdi: = {R31…, R2, R1, R0}, u16
Vdo: = {D31…, D2, D1, D0}, i16
VV = {S15, …, S0, T15, …, T0}
Di = sat _i32→i16 (VV[R[i] & 0x1F]), i=0,1,…,31
A universal intersectional fetch operation with forced saturation signed → signed to a smaller data type.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFHBU Vt, Vs, Vd Vt: = {T31…, T2, T1, T0}, u16
Vs = {S31…, S2, S1, S0}, u16
Vdi: = {R63…, R2, R1, R0}, u8
Vdo: = {D63…, D2, D1, D0}, u8
VV = {S31, …, S0, T31, …, T0}
Di = sat _i16→u8 (VV[R[i] & 0x3F]), i=0,1,…,63
A generic cross-sectional fetch operation with forced saturation signed → unsigned to a smaller data type.
The former values of the Vd register are taken as indexes, the result is written to it. VSHUFLBU Vt, Vs, Vd Vt = {T15…, T2, T1, T0}, u31
Vs = {S15…, S2, S1, S0}, u31
Vdi: = {R63…, R2, R1, R0}, u8
Vdo: = {D63…, D2, D1, D0}, u8
VV = {S15, …, S0, T15, …, T0}
Di = sat _i32→u8 (VV[R[i] & 0x1F]), i=0,1,…,63
A generic cross-sectional fetch operation with forced saturation signed → unsigned to a smaller data type.
The previous values of the Vd register are taken as indices, the result is written to it. VSHUFLHU Vt, Vs, Vd Vt: = {T15…, T2, T1, T0}, u32
Vs = {S15…, S2, S1, S0}, u32
Vdi: = {R31…, R2, R1, R0}, u16
Vdo: = {D31…, D2, D1, D0}, u16
VV = {S15, …, S0, T15, …, T0}
Di = sat _i32→u16 (VV[R[i] & 0x1F]), i=0,1,…,31
A generic cross-sectional fetch operation with forced saturation signed → unsigned to a smaller data type.
The previous values of the Vd register are taken as indices, the result is written to it.

Tab. 17.

Command mnemonic Description VLUT0 Vt, Vs, Vr, Vd
VLUT1 Vt, Vs, Vr, Vd VLUTa T, S, R, D
Vt = {T63…, T2, T1, T0}, u8
Vs = {S63…, S2, S1, S0}, u8
Vr = {R63…, R2, R1, R0}, u8
Vd = {D63…, D2, D1, D0}, u8
VV = {R63, …, R0, S63, …, S0}, u8
if (T[7] == a) then Di = VV[T[i] & 0x7F], i=0,1,…,63
a - integer 1-bit parameter that can take values: 0, 1;
T, S, R - input 512-bit vectors;
D is an output 512-bit vector.
The input and output vectors are divided into 64 bytes. The vector VV: = {Vr, Vs} contains a lookup table, more precisely, half of this lookup table, the complete lookup table is contained in two vectors VV corresponding to two values of the parameter a. The ST vector contains the data to be converted.
The choice of data from the table for each byte ti of the vector T (i = 0,1,…,63) is determined by its least significant seven bits according to the formula: di = SVV[ti[6:0]].
A feature of the VLUT command is that, in addition to the output vector itself, it also forms a byte-by-byte recording mask for this vector according to the formula: mi = (ti[7]== a). Thus, only data from the desired table is written to the output register D.

Tab. eighteen.

Command mnemonic Description VHIST0 Vs, Vd
VHIST1 Vs, Vd
VHIST2 Vs, Vd
VHIST3 Vs, Vd VHISTa S, D
a - integer 2-bit parameter that can take values: 0, 1, 2, 3;
S - input 512-bit vector;
D is an output 512-bit vector.
The input and output vector are divided into 64 bytes. For each i (i = 0,1,…,63) the number of bytes is calculated, the value of which is equal to (64*a + i), and this number is written to the i-th byte of the output vector.
To calculate a 256-level histogram, you must execute this command for all four values of the a parameter, then convert the resulting 64-component byte vectors with an extension to 16-bit or 32-bit unsigned integers, depending on the format in which the bins will be accumulated histograms, and accumulate.
Thus, to calculate histograms, vector type extension and integer addition instructions are also required. With compact code, it is possible to calculate a 256-level histogram for 64 pixels in about 6 cycles.
The four values of the a parameter can be implemented as four different commands. VHISTC0 Vs, VAd
VHISTC1 Vs, VAd
VHISTC2 Vs, VAd
VHISTC3 Vs, VAd The command is similar to VHIST*, only the result is accumulated in accumulators. Eight 32-bit unsigned accumulators are used in each vector section. It takes four accumulators to count the number of all input values.

Tab. 19.

Command mnemonic Description VPUSHD Vt, Vs, Vd Vt: = {T7…, T2, T1, T0}, u64
Vs = {S7…, S2, S1, S0}, u64
Vd = {S6, S5, S4, S3, S2, S1, S0, T7}
The operation of the circular intersectional shift by 8 bytes. The retrieved element S7 is lost.
With conditional execution, the command is executed in the normal mode, but only active elements are written according to the predicate condition. VPUSHRD Rt.D, Vs, Vd Vs = {S7…, S2, S1, S0}, u64
Vd = {S6, S5, S4, S3, S2, S1, S0, Rt}
Rt.D = S7.
8-byte ring intersection shift operation with transfer of the scalar register to the zero section. The retrieved element is returned to Rt.D.

Tab. twenty.

Claims (49)

1. A scalar vector processor 100 containing scalar and vector data processing channels 105 and 107 connected by a ring bus CDB 112, which are connected to the reduction unit VRED 104, as well as to the first level data memory DMEM/L1D $ 103, which is connected to the cache second-level memory L2$ 101, which is connected to the external interface of the processor, which has access to the external memory of the computing system, and is also connected to the first-level program memory PMEM/L1I$ 102, the output of which is connected to the input of the FETCH 109 command fetch unit, the output of which connected to the input of the command decoding block DECODE 110, the first output of which is connected to the inputs of the scalar and vector channels, and the second output is connected to the program control block PCTRL 111, the output of which is connected to the input of the program memory of the first level PMEM/L1I $ 102, and - the program memory of the first level PMEM/L1I$ 102 and the data memory of the first level DMEM/L1D$ 103 are made with the possibility of generating calls and transferring them to - cache memory of the second level L2$ 101, which is configured to serve calls from the program memory of the first level PMEM/L1I$ 102 and the data memory of the first level DMEM/L1D$ 103, as well as to load data via an external interface from the external memory of the computer system and transferring data to the first level data memory DMEM/L1D$ 103 and the first level program memory PMEM/L1I$ 102; - command fetch unit FETCH 109 is configured to fetch commands from program memory PMEM/L1I $ 102 and transfer them to - a command decoding unit DECODE 110, configured to decode commands and generate program control commands for the executive devices of the processor and transfer them to - a PCTRL block, which is configured to execute program control instructions. 2. The processor according to claim 1, characterized in that the first-level data memory DMEM/L1D$ 103 is made in the form of a first-level L1D$ cache memory or in the form of a tightly coupled TCM (Tightly-Coupled Memory) DMEM static memory. 3. The processor according to claim 1, characterized in that the first-level program memory PMEM/L1I$ 102 is made in the form of a first-level L1I$ cache memory or in the form of a tightly coupled TCM (Tightly-Coupled Memory) PMEM static memory. 4. The processor according to claim 1, characterized in that at the level of the computing core it has a Harvard architecture with the possibility of simultaneous access to the first level program memory PMEM/L1$ 102 and the first level data memory DMEM/L1D$ 103 via separate buses. 5. The processor according to claim. 1, characterized in that the cache memory of the second level L2 $ 101 has a von Neumann architecture. 6. The processor according to claim. 1, characterized in that the program control commands are selected from a set of commands containing program jump commands and program cycle commands. 7. The processor according to claim 1, characterized in that the commands are combined into instructions, which are organized in the form of a VLIW package 201 (VLIW - Very Long Instruction Word). 8. The processor according to claim 7, characterized in that the VLIW package 201 contains up to eight instructions, of which up to four instructions are for the scalar data processing channel agents and up to four instructions are for the vector data processing channel agents. 9. The processor according to claim 7, characterized in that the VLIW package 201 contains up to two scalar data exchange instructions and up to two vector data exchange instructions with the DMEM/L1D $ 103 data memory. 10. The processor according to claim 1, characterized in that it has a command system consisting of program control commands, commands of the actuators of the scalar data processing channel and the vector data processing channel, as well as commands of the VRED 104 reduction unit. 11. The processor according to claim. 1, characterized in that the scalar channel 105 contains one scalar computing section 106. 12. Processor according to claim. 1, characterized in that the scalar computing section 106 contains a scalar register file RF 301, which is multi-ported and which stores the processed scalar data. 13. Processor according to claim 12, characterized in that the scalar register file RF 301 contains ports associated with the scalar data processing channel 105 and configured to communicate with the data memory DMEM/L1D$ 103. 14. The processor according to claim 12, characterized in that the scalar register file RF 301 contains ports associated with the actuators of the scalar computing section 106 of the scalar data processing channel 105, configured to transmit initial data to perform computational operations and write the results of operations back to scalar register file RF 301. 15. The processor according to claim 1, characterized in that the scalar computing section 106 contains data processing units SLSE0 310, SLSE1 311, which are configured to provide data exchange between the DMEM/L1D $ 103 data memory and the RF 301 scalar register file, including including the execution of data transfer commands between the data memory DMEM/L1D $ 103 and the scalar register file RF301. 16. The processor according to claim 1, characterized in that the scalar computing section 106 contains data processing units ALU0 302, ALU1 303, ALU2 304, ALU3 305, performing arithmetic and logical operations on fixed-point numbers. 17. The processor according to claim 1, characterized in that the scalar computing section 106 contains data processing units FALU0 306, FALU1 307, performing arithmetic and logical operations on floating point numbers. 18. The processor according to claim. 1, characterized in that the scalar computing section 106 contains data processing units SMU0 308, SMU1 309, performing multiplication operations on fixed and floating point numbers. 19. The processor according to claim. 1, characterized in that the scalar computing section 106 contains a data processing unit SH 312 that performs logical and arithmetic shift operations. 20. The processor according to claim. 1, characterized in that the scalar computing section 106 contains a data processing unit CONV 315 that performs data type conversion operations. 21. The processor according to claim. 1, characterized in that the scalar computing section 106 contains a data processing unit DIV 313 that performs division operations. 22. The processor according to claim. 1, characterized in that the scalar computing section 106 includes a data processing unit MF 314, which performs the calculation of transcendental mathematical functions. 23. The processor according to claim. 1, characterized in that the vector channel 107 consists of several vector computing sections 108, the number of which corresponds to the capacity of the processed vector. 24. The processor according to claim 23, characterized in that the vector computing section 108 contains a vector register file VRF 401, which is multi-port and multi-format and which stores the processed vector data. 25. Processor according to claim 24, characterized in that the vector register file VRF 401 is multi-format, so that each 64-bit register 500 of the vector register file VRF 401 can store either one 64-bit value 501 or two 32-bit values 502 , or four 16-bit values 503, or eight 8-bit values 504. 26. The processor according to claim 24, characterized in that the VRF 401 vector register file contains ports associated with the external interface of the vector channel 107 and configured to exchange data with the DMEM/L1D $ 103 data memory. 27. The processor according to claim 24, characterized in that the VRF 401 vector register file contains ports associated with the execution devices of the vector computing section 108, configured to transmit initial data to perform computational operations and write the results back. 28. The processor according to claim 24, characterized in that the vector register file VRF 401 is configured to work with various data formats. 29. The processor according to claim 23, characterized in that the vector computing section 108 contains blocks VLSE0 412, VLSE1 413, which are configured to provide data exchange between the DMEM/L1D $ 103 data memory and the VRF 401 vector register file, including execution of data transfer commands between the data memory DMEM/L1D $ 103 and the vector register file VRF 401. 30. The processor according to claim 23, characterized in that the vector computing section 108 contains blocks VALU0 403, VALU1 404, VALU2 405, VALU3 406, configured to perform arithmetic and logical operations on fixed-point numbers. 31. The processor according to claim 23, characterized in that the vector computing section 108 contains blocks VFALU0 407, VFALU1 408, configured to perform arithmetic and logical operations on floating point numbers. 32. The processor according to claim 23, characterized in that the vector computing section 108 contains blocks VMU0 409, VMU1 410, configured to perform multiplication and multiplication-accumulation operations on fixed and floating point numbers. 33. The processor according to claim 23, characterized in that the vector computing section 108 contains a vector register file of accumulator registers VAC 402, configured to store data obtained and used as a result of performing multiplication with accumulation operations performed by vector multiplier units VMU0 409, VMU1 410. 34. The processor according to claim 23, characterized in that the vector computing section 108 contains a VSH 411 block, configured to perform logical and arithmetic shift operations on vector operands. 35. The processor according to claim 23, characterized in that the vector computing section 108 contains a VCONV 414 block, configured to perform a data type conversion operation on vector operands. 36. Processor according to claim. 1, characterized in that the reduction unit VRED 104 is configured to calculate reduction functions. 37. The processor according to claim 1, characterized in that the reduction unit VRED 104 is configured to calculate the reduction functions and, at the same time, implement the interaction functions of the scalar and vector parts of the processor in various operations in which the scalar channel 105 generates and / or consumes the scalar required and/or generated by the vector channel 107. 38. The processor according to claim. 1, characterized in that the reduction unit VRED 104 contains a RALU 601 unit, configured to perform arithmetic-logical intersectional reduction operations. 39. The processor according to claim. 1, characterized in that the reduction unit VRED 104 contains a block SHUFFLE 602, configured to perform cross-sectional permutations. 40. The processor according to claim. 1, characterized in that the reduction unit VRED 104 contains a LUT 603, configured to perform cross-sectional table transformations. 41. Processor according to claim. 1, characterized in that the reduction unit VRED 104 contains a block HIST 604 configured to perform histogram calculation operations. 42. The processor according to claim 1, characterized in that the CDB (Circular Data Bus) 112 is configured to exchange data simultaneously with the implementation of computational operations in the scalar and vector channels 105, 107 and in the reduction unit VRED 104. 43. The processor according to claim 1, characterized in that the ring bus CDB 112 is configured to implement cyclic shift commands, as a result of which the register Ri of the scalar register file RF 301 is shifted to the register Vj of the vector register file VRF 401 of the zero vector computing section 108: Vj.0=Ri; the register Vj of the vector register file VRF 401 of the senior (N-1) vector computing section 108 is shifted to the register Ri of the scalar register file RF 301: Ri=Vj.N-1; the registers Vj of the vector register files VRF 401 of the remaining vector computing sections 108 are shifted by one section towards the higher sections: Vj.k=Vj.k-1, k=1,2,…,N-1. 44. The processor according to claim 1, characterized in that the ring bus CDB 112 is configured to sequentially move data from the vector channel 107 to the scalar channel 105 in order to perform operations that are only available in the scalar channel 105, with the subsequent return of the converted data to the vector channel 107.

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