RU2568391C1 - Generator of sinusoidal signal - Google Patents

Abstract

FIELD: measurement equipment.

SUBSTANCE: generator of a sinusoidal signal comprises an N-digit summator, N-digit phase accumulator, a permanent memory, a digital-analogue converter, a device to generate a code of frequency of a generated signal F with capacity (N+M), a clock pulse oscillator, a device for conversion of a code of frequency of a generated signal F into a code of phase increment Δφ and into a code of clock frequency K in accordance with specified mathematical ratios of parameters.

EFFECT: expansion of a frequency range with preservation of summator and phase accumulator capacity and volume of permanent memory.

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Description

The present invention relates to automation and computer technology and can be used in measuring equipment for the synthesis of sinusoidal signals.

Known generator of a sinusoidal signal (High-speed synthesizer of sinusoidal signals of direct synthesis) [US Pat. 2326492 Russian Federation: Н03В 19/12. High-speed synthesizer of sinusoidal signals of direct synthesis / Bogatyrsky S.V., Goncharov A.V., Koluntaev E.N., Shelyapin E.S.- No. 2006142978/09; declared 12/04/2006; publ. 06/10/2008], comprising a frequency selection device, the outputs of which are connected to the first input of the first N-bit adder and the second input of the second N-bit adder, as well as serially connected clock generator and frequency divider into two, the outputs of which are connected to the third and second the inputs of the first, second and third shift registers, respectively. The output of the first register is connected to the first input of the second adder, the output of which is connected to the first input of the second register, to the first input of the third shift register and to the second input of the first adder, the output of which is connected to the first input of the first register. The output of the third register through the first read-only memory (ROM), and the output of the second register through the second ROM are connected respectively to the first and second inputs of the multiplexer, the output of which is connected to a digital-to-analog converter (DAC). The output of the frequency divider into two is connected to the third input of the multiplexer.

The disadvantage of this sinusoidal signal generator is that with an increase in the range of generated frequencies, the circuit becomes more complex due to an increase in the capacity of the adders, registers and an increase in the volume of the ROM.

A known generator of a sinusoidal signal (digital computer synthesizer) [US Pat. 3654450 USA: G06G 07/00, G06F 01/02, G06F 01/03, G06G 07/28, H03K 04/00, H03C 01/00, H03C 03/00, H03K 04/02, H04L 27/12, H04L 27 / 10, H04L 27/00, H04L 27/20, G06f 15/34. Digital signal generator synthesizer / Webb J. - No. 05/025,348; declared 04/03/1970; publ. 04/04/1970], which is the prototype of the invention and contains a series-connected device for generating the generated signal frequency code (UFC), an adder, a phase accumulator, the output of which is connected to the second input of the adder, ROM and DAC. A clock generator is connected to the clock input of the phase accumulator.

This sinusoidal signal generator operates as follows. The input of the adder connected to the UFK receives the value of the phase increment code Δφ at each clock cycle of the signal of the clock generator. At each cycle, the value from the output of the adder is latched into the phase accumulator. In this case, the code from the battery output goes to the second input of the adder. Thus, the value at the output of the battery is constantly increasing at each cycle of the clock signal. This happens until the adder overflows, after which the value at the output of the adder decreases abruptly and begins to increase again. As a result, at the battery output, we constantly have instantaneous phase values of the generated signal, i.e. instantaneous values of the function argument. Applying the table of values of the cosine function performed on the ROM, we convert the phase values into the amplitude values of the synthesized signal. Further, the value from the output of the ROM goes to the input of the DAC, which converts the amplitude code into an analog signal.

The code values of the phase increment Δφ are calculated by the formula (1):

$$\Delta \varphi =\frac{f_{out}\cdot 2^N}{f_G},(\mathrm{one})$$

where f _out is the frequency of the generated signal,

f _G is the pulse frequency of the clock generator,

N - bit capacity of the adder and battery.

The maximum frequency f _max generated by the device is equal to half the clock frequency of the circuit.

The disadvantage of the prototype is that when expanding the range of generated frequencies, the generator circuit becomes more complex due to an increase in the bit capacity of the adder and phase accumulator and an increase in the ROM volume.

This follows from the fact that the minimum generated frequency f _min is

$$f_{\min }=\frac{f_G}{2^N}.(2)$$

We obtain formula (2) by expressing from the formula (1) the frequency of the generated signal f _out and substituting the minimum phase increment equal to 1. As mentioned above, the maximum frequency is equal to half the clock frequency. Thus, while maintaining the same clock frequency, based on formula (2), we have that in order to expand the frequency range (decrease the minimum generated frequency), it is necessary to increase the bit capacity of the adder and battery. It should also be noted that the minimum generated frequency is also the value of the frequency tuning step Δf.

The objective (technical result) of the present invention is to expand the frequency range while maintaining the capacity of the adder and accumulator phase and volume of the ROM.

To achieve this goal, a sinusoidal signal generator containing a series-connected adder, a phase accumulator, the output of which is connected to the second input of the adder, ROM, DAC and low-pass filter, as well as a UVC and a clock pulse generator, is equipped with a conversion unit (UP) of the frequency code of the generated signal in the phase increment code and the clock frequency code according to a certain law (9), (10), (11), the input of which is connected to the output of the device for generating the frequency code of the generated signal, and its first output to the first input adder controlled divider (LE) clock pulse frequency, whose input is connected to the second output of the frequency code conversion device, its clock input connected to the output of the clock, the output - to an input of phase accumulator clock.

The drawing shows a functional diagram of the proposed device.

The proposed sinusoidal signal generator contains a series-connected UFK 1, UP 2, an adder (+) 3, a phase accumulator (A) 4, the output of which is connected to the second input of the adder 3, ROM 5, DAC 6, and a clock pulse generator (G) 7 , UD 8, the input of which is connected to the second output of unitary enterprise 2, and the clock input - with the output of the clock generator 7; the clock input of the battery 4 is connected to the output of the UD 8.

The sine wave generator operates as follows. The ligament operation algorithm: adder 3, phase 4 accumulator, ROM 5, DAC 6, is exactly the same as in the prototype. The difference is that the phase increment code Δφ is formed by UP 2, and the source of clock pulses of the battery 4 is the output of UD 8, on which the clock frequency f _CLK is:

$$f_{CLK}=\frac{f_G}{2^K},(3)$$

where K is the frequency code f _CLK , which comes from the UE 2 to the input of the UD 8 and takes integer values from 0 to M inclusive, M is the maximum value of the code K at which f _CLK takes the minimum value.

Moreover, replacing in the formula (1) f _G with f _CLK (since in the proposed generator of the sinusoidal signal the battery is clocked precisely by the frequency f _CLK ), we obtain:

$$\Delta \varphi =\frac{f_{out}\cdot 2^N}{f_{CLK}}.(\mathrm{four})$$

Substituting expression (3) in the formula (4), we have:

$$\Delta \varphi =\frac{f_{out}\cdot 2^N\cdot 2^K}{f_G}.(5)$$

It is possible to determine the dependence of the minimum possible output frequency of the generated signal f _min and, accordingly, the frequency tuning step Δf on K by expressing f _out from formula (5) and substituting a value of 1. instead of Δφ. Then we obtain:

$$\Delta f=f_{\min }=\frac{f_G}{2^N\cdot 2^K}.(6)$$

You can see that each value of the code K will have its own f _min and Δf.

If K = 0 (f _CLK takes the maximum value equal to f _G ), then the upper limit of the frequency range of the device is the same as for the prototype, and is equal to half the frequency of the clock pulses.

If K = M (f _CLK takes the maximum value equal to f _G / 2 ^M ), then substituting K = M in formula (6), we obtain:

$$f_{\min }=\frac{f_G}{2^{N+M}}.(7)$$

Thus, in the proposed sinusoidal signal generator, the upper limit of the frequency range of the generated signal is the same as for the prototype, and the lower limit is 2 ^M times smaller than that of the prototype, i.e. the frequency range is expanded by 2 ^M times.

From formula (5) it follows that in order for UFC 1 to be able to determine the code of the generated frequency F both for the minimum frequency of the range of generated frequencies and for the maximum, UFC 1 must have an output data bus with a resolution of (N + M). In this case, UFK 1 calculates the frequency of the output signal of the generator according to the formula

$$F=\frac{f_{out}\cdot 2^{N+M}}{f^G}.(8)$$

That is, UFC 1 calculates F in the same way that UFC 1 calculates Δφ in the prototype if the output data bus had a bit capacity (N + M).

The function of UP 2 is the conversion of the code F into the codes Δφ and K. This happens according to the following principle.

Initially, we derive the relationship between Δφ and F depending on f _CLK , i.e. from code K. Expressing f _out from formulas (5) and (8) and equating the resulting expressions, we have:

$$\Delta \varphi =\frac{F\cdot 2^K}{2^M}.(9)$$

This expression in the binary system means that in order to obtain Δφ the value of the code F must be shifted towards the higher digits by the number of digits equal to K (in this case, the bit depth of the obtained value as a result of this operation remains equal to (N + M)), then Δφ is numerically equal to the value N senior bits after this operation.

Thus, if f _CLK = f _G , then the lower M bits of the code F are ignored, and the value of the code Δφ is formed by the highest N bits of the code F. As f _CLK decreases, the number of ignored low bits decreases, and the number of ignored high bits starts to increase. When the code K reaches a maximum value equal to M, respectively, f _CLK = f _G / 2 ^M , the value of the code Δφ is formed by the lower N bits of the code F, and the highest M bits are ignored. As a result, we have that the value of the code Δφ is formed by the bits of the code F, starting from the least significant digit with the number (M-K) and ending with the highest digit with the number ((N + М-1) -K).

Based on this, we describe the principle of determining the value of the code K. It consists in the following: the code K is formed depending on the value of the number R, which is equal to the number of bits of the code F equal to logical zero, counting from the highest rank to the first bit equal to a logical unit, not including it. Strictly mathematically, the number R, depending on the value of the code F, can be calculated by the formula

where the brackets  refers to the operation of rounding down [R. Graham, D. Knut, O. Patashnik. Concrete math. The basis of computer science: Per. from English / ed. A.B. Khodulev; trans. V.V. Hike, A.B. Khodulev. - M .: Mir, 1998. - 703 s].

It should be noted that the number of bits of the code Δφ equal to zero, counting from the highest to the first bit equal to a logical unit, not including it, will be equal to (R-К). This follows from the relationship between the codes Δφ and F, which is described above.

If the value of R is less than the value of S set in the device, then the value of the code K is 0. S is a natural number whose value is determined from the considerations described below.

If the value of R is not less than the number S, then K is not 0. Moreover, the generator of the sinusoidal signal sets such a value of K that the number of bits of the code Δφ equal to zero, counting from the oldest to the first bit equal to a logical unit, not including it, will be equal to S . I.e. if R is greater than S, then R-K = S or K = R-S. This equality holds if R-S is not greater than the maximum K-M value.

If (RS) is greater than M, then the device cannot set a value K such that the number of bits of the code Δφ equal to zero, counting from the oldest to the first bit equal to a logical unit, not including it, will be S. In this case, the number of these bits will be greater than S, and the value of the code K will be M.

Thus, we obtain that the value of the code K is determined by the formula

From this it follows that the entire range of generated frequencies of the proposed sinusoidal signal generator can be arbitrarily divided into intervals depending on the value of K, i.e. depending on f _CLK. In this case, the values of the code K will be considered the interval numbers. In accordance with formula (6), each interval will be characterized by its own frequency tuning step Δf.

In the interval with number 0, the frequencies f _out fall, the generation of which occurs at f _CLK = f _G. The upper frequency of the interval is the maximum frequency of the generated signal f _max -f _G / 2, the code F of which is 2 ^{(N + M-1)} . The lower boundary of the interval is the frequency equal to f _G / 2 ^S whose code F is 2 ^{(N + M- (S + 1)} . In accordance with formula (6), this interval is characterized by Δf equal to f _G / 2 ^N.

Subsequent intervals from numbers from 1 to (M-1), with frequency boundaries from f _G / 2 ^{(K + S)} to f _G / 2 ^{(K + S-1)} , whose F codes are in the range from 2 ^{(N + M- (K + S + 1))} to (2 ^{(N + M- (K + S)} -1), are characterized by Δf definable by formula (6).

The last interval with the number M, with frequency boundaries f _G / 2 ^{(K + S)} to f _min = f _G / 2 ^{(N + M)} , whose F codes lie in the range from 1 to (2 ^{(N + M- (K + S)} -1), characterized by Δf defined by formula (7).

You can see that the larger the number S, the smaller the number of values of the code F lie in the intervals with numbers from 1 to M, and the greater the number of values of the code F lie in the interval with the number 0. That is, the larger the number S, the smaller the number of possible frequencies for generation we can set in the intervals with numbers from 1 to M, and vice versa for the interval with number 0. This follows from the fact that Δf does not depend on S for a particular interval, and with increasing S, the boundaries of the intervals shift toward lower frequencies. Consequently, the number of adjustment steps is reduced. The total number of possible frequencies of the output signal of the sinusoidal signal generator decreases. The smaller the value of the number S, the greater the number of possible frequencies of the output signal for generation that can be set.

On the other hand, the smaller the number S, the smaller the number of clock cycles f _CLK per one period of the output signal of the generator during the transition from one interval to another, which means that the quality of the generated signal at the boundary of the interval decreases. This follows from the fact that, in fact, S determines the number of bits of the code Δφ equal to zero, counting from the highest to the first bit equal to a logical unit, not including it, for intervals with numbers from 1 to (M-1). When moving from one interval to another, the first value of Δφ in the new interval will be equal to (2 ^NS -1). For this code, the number of clock cycles f _CLK per one period of the generator output signal will be approximately 2 ^S. As the frequency f _out decreases, Δφ will also decrease to (2 ^NS-1 ). For this code, the number of clock cycles f _CLK per one period of the generator output signal will be 2 ^{S + 1} . With a further decrease in the frequency, a transition to the next interval will occur and the patterns will be preserved, and so on until the interval with the number M, in which the number of clock cycles f _CLK per one period of the generator output signal will be from 2 ^S to 2 ^N.

It follows that S can take values from 1 to (N-1), and the more S, the better the quality of the generated signal. The smaller S, the more frequencies f _out there is the ability to set for generation.

Thus, by maintaining a sinusoidal signal UE and DD into the generator, the frequency range is expanded by 2 ^M times while maintaining the capacity of the adder and accumulator phase and volume of the ROM in comparison with the prototype.

Claims (1)

A sinusoidal signal generator comprising a N-bit adder connected in series, an N-bit phase accumulator, the output of which is connected to the second input of the adder, a read-only memory and a digital-to-analog converter, as well as a device for generating a frequency code of the generated signal with F bits (N + M) and a generator clock pulses, characterized in that a device for converting the frequency code of the generated signal F into the phase increment code Δφ and into the clock frequency code K is introduced into it according to the laws:

where S is a natural number, taking a value from 1 to (N-1),

where скоб brackets mean a rounding operation to the smaller side, the input of which is connected to the output of the frequency code generating device of the generated signal, and its first output is to the first adder input, a controlled clock frequency divider, the input of which is connected to the second output of the frequency code conversion device, its clock input is connected to the output of the clock generator; its output is connected to the clock input of the phase accumulator.