RU2452018C1 - Apparatus for evaluating scientific research and development works - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus has groups of input registers, groups of logarithmation units, groups of inverters, groups of delay elements, groups of multipliers, groups of accumulative adders, accumulative adders, groups of dividers, dividers, a switch, groups of output registers, output registers, groups of indicator units, a clock pulse generator, a switch and pulse distributors.

EFFECT: high accuracy of evaluating scientific research and development works owing to evaluation based on a priori probability values.

4 dwg, 2 tbl

Description

The invention relates to computer technology and can be used to evaluate the performance of research and development (R&D) in order to objectively evaluate the performance of the work as a whole and by its stages.

A device for assessing the implementation of research and development work, containing groups of input registers, input registers, groups of blocks of logarithms, groups of delay elements (EZ), groups of inverters, groups of multiplication blocks, groups of accumulative adders, accumulative adder, groups of division blocks , division block, switch, group of output registers, output register, group of display units, display unit, clock generator and pulse distributor (RF patent No. 2401750, class G06Q 10/00, 2009) .

Evaluation of R&D using this device can be carried out as follows.

The value of the entropy H _{i of} performing R&D with respect to the i-th parameter is determined:

where P _ij is the probability of the feasibility of the i-th parameter in the process of performing R&D according to the j-th expert (these values are assigned (set) by experts under conditions of a pre-established time for performing R&D and the costs of its implementation);

b _i - coefficient taking into account the qualification (competence) of the j-th expert;

k is the number of experts;

n is the number of parameters implemented in R&D.

выполнения НИОКР относительного i-го параметра по следующей формуле:Next, the average value of entropy is determined

R&D of the relative i-th parameter according to the following formula:

The entropy value H _{i∑ is determined, the} influence of the i-th parameter on R&D performance according to the following dependence:

where P _ij is the probability of the influence of the i-th parameter on R&D performance in the opinion of the j-th expert (these values are set by experts who take into account the pre-established time of R&D and the costs of its implementation).

влияния i-го параметра на выполнение НИОКР:Subsequently, the average value of entropy is estimated

the influence of the i-th parameter on R&D:

In conclusion, the value of Н _{∑ of the} entropy of R&D is determined by the formula

и Н_∑. Значения

характеризуют неопределенность выполнения НИОКР относительно i-го параметра и могут быть использованы Заказчиками и Исполнителями НИОКР.The output parameters will be the values

and H _∑ . Values

characterize the uncertainty of R&D performance relative to the i-th parameter and can be used by Customers and R&D Contractors.

The value of Н _∑ allows you to choose the "optimal" (rational) option for R&D in terms of the amount of funding, the timing and number of parameters implemented.

Carrying out similar calculations for all variants of R & D (R & performing predetermined conditions - settings, timing, and volume of funding) necessary to compare values of H _Σ and select the option that corresponds to the minimum value of this quantity of entropy.

и Н_∑.The decision maker (DM), taking into account the obtained calculation results, makes the final choice of the R&D option both in terms of the parameters of the future scientific and technical products (products) and the terms of its implementation. A specific numerical example of evaluation is given in the description of this device.

and H _∑ .

The disadvantage of this device is the low objectivity of the evaluation of R&D, since it is made only on the basis of expert information, which may be subjective.

Technically, the result of the claimed invention is to increase the objectivity of the assessment of R&D and expand the functionality due to the presence of this assessment based on objective information.

In this situation, the assessment of R&D can be carried out as follows. The value of the entropy H _{ip of} performing R&D of the relative i-th parameter in the presence of a priori probability values is determined by the following formula:

where P _ia is the a priori probability of the feasibility of the ith parameter in the process of R&D;

n is the number of parameters implemented in R&D.

Next, the entropy value H _{ib of the} influence of the ith parameter on R&D performance is determined by the following dependence:

- априорная вероятность влияния i-го параметра на выполнения НИОКР (здесь необходимо учитывать время выполнения НИОКР и затраты на ее проведение).Where

- the a priori probability of the influence of the i-th parameter on R&D (here it is necessary to take into account the time of R&D and the costs of its implementation).

In conclusion, the value of the entropy Н _{∑p of} performing R&D is determined by the formula:

The output values will be the values of H _ip and H _∑p . The values of H _ip characterize the uncertainty of R&D performance of the relative i-th parameter and can be used by Customers and R&D Contractors.

The value of H _∑p allows _you to choose a rational option for the implementation of R&D in terms of funding, timing and number of parameters implemented.

Carrying out the above calculations for all R&D options, it is necessary to compare the values of Н _∑p and choose the option that corresponds to the minimum value of this entropy value.

и

. В соответствии с формулами (6) и (7) будем иметь.To illustrate, consider a specific example for the case when n = 5. Table 1 shows the values of P _ia and H _ia , and table 2 contains the values

and

. In accordance with formulas (6) and (7) we will have.

Table 1 Values of P _ia and H _ia i one 2 3 four 5 P _ia 0.75 0.80 0.85 0.70 0.90 H _ia fifteen 0.178 0.139 0.250 0,095

Table 2

и

Values

and

i one 2 3 four 5

0.75 0.75 0.80 0.75 0.85

fifty 0.215 0.178 0.215 0.139

Using formula (8), we finally obtain:

H _∑p = (0.250 + 0.215 + 0.178 + 0.215 + 0.139) / 5 = 0.997 / 5 = 0.1994

In the future, performing similar calculations for other R&D options, it is necessary to compare the values of Н _∑p and choose the option that corresponds to the minimum value of this entropy.

, характеризующие вероятности влияния i-го параметра на выполнение НИОКР по мнению j-го эксперта, информационные входы третьей группы входных регистров являются входом задания исходной информации, на которые поступают значения b_j, характеризующие коэффициенты квалификации (компетентности) j-го эксперта, информационные входы первого и второго входных регистров являются входом задания исходной информации, на которые поступают соответственно значения n, характеризующие количество параметров, обрабатываемых в НИОКР, и величина k, характеризующая число экспертов, выходы первой и второй групп входных регистров соединены со входами соответственно первой и второй групп блоков логарифмирования, а также первой и второй групп ЭЗ, выходы первой и второй групп логарифмирования подключены к входам соответственно первой и второй групп инверторов, выходы которых соединены с первыми входами соответственно первой и третьей групп блоков умножения, вторые входы которых подключены к выходам соответственно первой и второй групп ЭЗ, выходы с первого по k-й элементов третьей группы входных регистров соединены с первыми входами соответственно с первого по n-й элементов каждого из k вертикальных рядов второй группы блоков умножения, вторые входы которой подключены к выходам соответствующих элементов первой группы блоков умножения, выходы с первого по k-й элементов каждого из n горизонтальных рядов второй и третьей групп блоков умножения соединены с первого по k-й входами соответственно с первого по n-й элементов первой и второй групп накопительных сумматоров, выходы которых подключены к входам делимого соответствующих элементов первой и второй групп блоков деления, входы делителя которых соединены соответственно с первым и вторым выходами коммутатора, информационный вход которого подключен к выходу второго входного регистра, выходы первой группы блоков деления подключены к информационным входам соответствующих элементов первой группы выходных регистров, выходы которых соединены с входами соответствующих элементов первой группы блоков индикации, выходы второй группы блоков деления подключены к соответствующим входам первого накопительного сумматора, выход которого соединен с входом делимого первого блока деления, вход делителя которого подключен к выходу первого входного регистра, а выход - к информационному входу первого выходного регистра, выход которого соединен с входом первого блока индикации, дополнительно содержит четвертую и пятую группы входных регистров, каждая из которых состоит из n элементов, третий входной регистр, третью и четвертую группы логарифмирования, каждая из которых состоит из n элементов, третью и четвертую группы инверторов, каждая из которых состоит из n элементов, третью и четвертую группы ЭЗ, каждая из которых состоит из n элементов, четвертую и пятую группы блоков умножения, каждая из которых состоит из n элементов, второй накопительный сумматор, второй блок деления, второй выходной регистр, второй блок индикации, второй накопительный сумматор, вторую группу выходных регистров, состоящую из n элементов, вторую группу блоков индикации, состоящую из n элементов, второй РИ и переключатель, вход которого соединен с выходом генератора тактовых импульсов, а первый и второй выходы подключены к тактовым входам соответственно первого и второго РИ, двенадцатый выход второго РИ соединен с входами записи четвертого и пятого регистров и третьего входного регистра, тринадцатый и четырнадцатый выходы со входами считывания соответственно четвертой и пятой групп входных регистров, пятнадцатый выход с входами записи второй группы выходных регистров, шестнадцатый выход - с входом считывания третьего входного регистра, семнадцатый выход - с входом считывания второго выходного регистра, восемнадцатый и девятнадцатый выходы - с входами считывания соответственно второй группы выходных регистров и второго выходного регистра, информационные входы четвертой группы входных регистров являются входами задания исходной информации, на которые поступают значения P_ia, характеризующие априорную вероятность реализуемости i-го параметра в процессе выполнения НИОКР, информационные входы пятой группы входных регистров являются входами задания исходной информации, на которые поступают значения P*_ia, характеризующие априорную вероятность влияния i-го параметра на выполнение НИОКР, информационный вход третьего входного регистра является входом задания исходной информации, на который поступает значение n, характеризующее количество параметров, отрабатываемых в НИОКР, выходы четвертой и пятой групп входных регистров соединены со входами соответственно третьей и четвертой групп блоков логарифмирования, а также третьей и четвертой групп инверторов, выходы которых подключены к входам соответственно третьей и четвертой групп ЭЗ, выходы которых соединены с первыми входами соответственно четвертой и пятой групп блоков умножения, вторые входы которых подключены к входам соответственно третьей и четвертой групп блоков логарифмирования, выходы каждого элемента четвертой группы блоков умножения соединены с информационными входами соответствующих элементов второй группы выходных регистров, выходы каждого из которых подключены к входам соответствующих элементов второй группы блоков индикации, выходы каждого элемента пятой группы блоков умножения соединены с соответствующими входами, с первого по n-й, второго накопительного сумматора, выход которого подключен к входу делимого второго блока деления, вход делителя которого соединен с выходом третьего входного регистра, а выход - с информационным входом второго выходного регистра, выход которого подключен к входу второго блока индикации.The technical result is achieved by the fact that the device for evaluating the implementation of research and development work, containing the first and second groups of input registers, each of which consists of k × n elements, the third group of input registers, consisting of k elements, the first and second input registers, the first and second groups of logarithm blocks, each of which consists of k × n elements, the first and second groups of delay elements (EZ), each of which consists of k × n elements, the first and second groups of inverters, each of which consists of k × n elements, the first, second and third groups of multiplication blocks, each of which consists of k × n elements, the first and second groups of accumulative adders, each of which consists of n elements, the first accumulative adder, the first and second groups of division blocks, each of which consists of n elements, a first division block, a switch, a first group of output registers consisting of n elements, a first output register, a first group of indication blocks consisting of n elements, a first indication block, a clock generator pulses and a first pulse distributor (RI), the first output of which is connected to the recording inputs of the first, second and third groups of input registers, the first and second input registers, the second and third outputs - from the read inputs of the first and second groups of input registers, the fourth output with read inputs of the third group of input registers, the fifth output - with the read input of the second input register, the sixth output - with the control input of the switch, the seventh output - with the read input of the first input register, eight and ninth outputs - to the inputs of respectively writing and reading the first group of output registers, tenth and eleventh outputs - to the inputs of respectively writing and reading of the first output register data inputs of the first group of input registers are input reference source information, which are supplied with the value P _ij, characterizing the probability of the feasibility of the i-th parameter in the process of performing research and development (R&D) according to the j-th expert, the information inputs of the second group s input registers are inputs of the job initial information, which receives the values

, characterizing the probabilities of the influence of the i-th parameter on R&D performance, according to the j-th expert, the information inputs of the third group of input registers are the input of the input of the initial information, to which b _j values characterizing the qualification (competence) coefficients of the j-th expert, information inputs the first and second input registers are the input input of the initial information, which receives respectively the values of n, characterizing the number of parameters processed in R&D, and the value of k, character The current number of experts, the outputs of the first and second groups of input registers are connected to the inputs of the first and second groups of logarithms, as well as the first and second groups of EZ, the outputs of the first and second groups of logarithms are connected to the inputs of the first and second groups of inverters, the outputs of which are connected to the first inputs of the first and third groups of multiplication blocks, respectively, the second inputs of which are connected to the outputs of the first and second groups, respectively, the outputs from the first to k-th elements of the third group of input registers are connected to the first inputs, respectively, from the first to the n-th elements of each of k vertical rows of the second group of multiplication blocks, the second inputs of which are connected to the outputs of the corresponding elements of the first group of multiplication blocks, the outputs from the first to k-th elements of each of the n horizontal rows of the second and the third group of multiplication blocks are connected from the first to the k-th inputs, respectively, from the first to the n-th elements of the first and second groups of accumulative adders, the outputs of which are connected to the inputs of the dividend of the corresponding elements of the first and second groups of division blocks, the divider inputs of which are connected respectively to the first and second outputs of the switch, the information input of which is connected to the output of the second input register, the outputs of the first group of division blocks are connected to the information inputs of the corresponding elements of the first group of output registers, the outputs of which are connected to the inputs of the corresponding elements of the first group of indication blocks, the outputs of the second group of division blocks are connected to the corresponding inputs of the first accumulative adder, the output of which is connected to the input of the dividend first division block, the input of the divider of which is connected to the output of the first input register, and the output to the information input of the first output register, the output of which is connected to the input of the first display unit, additionally contains the fourth and fifth groups of input registers, each of which consists of n elements, the third input register, the third and fourth groups of logarithms, each of which consists of n elements, the third and fourth groups of inverters, each of which consists of n elements entents, the third and fourth groups of EZ, each of which consists of n elements, the fourth and fifth groups of multiplication blocks, each of which consists of n elements, the second accumulative adder, the second division block, the second output register, the second display unit, the second accumulative adder , a second group of output registers, consisting of n elements, a second group of display units, consisting of n elements, a second RI and a switch, the input of which is connected to the output of the clock generator, and the first and second outputs are connected to clock cycles the first inputs of the first and second RIs, the twelfth output of the second RI is connected to the recording inputs of the fourth and fifth registers and the third input register, the thirteenth and fourteenth outputs with read inputs of the fourth and fifth groups of input registers, respectively, the fifteenth output with the write inputs of the second group of output registers, sixteenth output - with the read input of the third input register, seventeenth output - with the read input of the second output register, eighteenth and nineteenth outputs - with inputs read respectively, of the second group of output registers and the second output register, the information inputs of the fourth group of input registers are inputs of the initial information, which receive the values of P _ia characterizing the a priori probability of the feasibility of the ith parameter in the process of R&D, the information inputs of the fifth group of input registers are reference input of the initial information, which are supplied with the values of P * _ia, characterize the a priori probability of the impact of the i-th parameter for R & D, Inform the ion input of the third input register is the input input of the initial information, which receives the value n characterizing the number of parameters worked out in R&D, the outputs of the fourth and fifth groups of input registers are connected to the inputs of the third and fourth groups of logarithms, as well as the third and fourth groups of inverters the outputs of which are connected to the inputs of the third and fourth groups of EZs respectively, the outputs of which are connected to the first inputs of the fourth and fifth groups of blocks, respectively II, the second inputs of which are connected to the inputs of the third and fourth groups of logarithms, respectively, the outputs of each element of the fourth group of multiplication blocks are connected to the information inputs of the corresponding elements of the second group of output registers, the outputs of each of which are connected to the inputs of the corresponding elements of the second group of display blocks, the outputs of each element of the fifth group of multiplication blocks are connected to the corresponding inputs, from the first to the nth, second accumulative adder, the output of which is connected n to the input of the divisible second division block, the input of the divider of which is connected to the output of the third input register, and the output to the information input of the second output register, the output of which is connected to the input of the second display unit.

Figure 1, 2 and 3 presents a functional diagram of a device for evaluating the implementation of research and development (for the elimination of cumbersome communication between the RI and the control inputs of the respective blocks are shown incompletely, and are indicated by the numbering of inputs and outputs).

Figure 4 presents the sequence diagram of the operation of the claimed device (the ordinates indicate the numbers of the outputs of the RI, and the abscissa axis indicates the number of ticks), and the duration of various computational operations (addition is one clock, multiplication is eight clocks, division is sixteen clocks, logarithm is twenty clock cycles) in the upper part of figure 4 (for the possibility of execution of the cyclogram, k = 4, n = 5, although these values can take arbitrary values). Figure 4, a) shows the sequence diagram of the device in mode I, and figure 4, b) in mode II.

A device for evaluating the implementation of research and development (Figs. 1, 2 and 3) contains the first 1 and second 2 groups of input registers, each of which consists of k × n elements, the third group of 3 input registers, consisting of k elements, the first 4 and second 5 input registers, the first 6 and second 7 groups of logarithm blocks, each of which consists of k × n elements, the first 8 and second 9 EZ, each of which consists of k × n elements, the first 10 and second 11 groups of inverters, each of which consists of k × n elements, the first 12, sec 13th and third 14th groups of multiplication blocks, each of which consists of k × n elements, the first 15 and second 16 groups of accumulative adders, each of which consists of n elements, the first accumulative adder 17, the first 18 and second 19 groups of division blocks, each of which consists of n elements, the first division unit 20, the switch 21, the first group 22 of output registers, consisting of n elements, the first output register 23, the first group of 24 display units, the first display unit 25, the pulse generator 26, the first 27 and the second 28 RI, switch 29, h the fourth 30 and fifth 31 groups of input registers, the third input register 32, the first 33 and second 34 groups of logarithm blocks, the third 35 and fourth 36 groups of inverters, the third 37 and fourth 38 groups of EZ, the fourth 39 and fifth 40 groups of multiplication blocks, the second group output registers 41, a second group of indication blocks 42, a second accumulative adder 43, a second division block 44, a second output register 45, and a second indication block 46.

A variant of the accumulative adder is given in the graphic materials of the prototype.

A device for evaluating the implementation of research and development works in two modes as follows.

влияния i-го параметра на выполнение НИОКР по мнению j-го эксперта. На информационные входы каждого из элементов третьей группы 3 входных регистров направляются значения b_j коэффициента, учитывающего квалификацию (компетентность) j-го эксперта. На информационные входы первого 4 и второго 5 входных регистров засылается соответственно количество n параметров, реализуемых в НИОКР, и число k экспертов. При этом управляющий сигнал на входы записи групп 1, 2 и 3 и регистров 4 и 5 подается с первого выхода первого РИ 27, темп работы которого задается генератором 26 тактовых импульсов.Mode I. The switch 29 is set to position I and the signals from the clock generator 26 will be fed to the clock input of the first RI 27 (prototype blocks work). The information inputs of each of the elements of the first group 1 of the input registers are sent probabilities P _{ij of the} feasibility of the i-th parameter in the process of performing R&D according to the j-th expert. Probabilities are fed to the information inputs of the second of each element of the second group of 2 input registers

the influence of the i-th parameter on R&D performance, according to the j-th expert. The information inputs of each of the elements of the third group of 3 input registers are sent the values of b _j coefficient taking into account the qualification (competence) of the j-th expert. The information inputs of the first 4 and second 5 input registers are respectively sent the number n of parameters implemented in R&D, and the number k of experts. In this case, the control signal to the recording inputs of groups 1, 2 and 3 and registers 4 and 5 is supplied from the first output of the first RI 27, the pace of which is set by the clock generator 26.

засылаются на входы соответствующих элементов первой 6 и второй 7 групп логарифмирования соответственно и на входы соответствующих элементов первой 8 и второй 9 групп ЭЗ соответственно. С выходов групп 6 и 7 значения lnP_ij и

поступают на входы каждого из соответствующих элементов первой 10 и второй 11 групп инверторов соответственно.According to the signals from the second and third outputs of the first RI 27 to the read inputs of each of the elements of the first 1 and second 2 groups of input registers, respectively, the values of P _ij and

are sent to the inputs of the corresponding elements of the first 6 and second 7 groups of logarithms, respectively, and to the inputs of the corresponding elements of the first 8 and second 9 groups of EZ, respectively. From the outputs of groups 6 and 7, the values lnP _ij and

arrive at the inputs of each of the corresponding elements of the first 10 and second 11 groups of inverters, respectively.

Inverters are needed in order to eliminate the minus after the logarithm of probabilities that are less than one.

подаются на первые входы каждого из соответствующих элементов первой 12 и третьей 14 групп блоков умножения соответственно, на вторые входы которых направляются значения P_ij и

с выходов первой 8 и второй 9 ЭЗ соответственно. С выходов первой группы 12 блоков умножения величины -P_ij(lnP_ij) засылаются на вторые входы каждого из соответствующих элементов второй группы 13 блоков умножения, на первые входы которых по сигналу четвертого выхода первого РИ 27 на вход считывания каждого из элементов третьей группы 3 входных регистров подаются значения b_j. Причем величина b₁ засылается на все n элементов первого вертикального ряда, b₂ - на все n элементов второго вертикального ряда и т.д. Значения b_k направляются на первые входы всех n элементов k-го вертикального ряда.From the inputs of groups 10 and 11, the quantities - lnP _ij and -

fed to the first inputs of each of the corresponding elements of the first 12 and third 14 groups of multiplication blocks, respectively, to the second inputs of which the values P _ij and

from the outputs of the first 8 and second 9 EZ, respectively. From the outputs of the first group of 12 multiplication units, the quantities -P _ij (lnP _ij ) are sent to the second inputs of each of the corresponding elements of the second group 13 of the multiplication units, to the first inputs of which, by the signal of the fourth output of the first RI 27, to the read input of each of the elements of the third group of 3 input registers served values b _j . Moreover, the value of b _{1 is} sent to all n elements of the first vertical row, b ₂ - to all n elements of the second vertical row, etc. The values of b _{k are} sent to the first inputs of all n elements of the kth vertical row.

From the outputs of the second group of 13 multiplication blocks, the quantities -P _ij (lnP _ij ) b _{j are} sent to the input of the first group 15 of accumulative adders. Moreover, these values from the outputs from the first to the kth horizontal rows of group 15 are fed to the inputs from the first to kth, respectively, from the first to the n-th elements of the first group 15 of accumulative adders. Due to this, from the output of each element of group 16, the values of H _i determined by formula (1) are sent to the inputs of the dividend of the corresponding elements of the first group 18 of division blocks, the values of the number of experts k being supplied to the inputs of the divider of which from the first output of switch 21. The value of k is sent to the information input of the switch 21 according to the signal from the fourth output of the first RI 27 to the read input of the second input register 5. The signal to the control input of the switch 21 is sent from the sixth output of the first RI 27.

, определенные по формуле (2), подаются на информационные входы соответствующих элементов первой группы 22 выходных регистров, на входы записи которых управляющий сигнал подается с восьмого выхода первого РИ 27.From the outputs of each element of the group 18 values

determined by the formula (2) are fed to the information inputs of the corresponding elements of the first group of 22 output registers, the recording inputs of which the control signal is supplied from the eighth output of the first RI 27.

с выхода каждого элемента этой группы засылаются на входы соответствующих элементов первой группы 24 блоков индикации для наглядного отображения.According to the signal from the ninth output of the first RI 27 to the read inputs of the first group of 22 output registers

from the output of each element of this group are sent to the inputs of the corresponding elements of the first group of 24 display units for visual display.

From the outputs of the third group of 14 blocks of multiplication, the quantities P _ij (lnP _ij ) are sent to the inputs of the second group of 16 accumulative adders. Moreover, these values from the outputs from the first to the kth horizontal rows of group 16 are fed to the inputs from the first to kth, respectively, from the first to the n-th elements of the second group 16 of accumulative adders. Due to this, from the output of each element of group 16, the values of H _i∑ determined by formula (3) are sent to the inputs of the dividend of the corresponding elements of the second group 19 of division blocks, the values of k being supplied to the inputs of the divider of which from the second output of the switch 21. The value of k is sent to the information input of the switch 21 according to the signal from the fourth output of the RI 27 to the read input of the second output register 5. The signal to the control input of the switch 21 in this case is not supplied.

, определенные по формуле (4), подаются соответственно на входы с первого по n-й первого накопительного сумматора 17, с выхода которого величина

направляется на вход делимого блока 20 деления. По сигналу с седьмого выхода первого РИ 27 на вход считывания первого входного регистра 4 значение количества параметров n, реализуемых в НИОКР, засылается на вход делителя блока 20. С выхода этого блока величина Н_∑, вычисленная по формуле (5), подается на информационный вход первого выходного регистра 23, на вход записи которого управляющий сигнал направляется с десятого выхода первого РИ 27.From the outputs of each element of group 19 values

determined by the formula (4), respectively, are fed to the inputs from the first to the nth first accumulative adder 17, the output of which

sent to the input of the divisible division block 20. According to the signal from the seventh output of the first RI 27 to the read input of the first input register 4, the value of the number of parameters n implemented in R&D is sent to the input of the divider of block 20. From the output of this block, the value Н _∑ calculated by formula (5) is fed to the information input the first output register 23, the input of the recording of which the control signal is sent from the tenth output of the first RI 27.

According to the signal from the eleventh output of the first RI 27 to the read input of the output register 23, the value of Н _∑ from its output is sent to the input of the display unit 25 for visual display. The order of operation of the device in this mode is presented on the cyclogram of its operation (figa).

влияния i-го параметра на выполнение НИОКР. На информационный вход третьего входного регистра 32 засылается количество n параметров, реализуемых в НИОКР. При этом управляющий сигнал на входы записи групп 30 и 31 и регистра 32 подается с двенадцатого выхода второго РИ 28, темп работы которого задается генератором 26 тактовых импульсов.Mode II. The switch 29 is set to position II and the signals from the clock generator 26 will be fed to the clock input of the second RI 28 (the newly introduced blocks work). The information inputs of each of the elements of the fourth group of 30 input registers are sent probabilities P _{ia of the} feasibility of the ith parameter in the process of performing R&D. Probabilities are fed to the information inputs of each of the elements of the fifth group of 31 input registers

the influence of the i-th parameter on R&D. The information input of the third input register 32 is sent the number n of parameters implemented in R&D. In this case, the control signal to the recording inputs of groups 30 and 31 and register 32 is supplied from the twelfth output of the second RI 28, the pace of which is set by the clock generator 26.

засылаются на входы соответствующих элементов третьей 33 и четвертой 34 групп логарифмирования соответственно и на входы соответствующих элементов третьей 35 и четвертой 36 групп инверторов соответственно для ликвидации знаков «минус» после логарифмирования величин вероятностей, которые меньше единице.According to the signals from the thirteenth and fourteenth outputs of the second RI 28 to the read inputs of each of the elements of the fourth 30 and fifth 32 groups of input registers, respectively, the quantities P _ia and

are sent to the inputs of the corresponding elements of the third 33 and fourth 34 groups of logarithms, respectively, and to the inputs of the corresponding elements of the third 35 and fourth 36 groups of inverters, respectively, to eliminate the minus signs after the logarithm of the probability values that are less than one.

подаются на вторые входы каждого из соответствующих элементов четвертой 39 и пятой 40 групп блоков умножения соответственно, на первые входы которых направляются значения - P_ia и -

с выходов третьей 37 и четвертой 38 групп ЭЗ. Эти группы ЭЗ обеспечивают одновременность поступления сигналов на первые и вторые входы каждого элемента групп 39 и 40 блоков умножения. С выходов элементов четвертой группы 39 блоков умножения значения H_ip, определяемые по формуле (6), засылаются на информационные входы соответствующих элементов второй группы 41 выходных регистров. Управляющий сигнал на входы записи этих регистров подается с пятнадцатого выхода второго РИ 28.From the outputs of groups 33 and 34, the quantities ln (P _ia ) and

fed to the second inputs of each of the corresponding elements of the fourth 39 and fifth 40 groups of multiplication blocks, respectively, the first inputs of which are sent values - P _ia and -

with the outputs of the third 37 and fourth 38 groups of EZ. These EZ groups provide simultaneous signals to the first and second inputs of each element of groups 39 and 40 of the multiplication blocks. From the outputs of the elements of the fourth group of 39 blocks of multiplication, the values of H _ip determined by formula (6) are sent to the information inputs of the corresponding elements of the second group of 41 output registers. The control signal to the recording inputs of these registers is fed from the fifteenth output of the second RI 28.

подается на вход делимого второго блока 44 делителя, на вход делителя которого по сигналу на вход считывается третьего входного регистра 32 записывается величина n. Управляющий сигнал при этом направляется с шестнадцатого выхода второго РИ 28. С выхода блока 44 значение Н_∑р, определяемое по формуле (8), засылается на информационный вход второго выходного регистра 45. Управляющий сигнал на вход записи блока 45 подается с семнадцатого выхода второго РИ 28.From the outputs of the elements of the fifth group of 40 blocks of multiplication, the values of H _ib calculated by formula (7) are sent to the corresponding inputs of the second accumulative adder 43. From the output of block 43, the value

fed to the input of the divisible second block 44 of the divider, the input of the divider of which is read at the input of the third input register 32, the value n is written. The control signal is then sent from the sixteenth output of the second RI 28. From the output of block 44, the value of Н _{определяр} determined by formula (8) is sent to the information input of the second output register 45. The control signal is input to the recording input of block 45 from the seventeenth output of the second RI 28.

According to the signals from the eighteenth and nineteenth outputs of the second RI 28 to the read inputs of the second group of output registers 41 and the second output register 45, respectively, the values of H _ip and Н _{∑р are} sent respectively to the inputs of the second group 42 of display units and the second display unit 46 for visual display. The order of operation of the device in this mode is presented on the cyclogram of its operation (figb).

Thus, the technical result of the claimed invention is achieved not due to the mathematical apparatus, but using the technical means (blocks and elements) mentioned in the description of the operation of the device.

The described device allows the selection of the “optimal” (rational) R&D option in order to eliminate the failure to fulfill the technical specifications and significant material costs due to the production of low-quality (non-competitive) products. There is an expansion of functionality due to the availability of an R&D performance assessment based on a priori probability values, which significantly reduces the subjectivity of the assessment.

The industrial applicability of the invention is justified by the fact that it can be used in various fields (industries) of production when choosing a rational R&D option and evaluating its implementation.

Claims (1)

A device for evaluating the performance of research and development work, containing the first and second groups of input registers, each of which consists of k × n elements, the third group of input registers consisting of k elements, the first and second input registers, the first and second groups of logarithm blocks, each of which consists of k × n elements, the first and second groups of delay elements (EI), each of which consists of k × n elements, the first and second groups of inverters, each of which consists of k × n elements, the first the second and third groups of multiplication blocks, each of which consists of k × n elements, the first and second groups of accumulative adders, each of which consists of n elements, the first accumulative adder, the first and second groups of division blocks, each of which consists of n elements , the first division unit, the switch, the first group of output registers, consisting of n elements, the first output register, the first group of display units, consisting of n elements, the first display unit, the clock generator and the first pulse distributor s (RI), the first output of which is connected to the recording inputs of the first, second and third groups of input registers, the first and second input registers, the second and third outputs - with the read inputs, respectively, of the first and second groups of the input registers, the fourth output - with the read inputs of the third groups of input registers, the fifth output with the read input of the second input register, the sixth output with the control input of the switch, the seventh output with the read input of the first input register, the eighth and ninth outputs with inputs respectively but the writing and reading of the first group of output registers, tenth and eleventh outputs - to the inputs of respectively writing and reading of the first output register data inputs of the first group of input registers are input reference source information, which are supplied with the value P _ij, characterizing the probability realizability i-th parameter in the process of research and development (R&D), according to the j-th expert, the information inputs of the second group of input registers are inputs of the task niya of the initial information on which values

characterizing the probabilities of the influence of the i-th parameter on R&D according to the j-th expert, the information inputs of the third group of input registers are the input of the input of the initial information, to which b _i values characterizing the qualification (competence) coefficients of the j-th expert, the information inputs of the first and the second input registers are the input input of the initial information, which receives respectively the values of n, characterizing the number of parameters processed in R&D, and the value of k, character As the number of experts, the outputs of the first and second groups of input registers are connected to the inputs of the first and second groups of logarithms, as well as the first and second groups of EZ, the outputs of the first and second groups of logarithms are connected to the inputs of the first and second groups of inverters, the outputs of which are connected to the first inputs of the first and third groups of multiplication blocks, respectively, the second inputs of which are connected to the outputs of the first and second groups, respectively, the outputs from the first to the k-th elements of the third group of input p registers are connected to the first inputs, respectively, from the first to the nth elements of each of k vertical rows of the second group of multiplication blocks, the second inputs of which are connected to the outputs of the corresponding elements of the first group of multiplication blocks, the outputs from the first to kth elements of each of the n horizontal rows of the second and the third group of multiplication blocks are connected from the first to the k-th inputs, respectively, from the first to the n-th elements of the first and second groups of accumulative adders, the outputs of which are connected to the inputs of the divisible corresponding element in the first and second groups of division blocks, the divider inputs of which are connected respectively to the first and second outputs of the switch, the information input of which is connected to the output of the second input register, the outputs of the first group of division blocks are connected to the information inputs of the corresponding elements of the first group of output registers, the outputs of which are connected to the inputs of the corresponding elements of the first group of indication blocks, the outputs of the second group of division blocks are connected to the corresponding inputs of the first accumulative adder, the stroke of which is connected to the input of the dividend first division block, the input of the divider of which is connected to the output of the first input register, and the output to the information input of the first output register, the output of which is connected to the input of the first display unit, characterized in that it additionally contains the fourth and fifth groups input registers, each of which consists of n elements, the third input register, the third and fourth groups of logarithms, each of which consists of n elements, the third and fourth groups of inverters, each of which consists of n elements, the third and fourth groups of EZ, each of which consists of n elements, the fourth and fifth groups of multiplication blocks, each of which consists of n elements, the second accumulative adder, the second division block, the second output register, the second display unit , a second accumulative adder, a second group of output registers, consisting of n elements, a second group of indication blocks, consisting of n elements, a second RI and a switch, the input of which is connected to the output of the clock generator, and the first and second the moves are connected to the clock inputs of the first and second RIs respectively, the twelfth output of the second RI is connected to the recording inputs of the fourth and fifth registers and the third input register, the thirteenth and fourteenth outputs are with the read inputs of the fourth and fifth groups of input registers, respectively, the fifteenth output is with the record inputs the second group of output registers, the sixteenth output - with the read input of the third input register, the seventeenth output - with the read input of the second output register, eighteenth and nineteenth outputs - with reading inputs of the second group of output registers and the second output register, respectively, the information inputs of the fourth group of input registers are inputs of the input information, which receive the values of P _ia characterizing the a priori probability of the feasibility of the i-parameter in the process of performing R&D, information inputs of the fifth groups of input registers are inputs of a job of initial information, to which values

characterizing the a priori probability of the influence of the i-th parameter on R&D, the information input of the third input register is the input of the initial information, which receives the value n characterizing the number of parameters processed in R&D, the outputs of the fourth and fifth groups of input registers are connected to the inputs of the third and the fourth group of blocks of logarithms, as well as the third and fourth groups of inverters, the outputs of which are connected to the inputs of the third and fourth groups of EZ, respectively, output which are connected to the first inputs of the fourth and fifth groups of multiplication blocks, respectively, the second inputs of which are connected to the outputs of the third and fourth groups of logarithms, respectively, the outputs of each element of the fourth group of multiplication blocks are connected to the information inputs of the corresponding elements of the second group of output registers, the outputs of each of which connected to the inputs of the corresponding elements of the second group of indication blocks, the outputs of each element of the fifth group of multiplication blocks are connected to the corresponding by the input inputs from the first to the nth, second accumulative adder, the output of which is connected to the input of the divisible second division block, the input of the divider of which is connected to the output of the third input register, and the output to the information input of the second output register, the output of which is connected to the input of the second block indication.

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