RU2441320C1 - System of communication by ultrabroadband signals with increased accuracy and stability of synchronisation - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: in the proposed system of communication by ultrabroadband signals based on transfer and reception of low-duration pulses with high porosity, generation of transfer and reception intervals in the first and second radio stations is used so that they match each other without account of time required for passage of a radio signal between radio stations, after preliminary synchronisation a reference input of a frequency synthesiser on the basis of a system of pulse and phase frequency self-tuning, from which the reception intervals are generated in the first radio station, switches from the local reference signal to a reference signal from the second radio station, same as the reference input of the frequency synthesiser of the second radio station switches to the reference signal from the first radio station, as a result two cophased systems are generated, which makes it possible to synchronise signals between radio stations with accuracy to phase.

EFFECT: production of highly accurate and stable synchronisation during communication of interacting radio stations with application of a system of pulse-phase self-tuning of frequency.

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Description

The present invention relates to radio engineering, in particular to high-speed radio communication systems using pulsed ultra-wideband (UWB) signals, in which the working band and average signal frequency are comparable. Due to the absence of a carrier frequency, pulsed signals with a very short duration (of the order of 1 nsec or less) and a large duty cycle can increase the speed of information transfer, maintain high quality of the transmitted information and secrecy of transmission.

Known communication system according to patent US 6925109 "Method and system for fast acquisition of ultra-wideband signals". James L. Richards, Mark D. Roberts. 08/02/2005. The essence of the synchronization entry method in this UWB communication system is to use any part of the multipath propagation of a pulsed radio signal code sequence. Due to the increased pulsed flux of the multipath radio signal, it becomes possible to correlate with the standard pulsed flux, and when they coincide, the system enters into synchronism. With threshold processing of at least one reflected part of the multipath after checking for synchronism, the system performs a quick capture. Thus, a method for detecting a pulsed radio signal is to receive a pulsed signal, measure a reference (copy) of a pulsed stream, search for a pulsed signal by shifting a copy of the pulsed stream until they coincide.

The disadvantage of the known system can be attributed to inoperability in mobile execution, since the multipath condition unexpectedly varies depending on the range and relative position of the receiver and transmitter.

A known method and communication system with fast entry into synchronism with ultra-wideband signals (Patent RU No. 2354048. Method and communication system with fast entry into synchronism with ultra-wideband signals. G. Kyshtymov, V. Bondarenko and others. 11.28.2007)

The essence of the method of entering synchronism is the use of two independent radio channels - a UWB radio channel and a broadband (SHP) radio channel with FM or CT radio signals, which simultaneously transmit, for example, a synchronization code sequence.

The moments of change in the phase or frequency of the RF signal correspond to time windows with UWB pulses of the radio signal in the center of each time window. Entering synchronism and maintaining it at certain time intervals during which the UWB radio signal should not go beyond the time window for all destabilizing factors is provided by the NW radio channel. In the intervals between the synch signals of the NW radio channel can transmit other information. The moments of the change in the phase or frequency of the NW radio signal are extracted in the processes of its amplification, conversion to an intermediate frequency and digital form using an ADC and subsequent processing by a wavelet filter.

The disadvantages of this communication system include its operability only in the absence of multipath in the silo radio channel.

Closest to the proposed technical solution is the communication system described in [I.J. Immmorev, A. A. Sudakov, "Ultra-Wideband Interference Resistant System for Secure Radio Communication with High Data Rate", ICCSC′02, St. Petersburg, Russian Federation, June 2002] ("Ultra-wideband noise-immunity covert communications system with high data rate", pp. 230-232), adopted as a prototype.

The block diagram of the UWB radio prototype included in the communication system is shown in figure 1, where the following notation is introduced:

I - the general part of the device:

3 - receive / transmit switch;

4 - broadband filter (FFS);

5 - antenna;

II - transmitting part (PRD):

1 - transmitter buffer device (BUP);

2 - generator of ultra-wideband (UWB) pulses;

III - receiving part (PFP):

6 - low noise amplifier (MU);

7 - attenuator;

8 - power divider into two channels;

9 is a block of the time window of the signal channel;

10 - threshold device channel signal;

11 —buffer device of a signal channel (BUS);

12 - shaper threshold voltage of the signal channel;

13 - block time window of the noise channel;

14 - threshold device of the noise channel;

15 - buffer device noise channel (BUSH);

16 - shaper threshold voltage of the noise channel;

17 - processing and control unit;

18 is a synchronization unit.

The prototype device contains, in the general part I of the transceiver, a receive / transmit switch 3, a broadband filter (FWL) 4 and an antenna 5 connected in series. In the transmitting part II there is a buffer unit BUP 1 and an ultra-wideband (UWB) pulse generator 2 connected in series, the output of which is connected with the first input of the switch 3 receive / transmit. Receiving part III (PFP) contains a low-noise amplifier MU 6, an attenuator 7, a power divider into two channels 8, a block of a time window of a signal channel 9, a threshold device of a signal channel 10, a buffer device of the signal channel of the bus 11, the output of which is connected to the first input the processing and control unit 17, the first output of which is connected via a bus to the inputs of the threshold voltage conditioners of the signal channels 12 and noise 16, to the input of the synchronization unit 18 and the second input of the attenuator 7, the second input of the receive / transmit switch 3, the second output of which is connected to the input of MU 6. In addition, the second output of the power divider into two channels 8 is connected through a series-connected block of the time window of the noise channel 13, the threshold device of the noise channel 14 and BUSH 15 is connected to the second input of the processing and control unit 17, the second output which is connected to the input of the control unit 1. The first output of the synchronization unit 18 is connected to the second input of the time channel block of the signal channel 9, and the second output of the synchronization block 18 is connected to the second input of the time channel block of the noise channel 13. The outputs of the drivers the horn voltage of the signal channel 12 and the noise channel 16 are connected respectively to the second inputs of the threshold devices of the signal channel 10 and the noise channel 14. The input-output of the processing and control unit 17 is the input / output of information.

The prototype device operates as follows.

The information supplied to the "input / output" of the processing and control unit 17 is encoded into a sequence of pulses that, through the PCU 1, start the UWB pulse generator 2. UWB pulses are received through the switch 3 reception / transmission and SCF 4 in the antenna 5, which emits a signal on the air. Two channels of the receiving part of the subscriber UWB transceiver carry out parallel reception. One channel is used to receive the signal, the second - to assess the level of external noise and signals reflections from obstacles located on the path of the UWB signal. The basis of each channel is a sensitive threshold device of the signal channel 10 and a sensitive threshold device of the noise channel 14, made on the basis of key tunnel diodes designed to operate in the microwave range. Reception in the signal and noise channels is carried out in the corresponding time windows (time intervals). The signal received by the subscriber station antenna 5 through the switch 3 is amplified by a low-noise amplifier 6 and fed through the attenuator 7 to the power divider into two channels 8: a signal channel and a noise channel. The first channel sends a signal to the first input of the threshold device of the signal channel 10 through the time channel block of the signal channel 9, where it compares with the threshold voltage of the threshold voltage channel former of the signal channel 12. Noise from the second output of the power divider to two channels 8 through the time channel block of the noise channel 13 are fed to the first input of the threshold device of the noise channel 14, where there is a comparison with the threshold voltage of the driver of the threshold voltage of the noise channel 16. From the output of the threshold devices of the signal channel 10 and noise channel 14, the comparison results through the corresponding buffer devices BUS 11 and BUS 15 are sent to the digital signal processor of the processing and control unit 17. The signal processor analyzes deviations from threshold voltages, the received signal, and the received noise. Depending on the results of the processing, the sensitivity of the receiving part III is adjusted by adjusting the thresholds by the formers of the threshold voltage of the signal channel 12 and the noise channel 16. The dynamic range of the receiving part is adjusted using the attenuator 7. Also, according to the results of the analysis, the operation of the synchronization unit is controlled 18. Before you begin Calibration of the receiving part by external noise. The main calibration tasks are setting the threshold voltages supplied to the threshold devices of signal channel 10 and noise channel 14. During calibration, the threshold level in the signal channel is set higher than the threshold voltage in the noise channel by an amount necessary to achieve the required bit error probability. Calibration is carried out after turning on the power of the receiving part and after losing the signal in the operating mode. After calibration of the receiving part is completed, the system enters the signal search mode. Signal search is a mode that ensures the synchronization of the receiving and transmitting parts of the communication system. The transmitting part of the message source emits an overhead signal, which serves to establish communication between it and the receiving part. In this mode, in the receiver, the synchronization unit 18, through the time channel block of the signal channel 9, searches for the transmitted signal by temporarily shifting the synchronizing pulses until it coincides with the received signal. The received signal is set in the center of the window. The signal search procedure is carried out by the synchronization system and, like calibration, it is performed after turning on the power of the receiving part and after losing the signal in the operating mode. In the operating mode, the noise level in the noise windows is constantly assessed. When the measured noise level changes, the threshold values in the noise and, accordingly, in the signal channels change, and the signal level is adjusted by the attenuator 7. In addition, in the operating mode, the position of the UWB signal received is constantly monitored in the signal window. When the position of the UWB signal deviates from the center of the window by a specified minimum time interval, the synchronization system generates a command to shift the signal window by the required time interval. In the event of a signal loss (no pulses in the signal window), the communication system leaves the operating mode and switches to the calibration and signal search mode.

The time that the communication system enters the synchronism τ _sync is determined by sorting the time shift of the synchronizing pulses with a step equal to (0.5 ÷ 1) the duration of the UWB signal τ _and in the entire interval of the synchronization pulses T. Since the duration of the UWB pulse is τ _and much less than T (100 or more times), then the real time of entering synchronism even with a signal / noise ratio of 10 dB can reach from 0.05 to 0.5 seconds.

The disadvantage of the prototype device is the long time it takes for the system to enter synchronism, which is associated with a long search of the time shift of synchronizing pulses with a small step.

Another disadvantage of this device is as follows. This device uses uniformly-interval binary coding, when the reception and transmission of short pulses is carried out in previously known evenly spaced time intervals (time windows), the duration of which is much longer than the duration of a single UWB pulse that can be in this window. In other words, one UWB clock (or information signal “1” or “0”) can be in a relatively long window to simplify the mutual synchronization of transmitting and receiving radio stations.

At the same time, it is known that receiving a signal in a window whose duration is not much longer than the duration of the information signal improves the noise immunity of the device from impulse noise, since most of the impulse noise enters the noise windows.

Also increases the noise immunity from receiving the reflected signals.

However, in general, such a radio communication system is operable only when using narrowly directed antennas and with the stationary position of the transmitting and receiving radios.

Therefore, when using antennas with a circular orientation, it is necessary to transmit information signals “1” or “0” in the form of an uneven-interval code consisting of previously known n = 3, 4, 5, 6, etc. uneven intervals between UWB pulses. In this case, when using different intervals, the noise immunity of information transmission is significantly increased by correcting one, two or more errors in the received code due to the use of majority schemes for receiving information, but with a corresponding decrease in the transmission speed by a factor of n due to the redundancy of information pulses.

A significant reduction in the number of information pulses is achieved with positional coding of a binary code. The essence of this coding is that with one information signal located at one specific position, any number N of the bit code can be transmitted. For example, to transfer one byte of information, you must have 256 positions. The combined use of positional coding with unevenly interval coding of each information signal allows you to save both the transmission speed and noise immunity.

But for the implementation of positional coding, very high accuracy and stability of synchronization between two radio stations is necessary under all adverse conditions, and in mobile versions, taking into account the Doppler effect. The principal drawback of such schemes is the requirement of high identity of the master oscillators on different sides of the communication channel. Even expensive and bulky precision crystal oscillators do not solve the problem of the identity of the master oscillators on both sides of the communication channel, especially when working with high-speed mobile objects.

To eliminate these shortcomings in the communication system with ultra-wideband signals with increased accuracy and stability of synchronization, consisting of at least two radio stations, each of which has a common, transmitting and receiving parts, the common part containing a series of connected transmit / receive switch, a broadband filter and an antenna; the transmitting part comprises a series-connected buffer device of the transmitter and an ultra-wideband pulse generator; the receiving part contains a low-noise amplifier, an attenuator, a power divider in two channels (signal channel and noise channel) connected in series; the signal channel threshold device and the signal channel buffer device, the output of which is connected to the first input of the processing and control unit, are connected in series; the noise channel threshold device and the noise channel buffer device, the output of which is connected to the second input of the processing and control unit, are connected in series; in addition, the first output of the processing and control unit is connected by a bus to the inputs of the threshold voltage conditioners of the signal and noise channels, with the second inputs of the attenuator and the receive / transmit switch, the second output of which is connected to the input of the low-noise amplifier, and the second output of the processing and control unit is connected to the input of the transmitter buffer device, the output of the ultra-wideband pulse generator is connected to the first input of the receive / transmit switch, the outputs of the threshold channel voltage generators and to the noise channels are connected respectively to the second inputs of the threshold devices of the signal channel and the noise channel, the input-output of the processing and control unit is an input-output of information, series-connected reference generator, reference frequency divider, the first key, the output of which is connected to the output of the second key and signal the input of the frequency divider with a fixed division ratio; a response synchronizer, the first output of which is connected to the signal input of the second key, the second output is connected to the signal input of the third key, the output of which is connected to the reset input of the reference frequency divider; and the input-output bus of the response synchronizer is connected to the bus from the first output of the control and processing unit, to which the control inputs of the first, second, and third keys are connected to the same bus; digital frequency synthesizer (DSC), consisting of a series-connected frequency divider with a fixed division ratio, a frequency-phase detector, a low-pass filter, a voltage-controlled generator, and a frequency divider with a variable division ratio, the output of which is connected to the second input of the frequency-phase detector wherein the second output of the voltage-controlled generator is connected to the third input of the processing and control unit, and the second output of the frequency-phase detector is connected to its fourth input (in stroke matching indicator) as well as a microcontroller, with which the first output bus is connected to the control inputs of the frequency divider with a fixed division factor, the phase-frequency detector and frequency divider with a variable division ratio which form part of the digitally TSSCH; from the second output, the microcontroller is connected via the input-output bus to the bus from the first output of the processing and control unit, the fifth input of which is connected to the output of the reference generator; wherein the first output of the power divider into two channels is connected to the input of the threshold device of the signal channel, and the second output is connected to the input of the threshold device of the noise channel.

The proposed communication system is based on the task of creating high-precision and stable synchronization in the operation of two connected UWB radios. To do this, the transmitter of the first radio station emits clock pulses and information signals in each PRD interval, and the receiver of the second radio station receives these signals and adjusts and synchronizes its PRM intervals with the intervals of the PRM at the intervals of the first PRD based on the pulse phase-phase-locked loop (IFAP) accurate to phase. This is possible because the transmitter of the first radio station and the receiver of the second radio station now begin to operate from one reference generator in the first radio station. In the same way, the transmitter and the second radio station emits clock pulses and information signals in each PRD interval, and the receiver of the first radio station receives these signals and, using the DSC of the first radio station, synchronizes its PRM intervals with the intervals from the PRD of the second radio station up to phase. In other words, two IFAPCH synchronous systems are obtained, each operating from its own reference generator (OG). This synchronization is maintained under all destabilizing factors and in high-speed mobile devices.

Figure 2 presents a block diagram of the proposed UWB radio station included in the communication system, where it is indicated:

I is the general part; II - transmitting part (PRD); III - receiving part (PFP);

1 - transmitter buffer device (BUP);

2 - generator of ultra-wideband (UWB) pulses;

3 - receive / transmit switch;

4 - broadband filter (FFS);

5 - antenna;

6 - low noise amplifier (MU);

7 - attenuator;

8 - power divider into two channels;

10 - threshold device channel signal;

11 —buffer device of a signal channel (BUS);

12 - shaper threshold voltage of the signal channel;

14 - threshold device of the noise channel;

15 - buffer device noise channel (BUSH);

16 - shaper threshold voltage of the noise channel;

17 - processing and control unit;

19 - reference generator (OG);

20 - reference frequency divider (DOCH);

21 is the first key;

22 - the second key;

23 - the third key;

24 - driver response response pulses (FOS);

25 - frequency divider with a fixed division ratio (DPCD);

26 - frequency-phase detector (ChFD);

27 - low-pass filter (low-pass filter);

28 - voltage-controlled generator (VCO);

29 - frequency divider with a variable division ratio (DPKD);

30 - microcontroller (MK);

31 - digital part of the frequency synthesizer based on the IFAPCH system;

32 - control bus from MK 30.

The proposed device contains a common I, transmitting II and receiving III parts, as well as input units for mutual synchronization.

The common part I of the transceiver contains a series-connected switch reception / transmission 3 and a broadband filter FAS 4, the input of which is connected to the antenna 5.

The transmitting part II contains a series-connected buffer device of the transmitter BUP 1 and a UWB pulse generator 2, the output of which is connected to the first input of the receive / transmit switch 3.

The receiving part III contains a series-connected low-noise amplifier MU 6, an attenuator 7, a power divider into two channels 8, a threshold device for the signal channel 10, a buffer device for the signal channel BUS 11, the output of which is connected to the first input of the processing and control unit 17; serially connected threshold device of the noise channel 14 and a buffer device of the noise channel BUSH 15, the output of which is connected to the second input of the processing and control unit 17. In this case, the second output of the power divider into two channels 8 is connected to the first input of the threshold device of the noise channel 14, the second input of which connected to the threshold voltage generator of the noise channel 16. In addition, the first output of the processing and control unit 17 is connected by a bus to the inputs of the threshold voltage formers of the signal channel 12, the noise channel 16, with second inputs the attenuator 7 and the receive / transmit switch 3, the second output of which is connected to the input of the MU 6, and the output of the threshold voltage generator of the signal channel 12 is connected to the second input of the threshold device of the signal channel 10. The second output of the processing and control unit 17 is connected to the input of the control unit 1. The input-output of the processing and control unit 17 is an information input-output.

In addition, the proposed device contains a series-connected reference generator OG 19, DOCH 20 and a first key 21, the output of which is connected to the output of the second key 22 and the signal input DFKD 25; FOS 24, the first output of which is connected to the signal input of the second key 22, and the second output is connected to the signal input of the third key 23, the output of which is connected to the second input of DOCH 20. In this case, the input-output of the FOS 24 is connected to the bus from the first output of the control unit and processing 17, to which also the control inputs of the first 21, second 22 and third 23 keys are connected to the bus. The proposed device also contains a DSC, consisting of series-connected DPCD 25, ChFD 26, low-pass filter 27, VCO 28 and DPKD 29, the output of which is connected to the second input of the ChFD 26, while the second output of the VCO 28 is connected to the third input of the processing and control unit 17, and the second output of the BPF 26 (the output of the internal synchronism indicator of the DSC) is connected to the fourth input of the processing and control unit 17, the fifth input of which is connected to the output of the exhaust gas 19; and also the MK 30 microcontroller, from the first output of which is connected via the control bus 32 to the control inputs of the DFKD 25, ChFD 26 and DPKD 29. The second MK 30 output is connected via the input-output bus to the bus from the first output of the processing and control unit 17.

In the digital frequency synthesizer of the DSC based on the phase-locked loop phase-locked loop IFAPCH, the dashed blocks 25, 26 and 29 are executed in a single chip and represent the digital part of the DSC 31.

The control bus 32 from the first output of the MK 30 is a standard three-wire interface, where the pulse signals are transmitted in the serial code via three wires: 1) clock pulses (TI); 2) information signal (INF); 3) the pulse of recording permission (FROM) of the transmitted information in one of the blocks: DPKD 29, ChFD 26, DFKD 25. Moreover, for all blocks the common wires are TI and INF, and the pulse of recording permission FROM the transmitted information is fed through a separate wire to each controlled block .

The proposed communication system operates as follows.

When the power is turned on, all UWB radio stations of the communication system, after resetting and resetting counters, registers, and other digital devices, go through the UWB receiver calibration cycle, then go into receive mode (Rx) and wait for a call signal.

Entering synchronism, receiving and transmitting information between radio stations is carried out in the corresponding time intervals (time windows), which are alternated as follows: PFP, PDR, PFP, etc. (see timing diagrams in figure 3, explaining the process of entering into synchronism of two UWB radio stations and their subsequent operation).

Time intervals and corresponding positions within them are formed in the processing and control unit 17 using the elements of digital technology: shift registers, counters, D-flip-flops, etc. from highly stable frequencies from the DSC output (VCO 28 output) and from the exhaust gas 19. Highly stable clock frequency for the operation of digital receiver devices from the DSC output (more precisely, from the second output of the VCO 28) goes to the third input of the processing and control unit 17. Highly stable clock frequency for the operation of the digital devices of the transmitter is formed from the exhaust gas 19, from the output of which a high frequency is supplied to the fifth input of the block 17. Also, the log signals are generated in the processing and control unit 17. "0" and the log. "1" to switch the keys 21, 22, 23.

At the reference input CSCh (input DFKD 25) comes from the output of the reference generator OG 19 through the reference frequency divider DOCH 20 with the division ratio R and the closed first key 21 reference setting frequency F _O. In this case, the second key 22 is open, and the first key 21 and the second key 22 are controlled via the bus from the first output of the processing and control unit 17. Inside the digital part 31 of the digital clock circuit from the output of DPCD 25, the flow of short pulses with the comparison frequency F _cp = F _О / R arrives at the first input of the BPF 26, and at its second input a stream of short pulses from the output of the DPKD 29 with a frequency equal to the frequency F _cp in synchronism mode is received. The comparison of the two streams of pulses at the inputs of PFD 26 in frequency and phase at the first output PFD 26 generates a control voltage U _exercise, which, through the LPF 27 is supplied to the control input of the VCO 28 and adjusts its frequency F _VCO of the principle of operation IFAPCH ring under the support F _O . There is a capture of the frequency V of the _VCO from the reference frequency in the IFAPH ring, in which the synchronism is established up to the phase of the reference signal F _O according to the formula

R _gun = N · F _O / R = N · F _cf

where N is the division coefficient of the DPKD 29,

R is the division coefficient DFKD 25,

F _O - reference frequency at the input DFKD 25.

Synchronism with an accuracy of up to a phase in the IFAP ring of a digital frequency synthesizer is provided mainly due to the use of a digital frequency-phase detector (PFD) with three states and a loop low-pass filter using an integrator on an operational amplifier. Such a digital PFD is available in almost all modern DSC chips based on the IFAP ring (for example, LMX2364, LMX2470 chips from National Semiconductor, ADF4252, ADF4001 from Analog Devices and others).

As a result of the establishment of synchronism in the frequency synthesizer, a synchronism signal of the DSC with a log level is formed. “1” at the second output of the BPF 26 (synchronism indicator output).

Synchronism indicators are usually part of the ChFD of the DSC chips (for example, in the ADF4001 frequency synthesizer chip from Analog Devices) and are of two types: digital and analog. If there is no synchronism in the IFAPCH ring on which the DSC is built, then a log signal is generated at the output of the synchronism indicator. "0". From the second output of the BFD 26, a synchronism signal with a log level “1” enters the fourth input of the processing and control unit 17 and allows its operation.

In the mode of transmission of short pulses, the information supplied to the “input-output” of block 17 is encoded into a sequence of pulses that, from the second output of block 17, start the UWB pulse generator 2 through the BUP 1. These short UWB pulses are transmitted through the receive / transmit switch 3 and the FAP 4 to the antenna 5, which emits a signal on the air.

In reception mode, the signal received by antenna 5 passes through the BFF 4 and switch 3 to the input of MU 6, where it is amplified and supplied through the attenuator 7 and the power divider 8 into two channels — the signal channel and the noise channel. One channel is used to receive a signal, the second channel is used to estimate the level of external noise and signals of reflections from obstacles located on the path of UWB signal propagation. Reception in the signal and noise channels is carried out in the corresponding time windows (time intervals). The basis of each channel is a sensitive threshold device of the signal channel 10 and a sensitive threshold device of the noise channel 14. The second inputs of the threshold devices of the signal channel 10 and the noise channel 14 receive voltages respectively from the threshold voltage generator of the signal channel 12 and the threshold voltage generator of the noise channel 16. As a result, comparing the received signals and noise with the corresponding threshold voltages at the outputs of the threshold devices 10 and 14, signals are generated that through the corresponding buffer The primary devices BUS 11 and BUS 15 enter the processing and control unit 17, where deviations from threshold voltages, the received signal, and the received noise are analyzed. Depending on the processing results, the receiving part III is adjusted by adjusting the thresholds by the threshold voltage generators of the signal channel 12 and the noise channel 16. The dynamic range of the receiving part is adjusted using the attenuator 7 according to the signal received via the bus from the first output of the processing and control unit 17.

Thus, before starting work, the receiver is calibrated for external noise in the same way as in the prototype.

After passing the calibration cycle, both radio stations go into PFP mode and wait for a call signal.

Let the first radio station at time t ₁ (see time diagrams in Fig. 3) start operation, switch to the Tx mode, generate and emit at the end of the Tx interval (t ₂ ) for the second radio station a call signal consisting, for example, of 6 short pulses.

In the second radio station, after receiving the call signal in the processing and control unit 17, a single call pulse is allocated using a majority circuit to obtain greater reliability.

The majority scheme can be built on the appropriate microcircuits. For example, the KR1533LPZ microcircuit is a built-up majority element and is used to increase the reliability and noise immunity of the equipment. The logical state of the output of the microcircuit is determined by the coincident state of any two of the three inputs (see I.I. Petrovsky et al. “Logic ICs KR1533, KR1554” Reference. In two parts. Part 2, page 283. Moscow, Binom, 1993 )

A logic circuit with a set of such majority elements allows you to make a device, for example, for five or six inputs of seven, etc.

Under adverse conditions (long-distance communication, insufficient transmitter power, interference), not all 6 pulses of the call signal can be detected. Then the majority scheme should be turned on, with which a synchronization pulse can be allocated if 4 or 5 pulses arrive. The best option when 5 pulses arrive. If 4 pulses are received, then the transmitter power is insufficient and then it is necessary to transmit a command to increase the power. If all 6 pulses are received, then the power of the transmitting radio station is excessive and then it is necessary to transmit a command to reduce power in order to increase the stealth of transmission.

In the second radio station, after the call pulse arrives from the output of the majority circuit of the processing and control unit 17 at time t ₃ (see timing diagrams in FIG. 3), the standard time interval starts up to time t ₄ , at the end of which a response signal is sent for the first radio station also of 6 pulses. In other words, the call impulse from the first radio station gives a “start” to the new PRD interval in the second radio station and thus the alignment of the intervals of the two radio stations occurs without taking into account the propagation time of the radio signals.

And after this PRD interval in the second radio station, from the moment of time t ₄ , the standard PFP interval begins.

The response signal from the second radio station arrives at the first radio station at time t ₅ in the PFP interval and, using the majority scheme, one response pulse is extracted from this response signal. This means that in the second radio station, in block 17, from the received call signal, the beginning and end of the PfP and Ppd intervals were aligned with respect to the first radio station without taking into account the delay for the passage of radio signals, i.e. pre-synchronization between two radio stations has occurred. If the expected response signal did not arrive at the first radio station, then the call signal is repeated (t ₇ ) until the response signal arrives.

After that, for more accurate synchronization and continuous correction (tracking) of the beginning and end of each interval, the reference input of the central frequency converter of the first radio station is switched from the local reference frequency divider DOCH 20 from the local reference generator OG 19 to the reference signal generated from the response signal of the second radio station (t ₈ -t ₉ ) in FOS 24. To do this, first verify the accuracy of the clock signals received from FOS 24 via the input-output bus from the bus from the first output of the processing and control unit 17. After establishing in FOS 24 the response sync hrosignal to the reference signals from the DOCH 20 is sent from FOS 24 on the input-output bus to the bus from the first output of block 17, a signal allowing the command from the processing and control unit 17 to switch keys 21 and 22. As a result, to the DFKD 25 reference input now the clock pulses from the first output of the FOS 24 and all further intervals in the receiver of the first radio station and all the intervals in the transmitter of the second radio station are now generated from one exhaust gas 19 in the second radio station.

Similarly, the reference input of the DSC of the second radio station is switched from the local divider of the reference frequency DOCH 20 from the local exhaust gas 19 to the reference signal generated from the first radio station (t ₉ -t ₁₀ ) in FOS 24.

As a result, all further intervals in the receiver of the second radio station and all intervals in the transmitter of the first radio station are now formed from one reference generator OG 19 in the first radio station.

Thus, between radio stations after switching the reference frequencies of the DSC, complete synchronism is established up to a phase and any changes in clock pulses and information pulses in the transmitter of one radio station are exactly repeated at the output of the receiver of another radio station (capture and tracking in the IFAPC system).

Switching reference frequencies CSCH is as follows.

After equalization of time intervals in the first radio station with respect to the second in the FOS block 24 of the first radio station, the reliability of the clock pulses generated from the response signal (according to the majority scheme), which should arrive at the DFKD reference input 25 through key 22, is checked instead of the reference pulses from DOCH 20 coming through the key 21. If the reliability of these pulses is established, then a certain signal is sent from FOS 24 via the input-output bus to the processing and control unit 17, so that from the first output of the processing and control unit 17 along w otherwise there could be a signal to turn off the key 21, through which the reference signal from the DOCH 20 was received, and turn on the key 22, through which the reference signal from the FOC 24 will now come. Since the generated response clock pulses from the FOS 24 and the reference pulses operating at that time from the DOCH 20 may slightly differ in phase (see timing diagrams in Fig. 4, time instants t ₂ -t ₄ ), then switching these pulse flows can lead to an undesirable surge in the control voltage at the output of the BFD 26 and, accordingly, the output frequency of the VCO 28 of the synthesizer frequencies. To eliminate the unnecessary surge in the frequency of the DSC, the switching of these reference pulses occurs in the following sequence (see timing diagrams in figure 4).

First, on the bus from the first output of the processing and control unit 17 to the input-output bus of MK 30, a signal is sent through which a log is received from the output of MK 30 through its control bus 32. “1”, which puts the DSC chip (for example, Analog Devices ADF4001 chip) into synchronous Power-Down mode, i.e. into passive energy-saving mode. In this case, the current generator (charge pump) in the BFD 26 of the digital frequency synthesizer switches to the third state, characterized in that the BFD output inside the microcircuit is disconnected from all circuits and its resistance becomes very large (→ ∞).

As a result, the control voltage at the VCO 28 VSC input remains unchanged and the frequency at the VCO 28 output remains unchanged, although the IFAPC ring is broken.

In addition, at the same time frequency dividers DFKD 25 and DPKD 29 signal log. “1” from the output of MK 30 switches to the “reset” state.

Then, with MK 30, an inverse signal is sent to the processing and control unit 17 via the input-output bus 17, through which switching of keys 21 and 22 is allowed from block 17 so that now the reference signal arrives at DFKD 25 of the central clock system through a closed key 22 from FOS 24 , and key 21 was open. Then, the pulse stream from FOS 24, the phase of which is slightly shifted relative to the phase of the pulses from the output of the DOCH 20 and, accordingly, relative to the phase of the pulses from the output of the DPKD 29, will come to the input of the DPCD 25 (see Fig. 4, time instants t ₃ -t ₄ ).

After switching the keys 21 and 22, the microcontroller MK 30 on the control bus 32 of the digital part of the digital clock system 31 (the first bus) gives a log signal. "0", which switches the DSC from synchronous Power-Down mode to normal mode and the DFKD 25 and DPKD 29 counters start a simultaneous (synchronous) count of input pulses (see Fig. 4, time instants t ₄ -t ₇ ). In other words, a general “start” has been given to the dividers DPKD 29 and DFKD 25. Now the pulses from the DPKD 29 are phase-locked with pulses from DFKD 25 generated from FOS 24. In this case, switching the reference frequency sources at the input of the digital clock eliminates the frequency jump at the output VCO 29.

Then, the working mode of information exchange begins, and only after this, at the command from the first output of block 17, the third key 23 is turned on, allowing the response clock pulses from the FOS 24 to the DOCH 20 reset input (see Fig. 4, times t ₆ -t ₇ ).

As a result, the reference pulses of the same frequency and the same phase are formed at the output of the local DOCH 20 and at the output of the FOS 24, which allows you to instantly switch the frequency synthesizer to the reference signal from the local reference generator at any time and to maintain synchronism and phase matching in the operation of two radio stations.

In the same way, in the second radio station, after the clock pulses from FOS 24 arrive at the reference input of the local DSC, these clock pulses begin to arrive at the reset input of the local reference frequency divider DOCH 20.

As a result, in the second radio station, at the output of the local DOCH 20 and at the output of the FOS 24, flows of clock pulses of the same frequency and the same phase are formed, which also allows you to instantly switch the frequency synthesizer of the second radio station to the reference signal from the local reference OG 19 generator at any time and maintain synchronism and common mode in the operation of two radio stations.

In the event of a signal loss (no pulses in the signal window), the communication system leaves the operating mode and switches to the calibration and signal search mode.

The ability of the proposed device to work is determined by the fact that the input units are typical and can be performed on a well-known element base. High-frequency keys can be made based on the HEF4066B chip from Philips Semiconductors. As frequency synthesizers, high-speed DSCs based on the IFAPH system can be used (see, for example, patent for invention No. 2379830 dated 10.28.2008). The digital part of the DSC is performed on an ADF4001 chip from Analog Devices. A microcontroller type C8051F220 manufactured by SILABS (CYGNAL) is used to control the corresponding blocks of the frequency synthesizer.

Thus, the proposed communication system UWB signals in comparison with the prototype has the following advantages.

1. Improved performance when entering synchronism between two radio stations, because the receiver does not have a lengthy search process with a temporary signal window for an input UWB pulse.

2. Synchronization between the transmitter of one radio station and the receiver of another radio station occurs with an accuracy of phase, because all intervals, positions within the intervals, as well as short UWB communication pulses in the middle of these positions are formed from one reference generator on the transmitting side of the communication channel. In other words, this is the most complete synchronization based on common-mode systems; it provides fundamentally higher stability and accuracy of the operational parameters of the communication system.

3. Full synchronization with an accuracy of up to a phase from one reference oscillator eliminates the need to use precision quartz oscillators and makes it possible to work with ultra-high-speed mobile communication objects.

4. Compared with the prototype, the proposed communication system has a higher noise immunity and reliability both when entering synchronism and when transmitting information due to the use of position-interval coding and majority schemes to isolate clock pulses and information signals.

5. The use of majority schemes for the allocation of clock pulses not only helps to increase the accuracy and stability of synchronization, but also allows you to flexibly adjust the output power of the transmitter to ensure noise immunity and optimal power consumption, as well as to increase the secrecy of transmission.

In addition, a pulsed UWB communication system based on the transmission of ultrashort single pulses following each other with a large variable duty cycle (20-1000), allows to obtain a noise-like, ultra-wideband (up to ten GHz) spectrum of the emitted signal with a low level of spectral components that are not affect the performance in the common frequency band of other radio systems.

The proposed technical solution is new, because neither public methods nor devices are known that allow synchronization between pulse UWB radios with phase accuracy and to stably maintain this synchronization under the influence of various adverse conditions and in high-speed mobile devices.

Information sources

1. US 2003/0067963 A1 Mode Controller For Signal Acquisition And Tracking In Ultra Wide Band Communication System. Timothy R. Miller, Gerard P. Lynch, Deepak M. Joseph. 04/10/2003.

2. US 6925109 "Method and system for fast acquisition of ultra-wideband signals". James L. Richards, Mark D. Roberts. 08/02/2005.

3. I.J. Immmoreev, A.A. Sudakov, "Ultra-Wideband Interference Resistant System for Secure Radio Communication with High Data Rate", ICCSC′02, St. Petersburg, Russian Federation, June 2002, pp. 230-233.

4. I.Ya. Immoreev, A.A. Sudakov, “Ultra-wideband noise-immunity system of covert communications with a high data transfer rate”. Collection of reports of the All-Russian Scientific Conference. Murom, July 1-3, 2003 - Murom: Publishing house-printing center MI VlSU, 2003, pp. 435-440.

5. RU No. 2354048. Method and communication system with fast entry into synchronism by ultra-wideband signals. Kyshtymov G.A., Bondarenko V.V. et al. Published on April 27, 2009 Byul. No. 12.

6. I.I. Petrovsky et al. “Logical ICs KR1533, KR1554” Reference. In two parts. Moscow, Binom, 1993

7. Golub V.S. New frequency synthesizers of the ADF4xxx series. // Chip News. 2002. No. 4, S.20-23.

Claims (1)

A communication system with ultra-wideband signals with increased accuracy and stability of synchronization between interacting radio stations, consisting of at least two radio stations, each of which has a common, transmitting and receiving part, the common part containing a series of connected transmit / receive switch, a broadband filter and an antenna; the transmitting part comprises a series-connected buffer device of the transmitter and an ultra-wideband pulse generator; the receiving part contains a low-noise amplifier, an attenuator, a power divider in two channels (signal channel and noise channel) connected in series; the signal channel threshold device and the signal channel buffer device, the output of which is connected to the first input of the processing and control unit, are connected in series; the noise channel threshold device and the noise channel buffer device, the output of which is connected to the second input of the processing and control unit, are connected in series; in addition, the first output of the processing and control unit is connected by a bus to the inputs of the threshold voltage conditioners of the signal and noise channels, with the second inputs of the attenuator and the receive / transmit switch, the second output of which is connected to the input of the low-noise amplifier, and the second output of the processing and control unit is connected to the input of the transmitter buffer device, the output of the ultra-wideband pulse generator is connected to the first input of the receive / transmit switch, the outputs of the threshold channel voltage generators and to the noise channels are connected respectively to the second inputs of the threshold devices of the signal channel and the noise channel, the input-output of the processing and control unit is information input-output, characterized in that the reference generator, the reference frequency divider, the first key, the output of which is connected to the output, are introduced the second key and the signal input of the frequency divider with a fixed division ratio; a response synchronizer, the first output of which is connected to the signal input of the second key, the second output is connected to the signal input of the third key, the output of which is connected to the reset input of the reference frequency divider; and the input-output bus of the response synchronizer is connected to the bus from the first output of the control and processing unit, to which the control inputs of the first, second, and third keys are connected to the same bus; digital frequency synthesizer (DSC), consisting of a series-connected frequency divider with a fixed division ratio, a frequency-phase detector, a low-pass filter, a voltage-controlled generator, and a frequency divider with a variable division ratio, the output of which is connected to the second input of the frequency-phase detector while the second output of the voltage-controlled generator is connected to the third input ("midrange input") of the processing and control unit, and its second output (frequency input ") is connected to its fourth input ( a phase detector (synchronism indicator output), as well as a microcontroller configured to control the DSC, generate and switch the reference frequencies for it, interact with the processing and control unit, switch the operating modes of the units controlled by it to establish synchronism and phase matching in the operation of two interacting radios; from the first output of the microcontroller, the bus is connected to the control inputs of a frequency divider with a fixed division ratio, a frequency-phase detector and a frequency divider with a variable division coefficient, which form the digital part of the digital clock; from the second output, the microcontroller is connected via the input-output bus to the bus from the first output of the processing and control unit, the fifth input (“exhaust gas input”) of which is connected to the output of the reference generator; wherein the first output of the power divider into two channels is connected to the input of the threshold device of the signal channel, and the second output is connected to the input of the threshold device of the noise channel, and the processing and control unit is configured to analyze and process the received signals, adjust the sensitivity and dynamic range of the receiving part by the results of the analysis, joint work with the microcontroller on the formation and switching of the response and own reference frequencies for the DSC, switching the operating modes of the blocks controlled by it in and generating signals from the input information.

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