RU2325699C1 - Graphic conveyor and method for early depth detection - Google Patents

Abstract

FIELD: technological processes.

SUBSTANCE: invention is related to graphic engines. Technical result is achieved because graphic conveyor includes multitude of sequentially located processing stages, where imaging pixels data is visualized from input data of elementary objects. Processing stages include at least texturing stage and depth testing stage, and depth testing stage may be located earlier in the graphic conveyor than the texturing stage.

EFFECT: reduces consumed carrying capacity and power.

16 cl, 5 dwg

Description

Cross reference to related application (s)

Priority is claimed for US provisional patent application No. 60 / 550,018 of March 3, 2004 and US provisional patent application No. 60 / 550,024 of March 3, 2004, the entire contents of which are incorporated herein by reference.

State of the art

1. The technical field to which the invention relates.

The present invention relates generally to graphics processors, and more specifically, the present invention relates to a three-dimensional graphics pipeline in which the depth testing step is placed at the beginning in the pipeline to minimize the bandwidth and / or power consumption.

2. Description of the Related Art

Graphic machines were used to display three-dimensional (3D) images on stationary display devices, such as computer and television screens. These machines are typically contained in desktop systems powered by conventional AC wall outlets, and thus are not significantly constrained by power limitations. However, recent trends are the inclusion of three-dimensional graphics machines in handheld devices powered by batteries. Examples of such devices include mobile phones and personal digital assistants (OCAs). Unfortunately, however, conventional graphics machines consume large amounts of power and are thus not suitable for these low-energy operating conditions.

Figure 1 depicts a schematic representation of the main pipeline rasterization Open GL (open graphics language) contained in a conventional three-dimensional graphics machine. As shown, the pipeline of this example includes a step 101 for setting up triangles, a stage 102 for shading pixels (minimum image elements), a stage 103 for texture mapping, a stage 104 for smoothly blending (mixing) textures, a stage 105 for testing clipping, a stage 106 for alpha testing, a stage 106 107 stencil testing, stage 108 depth testing, stage 109 alpha conjugation (weighted blending of mixed colors) and stage 110 logical operations.

In three-dimensional graphics systems, each object to be displayed is usually divided into surface triangles defined by vertex information, although other elementary shapes can be used. Also typically a graphics pipeline is designed to process successive packets of triangles of an object or image. The triangles of any given package can visually overlap each other within a given scene.

With reference to FIG. 1, then in it the stage 101 of setting up the triangles “tunes in” each package of triangles using computational coefficients to be used in the calculations performed at later pipeline stages.

The pixel shading stage 102 uses vertex information to calculate which pixels are covered by each triangle from the processed triangle packet. Since triangles can overlap, multiple pixels of different depths can be located at the same point on the screen display device. In particular, the pixel shading step 101 interpolates the shading (lighting amount), color value, and depth value for each pixel using vertex information. For this purpose, any of a variety of shading methods can be selected and shading operations can be performed based on triangles, vertices or pixels.

The texture mapping step 103 and the texture smooth blending step 104 act to add and mix textures in each pixel of the processed triangles package. In the most general sense, this is accomplished by mapping predefined textures to pixels in accordance with vertex information. As with shading, you can select many methods to get texturing. Also, a method known as veiling processing (fogging) can be implemented.

Clipping testing step 105 is operative to discard pixels contained in portions (fragments) of triangles that extend outside the field of view of the displayed scene. In general, this is accomplished by determining whether pixels lie within the so-called clipping rectangle.

Alpha testing module 106 conditionally discards a fragment of a triangle (more precisely, pixels contained in a fragment) based on a comparison between the value of the alpha factor (transparency value) associated with this fragment and the reference value of the alpha factor. Similarly, stencil testing conditionally discards fragments based on a comparison between each fragments and the stored stencil value.

The depth testing step 108 (also called Hidden Surface Removal (USP)) discards the pixels contained in the fragments of the triangle based on the depth of these pixels and the depth of other pixels having the same location on the display. In general, this is done by comparing the use of the value of the Z axis (depth value) of the pixel undergoing depth testing with the value of the Z axis stored in the corresponding location of the so-called z-buffer or depth buffer. The tested pixel is discarded if its value along the Z axis indicates that the pixel can be blocked from being observed by another pixel having a value along the Z axis stored in the z-buffer. On the other hand, the value of the z-buffer is overwritten by the value along the Z axis of the tested pixel in the case when the tested pixel cannot be blocked from observation. With this method, the underlying pixels that are blocked from observation are discarded in favor of the overlying pixels.

Alpha-coupling step 109 combines the rendered pixels with pixels previously stored in the color buffer based on the values of the alpha factors in order to achieve transparency of the object.

Logic operation module 110 generally denotes the various remaining pipeline processes for ultimately obtaining pixel display data.

In any graphics system, it is desirable to maintain processor and memory bandwidth to the extent possible while maintaining satisfactory performance. This is especially important with portable or handheld devices where bandwidth may be limited. Also, as previously proposed, there is a specific industry need to minimize power consumption when processing three-dimensional graphics for display on portable or handheld devices.

SUMMARY OF THE INVENTION

In accordance with one aspect of the present invention, there is provided a graphics pipeline for processing pixel data, and it includes a plurality of sequentially executed processing steps by which visualization of pixel data is displayed from input data of elementary objects, where the processing steps include at least a texturing step and a depth testing step, and in which the depth testing step is located earlier in the graphics pipeline than the texturing step.

In accordance with another aspect of the present invention, there is provided a graphics pipeline for processing pixel data, and it includes a plurality of sequentially executed processing steps by which display data is visualized from input data of elementary objects. The processing steps include at least a texturing step, an alpha testing step, and a depth testing step. In addition, the pipeline is dynamically reordered between at least the first and second sequences of stages in accordance with the alpha test state of the processed pixel data. In the first sequence of stages, the depth testing stage is functionally located earlier in the graphics pipeline than the texturing stage. In the second sequence of steps, the depth testing step is functionally located after the texturing step and the alpha testing step.

In accordance with another aspect of the present invention, there is provided a graphics pipeline for processing pixel data, and it includes a depth buffer that stores depth values, and a depth testing step, at which the current depth value of the processed pixel is compared with the previous depth value stored in the buffer depth, and at which a write command is issued to overwrite the previous depth value by the current depth value, based on the comparison result. The graphics processor further includes a recording delay circuit that temporarily delays a recording command issued in the depth testing step, a texturing step in which the processed pixel is received after processing by the depth testing step, and an alpha testing step in which the processed pixel is received after processing by the step texturing. The recording delay scheme depends on the alpha testing stage as to whether to ignore or execute the delayed recording command issued at the depth testing stage.

Brief Description of the Drawings

The above and other aspects of the invention will become more apparent from the following detailed description with reference to the accompanying drawings, in which:

figure 1 is a schematic representation of an example of the main pipeline rasterization Open GL contained in a three-dimensional graphics machine;

FIG. 2 is a schematic representation of a three-dimensional graphical conveyor according to an example of a first embodiment of the present invention; FIG.

3 is a schematic representation of a three-dimensional graphical conveyor according to an example of a second embodiment of the present invention;

4 is a schematic representation of a three-dimensional graphic conveyor according to an example of a third embodiment of the present invention; and

5 is a schematic representation of a three-dimensional graphic conveyor according to an example of a fourth embodiment of the present invention.

Detailed description preferred embodiments

The present invention is at least partially distinguished by placing the depth testing stage at the beginning in the graphics pipeline in order to minimize the power consumption and throughput of the later pipeline stages. Depth testing works to discard pixels that cannot be visible because they are hidden from view by overlying pixels. Thus, by moving depth testing to an early position in the pipeline, hidden pixels are discarded prior to processing at later stages of the pipeline with high throughput and power consumption. Also, pipeline resources are not spent on discarded pixels.

The present invention is also at least partially distinguished by the optional placement of alpha testing, with the location of the testing depth in a three-dimensional graphics pipeline at the beginning. This can be done by dynamically reordering the pipeline depending on whether alpha testing is allowed, or by delaying the recording of depth testing results until the result of alpha testing can be established.

Now the present invention will be described by means of several preferred, but not limiting embodiments. The three-dimensional graphic conveyors described below are intended for visualization of display pixel data from the input data of elementary objects and can be included in appropriately configured three-dimensional graphic machines.

FIG. 2 is a schematic diagram of a three-dimensional graphical conveyor according to an example of a first embodiment of the present invention. As shown, the pipeline includes a triangulation step 201, a pixel shading step 202, a clipping testing step 203, a depth testing step 204, a texture mapping step 205, a texture smooth blending (blending) step 206, an alpha blending step 207, and a logic step 208 operations.

The operations of the respective conveyor stages shown in FIG. 2 may be the same as previously described in connection with the configuration of Open GL in FIG. 1, and accordingly, a detailed description of each step in this description is omitted to avoid redundant information. However, as shown in FIG. 2, the depth testing step 204 is placed in the conveyor in the initial part, and in particular, before the texture mapping step 205.

According to the configuration of FIG. 2, depth testing is performed in the pipeline as early as possible in order to maintain memory bandwidth and power consumption associated with pixels that are ultimately not visible. In other words, throughput and power are not wasted on pixels, which, after all, are not rendered in the displayed image. This is especially beneficial when processing three-dimensional graphics for display on portable or handheld devices.

The embodiment of the example of FIG. 2 does not include alpha testing. This is because alpha testing requires an alpha factor for a pixel, which cannot be calculated until texture mixing has occurred, and pixel depth testing cannot occur until alpha testing confirms that pixel exceeds transparency threshold. Accordingly, in the example of FIG. 2, the depth test is located in front of the texture mapping step to minimize throughput and power consumption, but due to the absence of an alpha test step in the pipeline. Other embodiments of the invention are focused on configurations in which alpha testing is provided despite the early placement of the depth testing stage in the pipeline.

Figure 3 depicts a schematic representation of a graphics pipeline according to an example of a second embodiment of the present invention. As shown, the pipeline includes a triangulation step 301, a pixel shading step 302, a clipping testing step 303, a first depth testing step 304, a texture mapping step 305, a smooth texture blending (mixing) step 306, an alpha testing step 307, a second step depth testing 308, alpha conjugation step 309 and logical operation step 310.

The pixel operations at the respective pipeline stages shown in FIG. 3 can generally be the same as the operations previously described in connection with the Open GL configuration of FIG. 1, and accordingly, a detailed description of each stage is omitted here to avoid redundant information. However, as shown in FIG. 3, the first depth testing stage 304 is placed at the start of the conveyor, and in particular, before the texture mapping stage 305, and the second depth testing stage 308 is located between the alpha testing stage 307 and the alpha conjugation stage 309.

The operational sequence of the stages of the conveyor of FIG. 3 is dynamically reordered depending on whether alpha testing is allowed for the pixel being processed. That is, in the case where alpha testing is not permitted, the conveyor is organized as shown by the reference numeral “a” in FIG. 3 as follows: step 301 of setting up triangles → step 302 of pixel shading → step 303 of clipping testing → step 304 of depth testing → texture mapping stage 305 → texture smoothing (blending) stage 306 → alpha blending stage 309 → logical operation stage 310.

In the case where alpha testing for the pixel is enabled, the steps advance as shown by the reference number “b” in FIG. 3 as follows: triangulation step 301 → pixel shading step 302 → clipping testing step 303 → texture mapping step 305 → step 306 smooth texture blending (blending) → alpha-testing stage 307 → depth testing stage 308 → alpha-coupling stage 309 → logical operations stage 310.

In general, a graphics pipeline includes control bits that are shifted toward the least significant bit of the pipeline along with pixel data. One of these control bits is an alpha test bit. Also in general, when a package of triangles is applied to the pipeline, each triangle of the package will have the same alpha test settings.

Assume that alpha testing is initially prohibited, and accordingly, the pipeline of FIG. 3 is structured according to the reference numeral “a”, so that the first stage 304 of depth testing is performed, and so that alpha testing 307 and second depth testing 308 get around. Suppose further that an alpha test bit is then detected in the pipeline, which indicates that alpha testing is permitted. At this time, data is being discarded locally from depth testing 304 to smooth texture blending (mixing) stage 306, and the first depth testing 304 is omitted, and alpha testing 307 and the second depth testing 308 are invoked (not omitted). With this method, the arrangement at reference position “b” in FIG. 3. Ultimately, when the alpha test bit indicates that alpha testing is prohibited, the pipeline reorders back to the layout at reference position “a”.

4 is a schematic diagram of a graphics pipeline according to an example of a third embodiment of the present invention. As shown, the pipeline includes a triangle setting step 401, a pixel shading step 402, a clipping testing step 403, a first multiplexer 404, a depth testing step 405, a second multiplexer 406, a texture mapping step 407, a texture blending (mixing) step 408, a texture step 409 alpha tests, third multiplexer 410, alpha conjugation step 411 and logical operations step 412 .

The pixel operations of the respective pipeline stages shown in FIG. 4 can generally be the same as previously described in connection with the Open GL configuration of FIG. 1, and accordingly, a detailed description of each stage is omitted here to avoid redundant information. However, as shown in FIG. 4, the depth testing step 405 is placed at the initial part in the pipeline, and in particular, before the texture mapping step 407, and multiplexers 404, 406, and 410 are used to enable dynamic reordering of the conveyor to provide, if necessary alpha testing.

The condition “AT = 0” of FIG. 4 indicates a state where alpha testing is prohibited for processed pixels. In this case, the multiplexer 404 selects an output signal from the clipping testing step 403 and applies it to the depth testing step 405; the multiplexer 406 selects the output signal from the depth testing step 405 and applies it to the texture mapping step 407; and multiplexer 410 selects an output signal from step 408 of smooth blending (mixing) of the textures and applies it to step 411 alpha-pairing. Thus, when AT = 0, the pipeline sequence is as follows: triangle setting stage 401 → pixel shading stage 402 → clipping testing stage 403 → depth testing stage 405 → texture rendering stage 407 → texture smoothing (blending) stage 408 → alpha stage 411 -conjugation → stage 412 logical operations.

When AT ≠ 0, alpha testing is allowed for pixels to be processed. In this case, the multiplexer 404 selects the output signal from the alpha testing step 409 and applies it to the depth testing step 405; multiplexer 406 selects an output signal from clipping testing step 403 and applies it to texture mapping step 407; and the multiplexer 410 selects the output from the depth testing step 405 and applies it to the alpha conjugation step 411. Thus, when AT ≠ 0, the pipeline sequence is as follows: stage 401 of setting up triangles → stage 402 of pixel shading → stage 403 of testing clipping → stage 407 of texture mapping → stage 408 of smooth blending (mixing) of texture → stage 409 alpha testing → stage 405 depth testing → stage 411 alpha-conjugation → stage 412 logical operations.

In each of the embodiments of FIGS. 3 and 4, the three-dimensional graphics pipeline is reordered depending on whether alpha testing is allowed. If alpha testing is permitted, then the depth testing phase is functionally located after the alpha testing stage, since the results of alpha testing are necessary before depth testing. If alpha testing is forbidden, then the depth testing stage is functionally located before the texture rendering stage to eliminate hidden pixels in the initial part of the pipeline, thereby preserving power and throughput.

5 is a schematic representation of an example of another embodiment of the present invention. Like the embodiments of FIGS. 3 and 4, the configuration of FIG. 5 is capable of providing alpha testing at the same time that the depth testing stage is located in the initial part of the pipeline.

5 illustrates a Depth Testing Step (HSR) step 501 (high-speed reader), a texture mapping step 502, a texturing step 503, an alpha testing step 504, a FIFO (first-come-first-serve) scheme 505, and a depth buffer interface 506 and buffer 507 depth. Depth testing step 501, texture mapping step 502, texturing step 503, and alpha testing step 504 form part of a graphics pipeline of a three-dimensional graphics machine.

In operation, the processed pixel arrives through the conveyor to the depth testing step 501, and the value along the Z axis (depth value) of the pixel is compared with the value along the Z axis stored in the corresponding location of the depth buffer 507. This is accomplished by transmitting the read address [addr_r (14: 0)] to the depth buffer 507 via the buffer interface 506 and receiving the Z axis value of the depth buffer [depth_r (15: 0)] stored in the depth buffer 507. The value on the Z axis of the pixel and the value on the Z axis of the depth buffer are compared, and if the comparison result indicates that the pixel may be invisible, the pixel is effectively discarded. On the other hand, if the comparison result predicts that the pixel may be visible, a delayed write process to the buffer is performed, as described below.

Assuming that the FIFO circuitry 505 is not complete, as indicated by the [fifo_full] signal, the delayed write process to the buffer is performed by issuing the FIFO write command [fifo_write], and then writing the write address signal to the buffer [addr_w (14: 0)], new values along the Z axis of the pixel [depth_w (15: 0)] and the alpha test signal [alpha_test] in the FIFO scheme 505. The buffer write address signal [addr_w (14: 0)] is indicative of the corresponding location of the processed pixel in the depth buffer 507. The new value on the Z axis of the pixel [depth_w (15: 0)] represents the value on the Z axis of the processed pixel (which passed the depth test). The alpha test signal [alpha_test] indicates whether alpha testing is allowed for the pixel being processed.

Like the buffer write address signal [addr_w (14: 0)], the new value along the Z axis of the pixel [depth_w (15: 0)] and the alpha test signal [alpha_test] are shifted through the FIFO circuit 505, the processed pixel is simultaneously subjected to texture mapping and texturing by texture mapping step 502 and texturing step 503, respectively. The depth "n" of the FIFO circuit 505 is preferably equal to the sum of the pixel capacities of the pipeline stages located between the depth testing step 501 and the alpha testing step 504. In this embodiment, the depth of the FIFO circuitry 505 is equal to the sum of the pixel information capacities of the texture mapping stage 502 and the texturing stage 503. As a result, the pixel will be processed on its way to the end of the FIFO scheme 505 in time matching, which coincides with the pixel processing by the texture mapping stage 502 and the texturing stage 503.

After texture mapping and texturing, the processed pixel is then applied to alpha testing step 504. At this time, for a pixel, alpha testing is either allowed or alpha testing is not allowed.

If alpha testing is not allowed for a pixel, the pixel is sent down the pipeline for further processing, and the [valid_pixel] signal is sent to the depth buffer interface 506. Assuming the FIFO circuit 505 is not empty, as indicated by the [fifo_empty] signal, the depth buffer interface responds to the [valid_pixel] signal with a read command [fifo_read] in the FIFO circuit 505, and reads the write address signal in the [addr_w buffer (14: 0 )], the new value on the Z axis of the pixel [depth_w (15: 0)] and the alpha test signal [alpha_test]. Then, the depth buffer interface 506 updates the depth buffer 507 by accessing the depth buffer 507 at the address [addr_w (14: 0)] and overwriting the new value along the Z axis of the pixel [depth_w (15: 0)] in the depth buffer 507.

If alpha testing is enabled for a pixel, alpha testing step 504 compares the alpha value of the processed pixel with a reference value. If the pixel passes alpha testing, the signal [alpha_pass] is passed to the depth buffer interface 506, and the pixel is sent down the pipeline for further processing. If a pixel alpha test fails, an [alpha_fail] signal is transmitted to the depth buffer interface 506 and the pixel is effectively discarded.

Assuming again that the FIFO circuit 505 is not empty as indicated by the [fifo_empty] signal, the depth buffer interface, in response to the [alpha_pass] and [alpha_fail] signals, issues a read command [fifo_read] to the FIFO circuit 505 and reads the write address signal in the buffer [addr_w (14: 0)], the new value on the Z axis of the pixel [depth_w (15: 0)] and a signal that allows alpha testing [alpha_test]. If the [alpha_fail] signal is enabled, the depth buffer interface 506 does not update the depth buffer 507 with a new value on the pixel axis Z [depth_w (15: 0)]. On the other hand, if the [alpha_pass] signal is activated, the depth buffer interface 506 updates the depth buffer 507. That is, the depth buffer interface is formed to the depth buffer 507 at the address [addr_w (14: 0)] and overwrites the new value along the Z axis of the pixel [depth_w (15: 0)] in the depth buffer 507.

The implementation described above in connection with FIG. 5 includes a circuit (eg, a FIFO circuit) that temporarily stores depth test results. The actual recording of a new value along the Z axis in the depth buffer is delayed until the results of alpha testing associated with the new pixel are available. If alpha testing is passed, the new value along the Z axis of the new pixel is stored in the depth buffer. If alpha testing fails, this does not happen. If there is no alpha testing, the new value on the Z axis can be recorded immediately, but only after any values on the Z axis are recorded that are in the process of solving alpha testing. The signal [alpha_test] can be used for this purpose. That is, if the results of all the z-axis values that are being processed do not show alpha testing, the depth buffer interface can be configured to immediately read from the FIFO circuitry 505 and update the depth buffer 507 accordingly.

By delaying the update of the depth buffer waiting for the result of alpha testing, as in the embodiment of FIG. 5, the depth testing step can be located at the initial part of the pipeline to avoid processing later hidden pixels, thereby preserving power consumption and throughput.

In the drawings and in the description, typical preferred embodiments of the present invention have been disclosed, and although specific examples have been formulated, they are used only in a universal and descriptive sense, and not for the purpose of limitation. Therefore, it should be understood that the scope of the present invention should be construed by the appended claims, and not by the described embodiments.

Claims (16)

1. A graphics pipeline for processing pixel data, comprising a plurality of sequentially arranged processing steps that visualize display pixel data from input data of elementary objects, wherein the processing steps include at least a texturing step, an alpha testing step and a depth testing step, wherein the pipeline is dynamically reordered between at least the first and second sequences of stages in accordance with the alpha testing state of the processed pixel data, in which in the first sequence of stages corresponding to the forbidden state of alpha testing, the stage of testing depth is functionally located earlier in the graphics pipeline than the stage of texturing, and in which in the second sequence of stages corresponding to the allowed state of alpha testing, many sequential processing steps include there are two stages of depth testing, and the first stage of depth testing is functionally located earlier in the graph. skom conveyor than texturing step, and wherein the second depth test stage situated after step functionally texturing and alpha testing. 2. The graphics pipeline according to claim 1, further comprising a depth buffer that stores depth values obtained by the depth testing step, in which the alpha testing step is located after the texturing step, and in which the storage of depth values in the depth buffer is temporarily delayed by the control of the alpha step -testing. 3. The graphics pipeline according to claim 1, further comprising a plurality of multiplexers operatively connected between the processing stages of the pipeline and controlled in accordance with the alpha test state of the processed pixel data. 4. The graphics pipeline according to claim 3, in which the plurality of multiplexers comprises a first multiplexer that applies the output from the previous pipeline to the depth testing stage when the alpha test state is disabled and that applies the output from the alpha test to the stage depth testing when the alpha testing state is enabled, the second multiplexer that applies the output from the depth testing stage to the texturing stage when the alpha state alpha testing is forbidden, and which applies the output from the previous pipeline stage to the texturing stage when the alpha test state is enabled, and a third multiplexer that applies the output from the texturing stage to the next stage when the alpha testing state is forbidden, and which applies the output from the depth testing stage to the next stage when the alpha testing state is enabled. 5. The graphics pipeline according to claim 4, in which the previous stage is a test stage clipping. 6. The graphics pipeline according to claim 5, in which the subsequent stage is an alpha-conjugation stage. 7. The graphics pipeline according to claim 1, wherein the texturing step comprises a texture mapping step and a smooth blending (blending) step of the textures. 8. The graphics pipeline according to claim 1, in which the pixel data of at least one stage of the graphics pipeline is reset when switching between the first and second sequences of stages. 9. A graphics pipeline for processing pixel data comprising a plurality of sequentially arranged processing means that visualize display pixel data from input data of elementary objects, in which the processing means include at least texturing means, alpha testing means and depth testing means, wherein the pipeline is dynamically reordered between at least the first and second sequences of stages in accordance with the alpha test state of the process pixel data, in which in the first sequence of stages corresponding to the forbidden state of alpha testing, the depth testing tool is functionally located earlier in the graphics pipeline than the texturing means, and in which in the second sequence of stages corresponding to the allowed state of alpha testing, there are many sequential processing steps includes two depth testing means, the first depth testing means being functionally located used in the graphics pipeline than the texturing means, and wherein the second depth testing means operatively positioned after the texturing means and means for the alpha test. 10. The graphics conveyor according to claim 9, further comprising means for storing depth values obtained by depth testing means, in which alpha testing means is located after the texturing means, and in which the storage of depth values in the means for storing depth values is temporarily delayed by alpha means testing. 11. The graphics pipeline according to claim 9, further comprising a plurality of multiplexing means operatively connected between the processing means of the pipeline and controlled in accordance with the alpha test state of the processed pixel data. 12. The graphics pipeline of claim 11, wherein the plurality of multiplexing means comprises first multiplexing means that applies the output from the previous conveyor means to the depth testing means when the alpha testing state is disabled and which uses the output from the alpha testing means to the depth testing means, when the alpha testing state is enabled, a second multiplexing means that applies the output from the test means depth to the texturing means when the alpha test state is disabled, and which applies the output from the previous pipeline means to the texturing means when the alpha testing state is enabled, and the third multiplexing tool that applies the output from the texturing means to the subsequent means when the alpha testing state is prohibited, and which applies the output from the depth testing means to the subsequent means, to When the alpha test state is enabled. 13. The graphics pipeline of claim 12, wherein the previous tool is a clipping test tool. 14. The graphics pipeline according to item 13, in which the subsequent tool is an alpha-conjugate. 15. The graphic conveyor according to claim 9, in which the texturing means comprises a texture display means and a means for smoothly blending (mixing) the textures. 16. The graphics pipeline according to claim 9, in which the pixel data of at least one means of the graphics pipeline are reset when switching between the first and second sequences of means.

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