RU2320071C1 - Phase-shifting device - Google Patents

Abstract

FIELD: transformation equipment engineering, possible use for controlling reverse thyristor transformer of constant current or thyristor voltage regulator, for example, to ensure smooth launch of asynchronous electric motors.

SUBSTANCE: device contains control signal source (input of phase-shifting device), adder, amplitude modulator, integrator, 2 relay elements, logical element "XOR", three logical elements "2AND", subtracting "n"-bit binary counter, input for connecting a supply of supporting voltage, generator of stable frequency impulses, adding "n"-bit binary counter, digital comparator, logical element "kAND", where n>k, mono-stable multi-vibrator, logical element "2OR", input for connecting the source of control impulses for power thyristors. Device belongs to the class of integrating systems with two digital scanning functions. One scan is independent and is generated due to generator of stable frequency impulses. The second scan is dependent, which is generated from control signal, and transformed due to impulse signal from output of voltage transformer to impulse frequency. Command for managing power thyristors is generated at the time moments when numeric values of independent and dependent scanning functions are equal or exceeded.

EFFECT: increased interference resistance, increased precision.

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Description

The invention relates to the field of converter technology and can be used to control a reversible thyristor DC converter or a thyristor voltage regulator, for example, for smooth starting of asynchronous electric motors.

Known pulse-phase control systems (SIFU), made on the basis of sequentially connected synchronization channel, sawtooth voltage generator, relay element and control pulse shaper (Control of DC valve electric drives / E.D. Lebedev, V.E. Neymark, M.Ya. Pistrak, O.V.Slezhanovsky. - M .: Energy, 1970. - 199 p.). The sawtooth voltage generator and the relay element together form a phase shifting device (FSU). The principle of operation of the device is based on a direct comparison of the sawtooth voltage signal with a control signal and at the moment of their equality, the thyristor control angle is formed.

SIFU data belong to the class of systems with "vertical" control, characterized by low noise immunity and reliability. In particular, to limit the minimum and maximum thyristor control angles in such schemes, a method is used to limit the linear amplitude of the static characteristic of the amplifier connected to the input of the control signal, based on, for example, counter-series connection of an amplifier of two zener diodes (Sledzhanovsky O.V. ., Biryukov A.V., Khutoretsky V.M. Devices of the Unified Block Control System of Discrete Type (UBSR-D). - M.: Energy, 1975. - 256 p.). At a high level of interference signals, nonlinear distortions arise due to saturation of the amplifier, which entails a decrease in its transmission coefficient and a deterioration in the quality indicators of SIFU as a whole (Tsytovich L.I., Suvorov G.V. Influence of periodic interference on the dynamic characteristics of a relay operational amplifier // Electrotechnical industry. Ser. Electric drive. - 1978. - Issue 1 (63). - S.23-25).

Famous SIFU (A.S. 873374 USSR, N02Z 13/16. Device for pulse-phase control of a valve converter / Gafiyatullin R.Kh., Suvorov G.V., Tsytovich L.I., Osipov O.I. et al. (USSR) - No. 2680999/07, claimed 02.11.78; Publ. 15.10.81, Bull. N38), consisting of integrating self-oscillating converters synchronized with the corresponding phase of the mains voltage, adders, reference signal sources, control pulse shapers.

The functions of the FSF are performed by self-oscillating converters based on a series-connected adder, integrator and relay element, the output of which is connected to a control pulse shaper and the first input of the adder. The control signal is supplied to the second input of the adder. The synchronization signal is connected to the third input of the adder. The output of the driver pulse control is connected to the control electrode of the power thyristor.

, пропорциональной амплитуде

и периоду Т_C напряжения сети, где А - амплитуда выходных импульсов релейного элемента (Цытович Л.И. Развертывающий операционный усилитель с перестраиваемой полосой пропускания // Приборы и техника эксперимента. - М.: АН СССР, 1979. - N4. - С.149-152). В результате повышенная помехоустойчивость СИФУ достигается ценой значительного ухудшения ее динамических показателей. Кроме того, ограничение углов управления тиристорами здесь также достигается за счет введения в схему входного усилителя-ограничителя, подключаемого к второму входу сумматора (вместо сигнала управления), что приводит к снижению помехоустойчивости СИФУ в целом.When operating in the external synchronization mode, the FSFs acquire the properties of a first-order aperiodic filter W (p) = 1 / (1 + Tr) with a time constant

proportional to the amplitude

and the period T _{C of the} mains voltage, where A is the amplitude of the output pulses of the relay element (Tsytovich LI Deploying operational amplifier with tunable bandwidth // Instruments and experimental equipment. - M.: USSR Academy of Sciences, 1979. - N4. - P. 149-152). As a result, increased noise immunity of SIFU is achieved at the cost of a significant deterioration in its dynamic performance. In addition, limiting the control angles of thyristors here is also achieved by introducing into the circuit an input amplifier-limiter connected to the second input of the adder (instead of a control signal), which leads to a decrease in the noise immunity of SIFU as a whole.

Closest to the proposed technical solution is a phase-shifting device with two functional (depending on the input signal) expanding functions based on analog-to-digital signal processing (Pat. For invention No. 2288532 RF, IPC ⁷ Н02М 1/08. Phase shifting device / L.I. Tsytovich, M.M. Dudkin. - No. 2005114902/09; application. 13.05.05; publ. 27.11.06, Bull. No. 33).

The FSU consists of a serially connected control signal source (“input” of the phase-shifting device), a voltage to pulse frequency converter (IF) and the first 2I logic element, the output of which is connected to the counting C-input of the summing and subtracting counters. The input source of the impulses for setting the initial conditions in the counters is connected to the installation R- and S-inputs of the summing and subtracting counters, respectively, the outputs of which are connected to a digital comparator. The direct output of the comparator is connected to the first input of the second 2I element, and the inverse output of the digital comparator is connected to the second input of the first 2I element. The output of the second logic element "2I" is the "output" of the phase-shifting device, and its second input is connected to the thyristor control pulse source.

The IFF, which is part of the FSU, consists of series-connected elements - an amplitude modulator, an adder, an integrator and a relay element, the output of which is the input of the first logic element "2I" phase-shifting device, and is simultaneously connected to the first input of the amplitude modulator, as well as to the second input adder. The second input of the amplitude modulator is connected to the source of the control signal (“input” of the phase-shifting device).

At the moment of formation of the pulse from the output of the synchronization device, the summing counter goes into the zero state, and the subtracting counter goes into the state of the maximum number N _max . Under the action of the counting pulses from the output of the IF, the number N ₁ (t) is accumulated in the summing counter, and the number N _max decreases in the subtracting counter in proportion to the value of the control signal. When the equality N ₁ (t) = N ₂ (t) is fulfilled, a signal corresponding to the logic state “0” is generated at the inverse output of the digital comparator, the first logic element “2I” closes and the counting stops. The signal corresponding to the logic state “1” opens the second logic element “2I” from the direct output of the digital comparator and a control pulse is applied to the power thyristor. As the amplitude of the input signal increases, the frequency of the output IF pulses increases, which leads to a corresponding change in the angle of control of the thyristors.

The disadvantage of the prototype device is also its relatively low noise immunity, which is explained as follows. The limitation of the minimum thyristor control angle α _min in such FSFs is carried out automatically by selecting the maximum frequency of the output IF pulses. In the same cases when fixing α _max is required, it is necessary, as in previous versions of the FSD, to include at the input of the IF the amplifier-limiter of the input exposure level with all the ensuing consequences for the noise immunity of the FSU. Obviously, the most acceptable option for limiting a _max would be the formation of this type of digital scan, in which the maximum control angle of the thyristors would automatically be limited directly to the totalizing counter. In addition, to reduce α _min (expanding the control range in the region of small control angles), the frequency of the output IF pulses should be as high as possible. This is achieved by reducing the time constant of the integrated channel, or by reducing the switching thresholds of the relay element of the IF. However, any of the listed options leads to a decrease in the noise immunity of the FSO as a whole. Here, the optimal solution is one that would increase the frequency of the output IF pulses without changing the initial parameters of its elements. In this case, the required noise immunity of the FSB and the accuracy of its operation would be maintained by increasing the bit capacity of the counter and thereby reducing the sampling error of the regulation of the angle of control of the thyristors.

The basis of the invention is a technical problem, which consists in increasing the accuracy and noise immunity of the phase-shifting device.

The proposed phase-shifting device contains a serially connected control signal source - the “input” of the phase-shifting device, an adder, an amplitude modulator, an integrator and a first relay element, the output of which is connected to the second input of the amplitude modulator, the first logic element “2I”, the output of which is connected to the counting C- the input of the binary "n" -bit subtractive counter, summing the "n" -bit binary counter, the outputs of the summing and subtracting counters are connected to the corresponding inputs of the digital to an omparator, the direct output of which is connected to the first input of the second “2I” logic element, the second input of which is connected to the source of thyristor control pulses, the output of the second “2I” logic element is the “output” of the phase shifting device, the pulse source of setting the initial conditions in the counters, and differs from a known device in that a second relay element and an exclusive OR logic element, a reference voltage source, a generator connected in series are connected in series a torus of stable frequency pulses and a third logic element “2I”, connected in series with a logic element “kI”, with k <n, and a single-shot, as well as a logic element “2И”, while the input of the second relay element is connected to the output of the integrator, the second input of the element The exclusive OR is connected to the output of the first relay element, the output of the exclusive OR element is connected to the first input of the first logic element 2I, the voltage reference is connected to the second input of the adder, the output of the third logical element is 2I connected to the counting C-input of the binary "n" -digit totalizing counter, the corresponding outputs of which are connected to the logic element "kI", the output of the one-shot is connected to the S-input of the summing counter and to the first input of the logical element "2OR", the second input of which is connected to the source of impulses for setting the initial conditions in the summing and subtracting binary counters, the output of the 2OR element is connected to the S-input of the subtracting and R-input of the summing counters, the inverse output of the digital comparator is connected to the second inputs mi of the first and third logical elements "2I".

In the study of the proposed device according to patent and scientific and technical literature, no technical solutions were found containing signs equivalent to the claimed object, which allows us to consider it to meet the criterion of "inventive step".

The stated technical problem is achieved by doubling the frequency of the output pulses of the voltage converter to the pulse frequency using the second relay element and the exclusive OR logic block, as well as the formation of a discrete section of the signal of the leading digital scan at the time of limiting α _max using the logical element "kI", single-vibrator and logical element "2OR", which translates the summing and subtracting counters in maximum number mode.

Thus, the proposed FSU has increased accuracy and noise immunity.

The invention is illustrated by drawings:

Figure 1 - functional diagram of the proposed device;

Figure 2 - timing diagrams of the signals of the proposed device;

Figure 3 is a timing diagram of the FSF to explain the principle of limitation α _max ;

4 is a timing diagram of the signals of the voltage to pulse frequency converter.

The FSU includes (Fig. 1) a serially connected control signal source (“input” of a phase shifter), an adder 1, an amplitude modulator 2, an integrator 3, a first relay element 4, an exclusive OR gate 5 and a first 6 logic gate 2I ”, the output of which is connected to the counting C-input of the subtracting“ n ”-bit binary counter 7. The input of the reference voltage source 8 is connected to the second input of the adder 1, and the output of the integrator 3 is the input of the second relay element 9, the output of which is connected to another input logical element 5 "exclusive OR". The output of the first relay element 4 is connected to the second input of the amplitude modulator 2. Links 1-5, 8, and 9 form a voltage to pulse frequency converter (VLF). The output of the stable frequency pulse generator 10 is connected to the first input of the third logic element 11 "2I", the output of which is connected to the counting C-input of the summing "n" -bit binary counter 12. The corresponding outputs of the summing 12 and subtracting 7 counters are connected to a digital comparator 13, the direct output of which is connected to the first input of the second logic element 14 "2I", and the inverse output of the comparator 13 - with the second inputs of the first 6 and third 11 logic elements "2I". The corresponding outputs of the totalizing counter 12 are connected to the inputs of the logic element 15 "kI", the output of which is connected to the input of the single-shot 16, and its output is connected to the S-input of the totalizing counter 12 and the first input of the logic element 17 "2OR", the output of which is connected to S- the input of the subtracting counter 7 and the R-input of the summing counter 12. The second input of the logic element 17 “2OR” is connected to the source 18 of the pulses for setting the initial conditions in the counters 7 and 12, and the source of 19 pulses of the thyristor control is connected to the second input of the second logical element 14 "2I", the output of which is the "output" of the phase-shifting device.

Figure 1-4 introduced the following notation:

X _VH - FSU control signal (“input” of the device);

At _A - the output signal of the amplitude modulator 2;

Y _And - the output signal of the integrator 3;

Y _P1 , Y _P2 - the output signal of the first 4 and second 9 relay elements, respectively;

Y _F - the output signal of block 5 "Exclusive OR";

X ₀ - reference voltage at the input 8;

Y ₀ is the output signal of the one-shot 16;

- сигналы на прямом и инверсном выходах компаратора 13 соответственно;Q,

- signals at the direct and inverse outputs of the comparator 13, respectively;

N ₁ (t), N ₂ (t) - digital scan at the output of the summing 12 and subtracting 7 counters, respectively;

f _i - pulse frequency at the output of block 5 "Exclusive OR";

f _G is the constant frequency at the output of the pulse generator 10;

N _max - the maximum number in the counters 7 and 12;

α _i is the angle of control of power thyristors;

N ₀ <N _max - a predetermined number corresponding to the time limit of the maximum control angle α _max ;

± b - switching thresholds of the first relay element 4;

T ₀ - the period of the output pulses of the first relay element 4;

± A - the amplitude of the output pulses of the first 4 and second 9 relay elements.

The phase shifter units have the following characteristics.

The adder 1 has a single gear ratio for each of the inputs.

The amplitude modulator 2 generates bipolar pulses at the output with the frequency of the output signal of the relay element 4 and with the amplitude of the output signal of the adder 1. The phase shift between the output pulses of the relay element 4 and the amplitude modulator 2 is zero.

The integrator 3 is made with the transfer function W (p) = 1 / T _AND p and the inverting characteristic "input-output".

The relay element 4 is made with a non-inverting hysteresis loop and with switching thresholds ± b symmetrical with respect to the zero level. The relay element 9 has a zero value of switching thresholds and an inverting characteristic "input-output". The output signals of the relay elements 4, 9 vary discretely within ± A.

Block 5 of the “Exclusive OR” function generates a logical signal “1” at the output in the event of a mismatch of the signal signs at the outputs of the relay elements 4, 9 and a logical signal “0” - in case of coincidence of the signs of these signals.

The output signal of the elements 6, 11, 14, 15 corresponds to the logical state “1” provided that there is a logical state “1” at each of their inputs simultaneously.

Counter 12 performs the summation, and counter 7 subtracts the number of pulses from the output of blocks 6, 11, respectively. Entrance "C" is countable. Input "S" is intended for forced installation of counters 7, 12 in the state of the maximum number. The input "R" is intended for forced installation of the counter 12 in the zero state.

The generator 10 generates at the output high-frequency unipolar pulses of a stable frequency.

The digital comparator 13 forms a logical state “1” at the direct output provided that the equality N ₁ (t) ≥N ₂ (t) is satisfied, and at the inverse output, a logical state “1” is formed under the condition that the equality N ₁ (t) ≥N _{2 is} not fulfilled (t).

The single-vibrator 16 generates an output pulse of a given duration synchronously with the time moment of switching unit 15 to the logical state "1".

Block 17 generates an output signal corresponding to the state “1” provided that “1” is present at least at one of its two inputs.

The device operates as follows.

FSU belongs to the class of integrating systems of the "vertical" type with two digital deploying functions. The first - independent N ₁ (t) is formed at the output of the summing counter 12, the second - functional N ₂ (t) (depending on X _BX ) is fed to the input of the comparator 13 from the output of the subtracting counter 7. Links 1, 2, 3, 4, 5 , 8, 9 together form a voltage to pulse frequency converter (VLF), where the frequency of the signal Y _{F is} proportional to the amplitude X _VX .

» цифрового компаратора 13 (фиг.1) формируется логический сигнал «0», логические элементы 6, 11 закрываются и счет в счетчиках 7, 12 прекращается. Сигналом логической «1» с прямого выхода «Q» цифрового компаратора 13 открывается логический элемент 10 и на тиристор подается управляющий импульс. По мере роста амплитуды входного сигнала (фиг.2б) увеличивается частота на выходе блока 5 (фиг.2в), что приводит к соответствующему изменению угла управления α_i тиристорами (фиг.2д).Consider the work of the FSU without taking into account the limitation mode α _max (figa-e). At the time of formation of the pulse "Reset" from the output of the synchronization device (Fig. 1 - input 18, Fig. 2a), the subtracting counter 7 goes into the state of the maximum number N _max , and the totalizing counter 12 is reset (Fig. 2e). In this case, the inverse output of the digital comparator 13 is in the logical state “1”. Under the action of the counting pulses from the output of the generator 10 (Fig.2d), the number N ₁ (t) is accumulated in the summing counter 12, and in the subtracting counter 7 the number N _MAX decreases in proportion to the value of the control signal X _BX (fig.2b, c, d) . When the equality N ₁ (t) ≥N ₂ (t) (fig.2d) on the inverse output

"Digital comparator 13 (figure 1) is formed by a logical signal" 0 ", the logic elements 6, 11 are closed and the counters in the counters 7, 12 are stopped. The logic signal “1” from the direct output “Q” of the digital comparator 13 opens the logic element 10 and a control pulse is applied to the thyristor. As the amplitude of the input signal increases (Fig.2b), the frequency at the output of block 5 (Fig.2c) increases, which leads to a corresponding change in the control angle α _{i of the} thyristors (Fig.2d).

Consider the restriction mode in the FSF of the maximum control angle α _max (figure 3). Using the logical element 15 sets the number N ₀ <N _max at which there is a restriction α _max (figb). With a small value of the control signal X _BX , the digital sweep derivative N ₂ (t) drops due to a decrease in the frequency of the counting pulses from the output of block 5 (Fig. 3a, b). Therefore, in the range α _MAX, the inequality N ₁ (t) <N ₂ (t) is observed and the digital comparator 13 is in the logical state Q = 0. At time moment N ₁ (t) = N _{0, the} logic element 15 goes into the logical state “1” and the one-shot 16 starts (Fig.3c), under the action of the output signal of which the summing 12 and subtracting 7 counters are forcibly set to the N _max position (Fig. .3b). The digital comparator 13 switches to the logical state Q = 1 and a control pulse corresponding to α _max is applied to the thyristors. Subsequently, the “Reset” signal at input 18 (Fig. 3d) resets the totalizing counter 12, confirms the state of the maximum number N _max in the subtracting counter 7, and the FSU returns to its original position. In the future, the process is repeated. Thus, the maximum angle α _{max is} limited in the entire range of the inequality N ₀ ≤N ₂ (t) ≤N _max .

Therefore, the introduction of blocks 15, 16 into the FSF circuit allows one to form a discrete sweep section N ₁ (t) and thereby limit α _max at a predetermined level without using an analog signal limiter amplifier at the FSF input, which increases the noise immunity of the device.

Consider the operation of blocks 1-5, 8, 9, forming the IFF (figure 1). The minimum amplitude of the output pulses of the modulator 2 is set by the reference voltage supplied to the input 8 (figure 1, figa, b). Under the action of the output pulses of modulator 2 in the circuit of elements 2, 3, 4, a stable self-oscillation mode occurs (Fig. 4c), the frequency of which is determined by the time constant T _{AND of the} integrator 3 and the switching thresholds ± b of the first relay element 4. As the value of the control signal increases X _BX (figa) increases the amplitude of the pulses at the output of the modulator 2 (fig.4b), which leads to an increase in the frequency of the output pulses of the first relay element 4 (figv). The output signal of the integrator 3 has a sawtooth shape, limited in amplitude by the switching thresholds ± b of the first relay element 4 (pigv). The second relay element 9 switches at the moment of time of changing the sign of the sawtooth voltage at the output of the integrator 3 (figv, d), as a result of which the output pulses of block 9 are shifted relative to the output pulses of block 4 by 90 el. hail. In this case, the logical element 5 of the “Exclusive OR” function generates a signal whose frequency is twice the frequency of the pulses at the output of the first relay element 4 (figv, d).

Thus, the frequency of the output IF frequency pulses is doubled without changing the parameters of blocks 3 and 4, which positively affects the noise immunity of the FSF. Increasing the frequency of the output signal of the VFD provides the possibility of increasing the bit depth of the counters 7, 12, which reduces the sampling error of the regulation of the angle of control of the thyristors and increases the accuracy of the FSU.

Therefore, due to the introduction of blocks 5, 9, 15, 16, 17, the accuracy and noise immunity of the phase shifting device are increased.

Industrial applicability.

The device under consideration is proposed for use in the reconstruction of electric drives of blowers of workshop No. 2 of OJSC MMK using thyristor control stations for the smooth start-up of asynchronous electric motors.

Due to the introduction of such a system with increased noise immunity and accuracy in operation, the main articles of economic efficiency are:

- saving energy costs as a result of the transfer of electric motors from continuous to off state;

- efficiency from reducing the flow of failures of electrical and technological equipment and reducing the cost of repairs and maintenance.

Thus, the estimated economic effect of the introduction of thyristor voltage regulators for the smooth start of asynchronous electric motors is 4650000 rubles. in year. The payback period is 2.1 years.

Claims (1)

Phase shifting device containing a serially connected control signal source - “input” of the phase shifting device, adder, amplitude modulator, integrator and first relay element, the output of which is connected to the second input of the amplitude modulator, the first logic element “2I”, the output of which is connected to the counting C- the input of the binary "n" -bit subtractive counter, summing the "n" -bit binary counter, the outputs of the summing and subtracting counters are connected to the corresponding inputs of the digital comparator the direct output of which is connected to the first input of the second “2I” logic element, the second input of which is connected to the source of thyristor control pulses, the output of the second “2I” logic element is the “output” of the phase shifting device, the pulse source of setting the initial conditions in the counters, characterized in that a second relay element and an exclusive OR logic element, a reference voltage source, a stable frequency pulse generator, and sequentially connected third logical element “2I”, series-connected logic element “kI”, with k <n, and one-shot, as well as logic element “2OR”, while the input of the second relay element is connected to the output of the integrator, the second input of the element “Exclusive OR” is connected with the output of the first relay element, the output of the “Exclusive OR” element is connected to the first input of the first logic element “2I”, the voltage reference source is connected to the second input of the adder, the output of the third logic element “2I” is connected to the countable C-input of the binary of the “n” -bit totalizing counter, the corresponding outputs of which are connected to the “kI” logic element, the output of the single vibrator is connected to the S-input of the summing counter and to the first input of the “2OR” logic element, the second input of which is connected to the pulse source for setting the initial conditions in summing and subtracting binary counters, the output of the “2OR” element is connected to the S-input of the subtracting and R-input of the summing counters, the inverse output of the digital comparator is connected to the second inputs of the first and third logical elec "2I" cops.

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