RU2307456C1 - Output cascade for rapid action operational amplifier - Google Patents

Abstract

FIELD: radio engineering and communications for usage as output device for amplification of analog signals power (buffer amplifier).

SUBSTANCE: output cascade (dwg. 2) contains first n-p-n (1) and second p-n-p (2) input transistors with combined bases, while emitter of first input n-p-n (1) transistor is connected to collector output of first current mirror (3) and to base of first output p-n-p transistor (4), emitter of second input p-n-p transistor (2) is connected to collector output of second current mirror (5) and to base of second output n-p-n transistor (6), and emitters of first (4) and second (6) output transistors are connected to load (7). Additionally introduced are first p-n-p (8) and second n-p-n (9) auxiliary transistors, while emitter of first auxiliary p-n-p transistor (8) is connected to additional support current supply (11), its base is connected to emitter of second (2) input p-n-p transistor, and collector - to input of first current mirror (3), emitter of first auxiliary n-p-n transistor (9) is connected to second correcting capacitor (12) and to second additional support current supply (13), and collector is connected to input of first current mirror (5).

EFFECT: increased speed of operation.

2 cl, 7 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as an output device for amplifying rapidly changing analog signals in power (buffer amplifier), in the structure of input stages of analog microcircuits for various functional purposes, for example, operational amplifiers with current feedback.

Known schemes for push-pull output stages on n-p-n and p-n-p transistors [1], which have become one of the basic elements of many analog microcircuits, are widely used in the structure of various ULFs and operational amplifiers in both output and input circuits. Due to their good static and other characteristics, such output cascades received the special name “diamond” transistors. Over 50 patents have been issued for their improvement in different countries [1-50].

The closest prototype (figure 1) of the claimed device is the output stage described in US patent application US 2005/0127999 A1 (figure 1) dated 06/16/2005, containing the first npn 1 and second pnp 2 input transistors with integrated bases, the emitter of the first the input npn 1 of the transistor is connected to the collector output of the first current mirror 3 and the base of the first output pnp of the transistor 4, the emitter of the second input pnp of the transistor 2 is connected to the collector output of the second current mirror 5 and the base of the second output npn transistor 6, and the emitters of the first 4 and second 6 output transistors are connected to a load of 7.

A significant disadvantage of the known device is that it has a long transient establishment time (t _fr ) when working with rapidly changing pulsed signals of large amplitude, as well as low values of the maximum slew rate of the output voltage (ϑ _out ).

The main objective of the invention is to increase the speed of the output stage - to reduce by 20-50 times the time to establish the transient process (t _fr ) for a given zone of dynamic error ε ₀ = 10%, and increase the maximum slew rate of the output voltage ϑ _{output by} 20-40 times .

This goal is achieved in that in the output stage (VK) of figure 1, containing the first npn 1 and second pnp 2 input transistors with integrated bases, and the emitter of the first input npn 1 transistor connected to the collector output of the first current mirror 3 and the base of the first output pnp transistor 4, the emitter of the second input pnp transistor 2 is connected to the collector output of the second current mirror 5 and the base of the second output npn transistor 6, and the emitters of the first 4 and second 6 output transistors are connected to the load 7, new elements are introduced and communications, the first pnp 8 and second npn 9 auxiliary transistors, the emitter of the first auxiliary pnp transistor 8 is connected to the first correction capacitor 10 and the first additional reference current source 11, its base is connected to the emitter of the second 2 input pnp transistor, and the collector to the input of the first current mirror 3, the emitter of the second auxiliary npn transistor 9 is connected to the second correction capacitor 12 and the second additional reference current source 13, and the collector is connected to the input of the second current laugh 5.

The scheme of the claimed device in accordance with claim 1 of the claims is shown in the drawing of figure 2.

The drawing of figure 3 shows the inventive VK in the computer simulation environment PSpice on the models of integrated transistors FSUE NPP "Pulsar". In the drawing of FIG. 4, a transition process is shown at the output of the inventive device at various capacitance values of the correction capacitors 10 and 12 (C _s ) obtained as a result of computer simulation of the circuit of FIG. 3.

The drawing of figure 5 shows the transient in the claimed and known devices, which allows you to compare their parameters on the same scale and the same measurement modes.

The drawing of Fig.6 shows a diagram of the inventive VK according to claim 2 of the claims in the environment of PSpice. In this case, the current transfer coefficient of the first 3 (VT30, VT9) and second 5 (VT1, VT29) current mirrors are selected by changing the areas of the emitter junctions of their transistors at the level of K _i = 4. This made it possible to eliminate the correction capacitors 10 and 12 and use the natural capacitances of transistors VT33, VT35 and VT34 to increase the speed.

The drawing of Fig. 7 shows the results of computer simulations of the VC of Fig. 6, which show that the inventive device has (in comparison with the prototype) 40–70 times higher average slew rate of the output voltage and 40–50 times less transient establishment time.

The output stage of figure 2 contains the first npn 1 and second pnp 2 input transistors with combined bases, the emitter of the first input npn 1 transistor connected to the collector output of the first current mirror 3 and the base of the first output pnp transistor 4, the emitter of the second input pnp transistor 2 connected to the collector output of the second current mirror 5 and the base of the second output npn transistor 6, and the emitters of the first 4 and second 6 output transistors are connected to the load 7. The first pnp 8 and second npn 9 auxiliary transistors are introduced into the circuit, p Therefore, the emitter of the first auxiliary pnp transistor 8 is connected to the first correction capacitor 10 and the first additional reference current source 11, its base is connected to the emitter of the second 2 input pnp transistor, and the collector is connected to the input of the first current mirror 3, the emitter of the second auxiliary npn transistor 9 is connected to the second correcting capacitor 12 and the second additional source of reference current 13, and the collector is connected to the input of the second current mirror 5.

In the inventive device of figure 2, the ratio of the areas of the emitter junction of the transistors forming the current mirrors 5 and 3 varies at the level of 1 ÷ 10, which allows the use of correction capacitors 10 and 12 of the capacitance on the substrate and C _Kb transistors VK.

Consider the operation of the inventive device of figure 2.

In static mode, the emitter currents of transistors 1 and 2 are equal to the output currents of current mirrors 3 and 5:

I _E1 = K _i3 · I ₁₁ ,

I _E2 = K _i5 · I ₁₃ ,

where K _i3 , K _i5 - current gain of current mirrors 3 and 5, depending on the ratio of the areas of the emitter junctions of their transistors,

I ₁₁ , I ₁₃ - currents of the sources of the reference current 11 and 13.

In particular cases, the coefficients K K _i3 and _i5 are selected depending on the numerical values of the capacitances 10 and 12 and the equivalent capacitances in the emitter circuits of the transistors 1 (C _Σ1) and 2 (C _Σ2) in the range 1 ÷ 10.

If a positive input voltage pulse close to the supply voltage is applied to the VK input, this causes an almost instantaneous shutdown of transistor 2. In this case, the input pulse is transmitted to the emitter of transistors 1, 4, 9, causing a “jump” in the collector current of transistor 9 and, therefore, Repeater output current 5. This causes a quick recharge of the total equivalent capacitance (C _∑2 ) in the emitter circuit of transistor 2. This capacitance is made up of collector-base capacitors of transistors 8 and 6, as well as capacitance on the output transformer substrate current mirror torus 5. Typical values C _∑2 = 1 ÷ 3 pF.

As computer simulation of the circuits of Fig. 3, Fig. 6 shows, forcing the parasitic capacitance recharge current C _{∑ 2} increases the VC speed by 30–50 times. Moreover, this effect is provided without increasing the input capacitance of the VC and the deterioration of the stability of its static mode.

Information sources

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Claims (2)

1. The output stage of a high-speed operational amplifier containing the first npn (1) and second pnp (2) input transistors with integrated bases, the emitter of the first input npn (1) transistor connected to the collector output of the first current mirror (3) and the base of the first output pnp transistor (4), the emitter of the second input pnp transistor (2) is connected to the collector output of the second current mirror (5) and the base of the second output npn transistor (6), and the emitters of the first (4) and second (6) output transistors are connected to the load ( 7), different t We note that the first pnp (8) and second npn (9) auxiliary transistors are introduced into the circuit, and the emitter of the first auxiliary pnp transistor (8) is connected to the first correction capacitor (10) and the first additional reference current source (11), its base is connected to the emitter of the second (2) input pnp transistor, and the collector to the input of the first current mirror (3), the emitter of the second auxiliary npn transistor (9) is connected to the second correction capacitor (12) and the second additional reference current source (13), and the collector connected to the course of the second current mirror (5). 2. The device according to claim 1, characterized in that the first and second correction capacitors (14) and (12) use natural capacitances on the substrate of active elements of additional reference current sources (11) and (13), and the current transfer coefficients the first (3) and second (5) current mirrors, depending on the ratio of the areas of the emitter junctions of their output and input transistors, are selected more than unity.

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