RU2356171C1 - Adaptive device for data transfer with pseudorandom tuning of working frequency - Google Patents

Abstract

FIELD: physics, radio.

SUBSTANCE: suggested device is related to the field of radio engineering and may find application in adaptive systems of special radio communication for data transfer along radio channel under conditions of deliberate noise complex effect. Device comprises source of information, commutator of speeds, packager, the first and second demultiplexers, M coders, modulator, the first and second antenna-feeder units, clock pulses generator, generator of code sequences, control unit, the first and second analysers of signal quality, the first and second synthesisers of frequencies, generator of pseudorandom sequence, frequency transducer, amplifier of intermediate frequency, demodulator, M decoders, depackager, information receiver, unit of signal element identification, K-circuits of comparison, unit of phase self-tuning, the first, second and third multiplexers.

EFFECT: increased validity of information reception due to adaptation of clock signal to change of noise environment.

10 dwg

Description

The proposed device relates to the field of radio engineering and may find application in adaptive systems of special radio communications for transmitting data over a radio channel under the influence of a complex of intentional interference.

A device for transmitting under conditions of uncertain interference is described in [1], in which an increase in the noise immunity of a radio line under the influence of unsteady interference is achieved in the presence of long-term heterogeneous quality of individual frequency channels.

A known device for transmitting information with pseudo-random frequency tuning (PFC) according to the patent [2], in which the value of the operating frequency is formed according to the pseudo-random law, at pseudo-random times, guaranteed synchronously for both sides of the radio line.

A disadvantage of the above devices is the lack of adaptation of the clock signal to changes in the interference environment.

The closest in technical essence to the proposed is the device described in [3], taken as a prototype.

The functional diagram of the prototype device is shown in figure 1, where the following notation:

1 - source of information (AI);

30 - the first random access memory (RAM1);

6 - modulator;

7 - the first antenna-feeder unit (AFB1);

31 - the first encoder of the write address (KAZ1);

32 - the first encoder read addresses (CAS1);

12, 29 - the first and second frequency synthesizers (MF1 and MF2);

8 - the first generator of clock pulses (GTI1);

33 - the first frequency divider (DCH1);

34 - the second frequency divider (DCH2);

35 - the first driver of bursts of pulses (FPI1);

13 - the first pseudo-random sequence generator (GPSP1);

21 - the second antenna-feeder unit (AFB2);

14 - frequency converter (IF);

15 - intermediate frequency amplifier (UPCH);

16 - demodulator;

36 - second random access memory (RAM2);

20 - information receiver (PI);

37 - second pseudo-random sequence generator (GPSP2);

38 - sync generator (SG);

39 - the second encoder of the write address (KAZ2);

40 - second encoder read addresses (CAS2);

41 - the third frequency divider (DCHZ);

42 - the fourth frequency divider (DCH4);

43 - the second driver of the bursts of pulses (FPI2);

44 - the second clock generator (GTI2).

The prototype device contains AI 1, GPSSP1 13, GPSSP2 37, SCh1 12, SCh2 29, modulator 6, AFB1 7, AFB2 21, ПЧ 14, ППЧ 15, demodulator 16, СГ 38 and ПИ 20, and the output of ГПСП1 13 through СЧ2 12 connected to one input of the modulator 6, the output of which is connected to the input of AFB1 7, the output of AFB2 21 is connected to the first input of the inverter 14, the output of which is connected to the input of the amplifier 15, the output of the amplifier 15 is connected to the input of the demodulator 16, the output of which is connected to the input of the SG 38, the output of which is connected to one input of GPS2 37, the output of which through MF2 29 is connected to the second input of the frequency converter 14, in addition, it contains the first and second opera explicit memory devices (OZU1 30, OZU2 36), the first and second encoders of the write address (KAZ1 31, KAZ2 39), the first and second encoders of the read address (KAS1 32, KAS2 40), the first, second, third and fourth frequency dividers (DCH1 33, DCH2 34, DCHZ 41, DCH4 42), the first and second pulse trainers (FPI1 35, FPI2 43), the first and second clock generators (GTI1 8, GTI2 44). Moreover, the output of AI 1 is connected to the first input of RAM1 30, the output of which is connected to the input of modulator 6, the output of GTI1 8 is connected in parallel to the inputs of DCH1 33, DCH2 34 and FPI1 35, and the outputs of DCH1 33, DCH2 34 and FPI1 35 are connected respectively to the input KAZ1 31, KAS1 32 and GPS1 13, the outputs KAZ1 31 and KAS1 32 are connected to the inputs of RAM1 30, the output of the demodulator 16 is connected to the first input of RAM2 36, the output of which is connected to the input of the inverter 14, the output of the GTI2 44 is connected in parallel to the inputs of the DCHZ 41, DCH4 42 and FPI2 43, and the outputs DCHZ 41, DCH4 42 and FPI2 43 are connected respectively to the inputs of KAZ2 39, KAS2 40 and GPSSP2 37, the outputs of KAZ2 39 and KA C2 40 connected to the inputs of RAM2 36.

The operation of the prototype device is as follows.

The input digital signal is written to RAM1 30 in the cells, according to the commands of KAZ1 31. When N blocks are written, by the command KAS1 32 the information signal is read from RAM1 30 block by block at the speed necessary for transmission. At the same time carry out the transcoding of blocks. The signal read from RAM1 30 is modulated at frequencies determined by GPSSP1 13, each block being modulated at the next frequency. GTI1 8, DCH1 33, DCH2 34 and FPI1 35 are necessary for general synchronization. At the receiving end, the signal after demodulation is recorded from RAM2 36 to the cells determined by KAZ2 39. When N blocks of signal are written to RAM2 36, then by the command KAS2 40 the elements are read from RAM2 36 into the PI 20 with the speed of the original signal, while it is decoded.

In the prototype device, information rate conversion is intended to interleave the bits for subsequent application of the error-correcting code. However, this method is only effective under unintentional interference. In special radio communications, the central direction is to increase noise immunity in the conditions of continuous improvement of radio countermeasures (SRP), in particular, when a radio line with frequency hopping is exposed to suppress one of the delayed interference, effective from the point of view of energy capabilities, in combination with barrage interference in a part of the band ( STD). The application of frequency hopping leads to the allocation of time intervals for synchronization of the radio link and for transferring it from frequency to frequency without loss of message elements at these intervals. The last requirement leads to the conversion of the block into a slot: the information bits are “framed” by the frequency tuning bits (the time spent by the equipment on tuning) and the protection bits (taking into account the desynchronization of generators). The lack of clear bitwise synchronization can negate all the advantages of the frequency hopping system. With this in mind, PSAs act not only on slots with information (delayed interference, tracking over frequencies), but also on slots with clock signals (using STDs). To protect against the latter, it is advisable to introduce a change in the type of clock in the radio link.

However, a change in the type of the clock signal cannot but affect the general structure of the time diagram of the radio line and, as a result, the general construction of the equipment with frequency hopping. Modern data transmission equipment should be designed to operate at different transmission speeds (corresponding to GOST 17422), as well as to protect information from intentional interference by changing the frequency hopping frequency, the type of noise-resistant code and the use of the feedback channel between the receiver and transmitter to analyze the interference situation. Thus, the adaptation of the clock signal should entail the adaptation of the entire timing diagram of the radio link.

The last condition indicates that the unchanged radio line formed by the operation of the prototype device is not able to provide the specified quality of communication throughout the communication session, since the input conditions may change from time to time. Thus, the disadvantage of the prototype device is the low quality of information transfer under conditions of intentional interference. In this case, it becomes necessary to use an adaptive device, which, using the regular search process, constantly searches for the optimum within the limits of an acceptable class of capabilities.

The aim of the proposed work is the introduction of adaptation of the data transmission device with frequency hopping to changes in the interference environment and the reduction of information loss.

To achieve this goal, a device containing a source of information, the input of which is the first input of the device, an information receiver, the output of which is the second output of the device, a modulator and a first antenna-feeder unit connected in series, the output of which is the first output of the device; a pseudo-random sequence generator and a first frequency synthesizer connected to a second signal input of the modulator in series; a clock pulse generator, a second frequency synthesizer, a demodulator, a second antenna-feeder unit connected in series, the input of which is the second input of the device, a frequency converter and an intermediate frequency amplifier, according to the invention, a speed switch, a packetizer, a depacketator, a code sequence generator, a control unit, a block are introduced signal element identification, phase locked loop, first and second signal quality analyzers, first and second demultiplexers, first, second and third multiplexers, M encoders, M decoders and K comparison circuits; in addition, in the information source, modulator, demodulator, pseudo-random sequence generator, first and second frequency synthesizers, it is additionally inputted at the clock input, and in the modulator and demodulator it is additionally inputted at the control input; wherein the input of the information source through the speed switch is connected to the first signal input of the packetizer, the output of which is connected to the signal input of the first demultiplexer, the M outputs of which are connected to the signal inputs of the corresponding M encoders, the outputs of which are connected respectively to the M signal inputs of the first multiplexer, the output of which is connected to the first signal input of the modulator; the demodulator output is connected to the signal input of the second demultiplexer, the M outputs of which are connected to the signal inputs of the corresponding M decoders, the outputs of which are connected respectively to the M signal inputs of the second multiplexer, the output of which is connected to the first signal input of the depacketator, the second signal input of which is connected to (M + 1 ) -th output of the second demultiplexer, and the output of the depacketator is connected to the signal input of the information receiver; also the outputs of the M decoders are connected respectively to the M signal inputs of the first signal quality analyzer, the (M + 1) -th signal input of which is connected to the output of the demodulator; the output of the intermediate frequency amplifier is connected to the first signal input of the phase-locked loop, the output of which is connected to the signal input of the demodulator; the second antenna-feeder unit is configured to separate the signal into service and information components and it additionally introduces a second output connected to the first signal input of the signal element identification unit, the output of which is connected to the signal inputs K of the comparison circuits, the outputs of which are connected respectively to the K signal the inputs of the third multiplexer, the output of which is connected to the second signal input of the phase-locked loop; in addition, the outputs of the M comparison circuits are connected to the M signal inputs of the second signal quality analyzer, the (M + 1) -th signal input of which is connected to the output of the signal element identification unit; the first to tenth outputs of the control unit are connected respectively to the control inputs of the packetizer, first demultiplexer, first multiplexer, modulator, depacketator, second demultiplexer, second multiplexer, demodulator, code sequence generator and third multiplexer, and the output of the code sequence generator is connected to the second signal input of the packetizer ; the outputs of the first and second signal quality analyzers are connected respectively to the first and second inputs of the control unit; the second output of the pseudo-random sequence generator is connected to the signal input of the second frequency synthesizer, the first output of which is connected to an additional third signal input of the modulator, the (M + 1) -th output of the first demultiplexer is connected to an additional fourth signal input of the modulator, and the first frequency synthesizer is additionally introduced the second output connected to the second input of the frequency converter, in the second frequency synthesizer, an additional second output connected to the second signal is introduced th input signal element identification unit; the output of the clock generator is connected to the clock inputs of the information source, speed switch, packetizer, first and second demultiplexers, first, second and third multiplexers, modulator, code sequence generator, control unit, phase locked loop, first and second signal quality analyzers, first and second counters, pseudo-random sequence generator, signal element identification unit, demodulator, depacketator, information receiver, M encoders, M deco By comparing the moat and circuits.

The functional diagram of the proposed adaptive data transmission device with pseudo-random tuning of the operating frequency is shown in figure 2, where the following notation:

1 - source of information (AI);

2 - speed switch (CS);

3 - packer;

4 - the first demultiplexer (D1);

5 ₁ -5 _M - encoders;

6 - modulator;

7 - the first antenna-feeder unit (AFB1);

8 - clock generator (GTI);

9 - code sequence generator (GKP);

10 - control unit (CU);

11 - the first signal quality analyzer (AKS1);

12 - the first frequency synthesizer (MF1);

13 - pseudo-random sequence generator (GPSP);

14 - frequency converter (IF);

15 - intermediate frequency amplifier (UPCH);

16 - demodulator;

17 - the second demultiplexer (D2);

18 ₁ -18 _M - decoders;

19 - depacketizer;

20 - information receiver (PI).

21 - the second antenna-feeder unit (AFB2);

22 - signal element identification unit (BOES);

23 ₁ -23 _K - comparison schemes (SS);

24 - phase-locked loop (BFA);

25 - the third multiplexer (MOH);

26 - the first multiplexer (Ml);

27 - second multiplexer (M2);

28 - second signal quality analyzer (AKS2);

29 - the second frequency synthesizer (MF2).

The proposed device contains a series-connected information source (AI) 1, the input of which is the first input of the device, and a speed switch (KS) 2, the output of which is connected to the first signal input of the packetizer 3, the output of which is connected to the signal input of the first demultiplexer (D1) 4, M outputs are connected to respective signal inputs of encoders May ₁ M 5 _M, whose outputs are connected respectively with the M signal inputs of the first multiplexer (M1) 26, whose output is connected to a first signal input mode Yator 6, a fourth signal input coupled to (M + 1) th output 4. The output D1 of the modulator 6 is connected to the input first antenna-feeder block (AFB1) 7 whose output is the first output device.

In addition, the device contains a second antenna-feeder unit (AFB2) 21 connected in series, the input of which is the second input of the device, a frequency converter (GFC) 14 and an intermediate frequency amplifier (UPCH) 15, the output of which is connected to the first signal input of the phase-locked loop ( BFA) 24, the output of which is connected to the signal input of the demodulator 16, the output of which is connected to the signal input of the second demultiplexer (D2) 17, whose M outputs are connected to the signal inputs of the corresponding M decoders 18 ₁ -18 _M , the outputs are which are connected respectively to the M signal inputs of the second multiplexer (M2) 27, the output of which is connected to the first signal input of the depacketator 19, the second signal input of which is connected to the (M + 1) -th output of D2 17. The output of the depacketator 19 is connected to the signal input of the information receiver (PI) 20, the output of which is the second output of the device.

Also, the outputs of the M decoders 18 ₁ -18 _{M are} connected respectively to the M signal inputs of the first signal quality analyzer (AKS1) 11, the (M + 1) -th signal input of which is connected to the output of the demodulator 16.

The second output of AFB2 21 is connected to the first signal input of the signal element identification unit (BOES) 22, the output of which is connected to the signal inputs of comparison circuits (CC) 23 ₁ -23 _K , the outputs of which are connected to the corresponding K signal inputs of the third M3 25 multiplexer, output which is connected to the second signal input BFA 24. In addition, the outputs

SS 23 ₁ -23 _{K are} connected respectively to K signal inputs of the second signal quality analyzer (AKS2) 28, (K + 1) -th signal input of which is connected to the output of BOES 22.

From the first to the tenth outputs of the control unit (BU) 10 are connected respectively to the control inputs of the packetizer 3, D1 4, M1 26, modulator 6, depacketator 19, D2 17, M2 27, demodulator 16, GKP 9 and M3 25, and the output of GKP 9 connected to the second signal input of the packetizer 3. The output of the AKS1 11 is connected to the first input of the control unit 10, and the output of the AKS2 28 is connected to the second input of the control unit 10.

The first output of the pseudo-random sequence generator (GPS) 13 is connected to the signal input of the first frequency synthesizer (MF1) 12, the first output of which is connected to the second signal input of the modulator 6, and the second output to the second input of the inverter 14.

The second output of the GPSP 13 is connected to the signal input of the second frequency synthesizer (MF2) 29, the first output of which is connected to the third signal input of the modulator 6, and the second output to the second signal input of the BOES 22.

The output of the clock generator (GTI) 8 is connected to the clock inputs of AI 1, KS 2, packetizer 3, D1 4, M encoders 5 ₁ -5 _M , M1 26, modulator 6, GKP 9, BU 10, AKS1 11, AKS2 28, SCH1 12, SCH2 29, GPSSP 13, BOES 22, BFA 24, demodulator 16, D2 17, M decoders 18 ₁ -18 _K , M2 27, depacketator 19, PI 20, M3 25, as well as K SS 23 ₁ -23 _K .

The device operates as follows. At the transmitting end, from the first input of the device, the signal enters AI 1. From AI 1, data at a speed of C bits / s intended for transmission over a communication channel is sent to KS 2, where the information speed C is converted to the technical speed V Baud. From KS 2, information is fed to the first signal input of the packetizer 3, where it is divided into information blocks with the organization of slots, frames, and data packets based on the control signal coming from the first output of the control unit 10. In this case, the control circuit 9 is based on the control signal coming from the ninth output of the control unit 10, generates bits of the sync sequence and issues them to the second signal input of the packetizer 3 to form synchronization slots in it.

From the output of the packer 3, the information blocks are sent to the signal input D1 4, to the control input of which a signal is supplied from the second output of the control unit 10, based on which the information block in D1 4 is divided into (M + 1) channels. In this case, the signals from the corresponding M outputs of block D1 4 are fed to the signal inputs of the corresponding M encoders 5 ₁ -5 _M , where noise-resistant coding of the information bits of the slot occurs, and the signal from the (M + 1) -th output is fed to the fourth signal input of modulator 6. From the outputs of blocks 5 ₁ -5 _{M, the} encoded information slots are fed to the corresponding signal inputs M1 26, in which, based on the control signal coming from the third output of the control unit 10, M encoded signals are multiplexed into one encoded signal. From the output M1 26, an information packet containing service slots and coded information slots is fed to the first signal input of modulator 6.

GPSSP 13 generates various SRPs for generating modulating frequencies. At the same time, from the first output of the GPSSP 13, the first SRP code is supplied to the signal input of the MF1 2, on the basis of which a transmission frequency is formed in it for modulating the encoded information bits of the information slots, which is fed from the first output of the MF1 2 to the second signal input of modulator 6, and from the second the output of the GPSP 13 to the signal input of the SCH2 29 a second code of the PSP is fed, on the basis of which a transmission frequency is formed in it to modulate the synchronization sequence of the service slots, which from the first output of the SCH2 29 is fed to the third signal input modulator 6. Thus, in block 6 there is a modulation of service and information slots with different frequencies. Moreover, the frequency tuning speed in the modulator 6 is determined based on the control signal coming from the fourth output of the control unit 10. The resulting modulated information block is radiated into space using AFB1 7.

At the receiving end, the input signal, which is a mixture of the useful signal and interference, is received by AFB2 21, where it is divided into service and information components.

The part of the input signal containing the service component from the second output of AFB2 21 is fed to the first signal input of BOES 22. The sequence of random elements of the mixture is converted into BOES 22 into a random sequence of decisions about the symbols corresponding to the received elements of the signal using the reception frequency obtained at the second output SCH 29 on the basis of the second SRP code supplied from the second output of the GPSS 13. This sequence of decisions on symbols in the general case due to the action of interference does not coincide with any of the sequences symbols of the elements that were used in the formation of the sync sequences in GCP 9. In BOES 22, the mixture of the signal element and the noise is optimally processed, and a sequence of decisions is issued on its output about which sync sequence element (logical "0" or logical "1") worked, which is fed to the (K + 1) -th signal input of AKS2 28. In addition, the obtained sequence of decisions about symbols is compared element-wise with the codes of the expected sync sequences in the corresponding SSs 23 ₁ -2 _k .

The comparison results from the outputs of the SS 23 ₁ -23 _K are fed to the corresponding signal inputs of AKS2 28, where the quality of the service component of the signal is analyzed, the result of which is fed to the second input of the control unit 10.

In addition, the signals from the outputs of the SS 23 ₁ -23 _K are fed to the corresponding signal inputs M3 25, in which, based on the signal coming from the tenth output of the control unit 10, they are multiplexed into one signal supplied to the second signal input of the BFA 24.

Another part of the input signal containing the information component is fed to the first input of the inverter 14, in which it is converted to a receiving frequency, the value of which, determined on the basis of the first code of the inverter, is fed to the second input of the inverter 14 from the second output of the MF1 12.

Then the intermediate frequency signal is amplified in the IFA 15 and is supplied to the first signal input of the BFA 24, in which the exact phase adjustment of the information component and the clock sequence based on the service component occurs. The signal from the output of the BPA 24 is fed to the signal input of the demodulator 16, where it is demodulated, and the frequency tuning speed is determined on the basis of the control signal coming from the eighth output of the control unit 10. Moreover, the accuracy of the demodulation is determined by the accuracy of synchronization of clock pulses from the GTI 8 and the signal from the UPCH 15, determined based on a signal from M3 25.

From the output of the demodulator 16, information slots are fed to the signal input D2 17, to the control input of which a signal is supplied from the sixth output of the control unit 10, based on which the demodulated signal in D2 17 is divided into (M + 1) channels. In this case, the signals from the corresponding M outputs D2 17 are fed to the signal inputs of the corresponding M decoders 18 ₁ -18 _M , where the error-correcting code of the slot information bits is decoded.

From the outputs of blocks 18 ₁ -18 _{M, the} decoded information slots are fed to the corresponding signal inputs M2 27, in which, based on the control signal coming from the seventh output of the control unit 10, M decoded signals are multiplexed into one decoded signal, which is output from the output of M2 27 to the first signal input of the depacketator 19, to the second signal input of which a signal is supplied from the (M + 1) -th output of D2 17.

In the depacketator 19, a binary information sequence is combined, which is then fed to the signal input of the PI 20, where it is converted into the output signal form.

In addition, the decoding results determined by the decoders 18 ₁ -18 _M are received respectively at the M signal inputs of AKS1 11, the demodulated information slots from the output of the demodulator 16 are fed to the (M + 1) -th signal input of which is analyzed in the AKS 11 component of the signal, the result of which is fed to the first input of the control unit 10.

BU 10 generates control signals based on information received at its first and second inputs from the corresponding AKS1 11 and AKS2 28.

From the output of the GTI 8 to blocks 1, 2, 3, 4, 5 ₁ -5 _M , 26, 6, 29, 12, 13, 28, 11, 10, 9, 24, 22, 16.17,

18 ₁ -18 _M , 23 ₁ -23 _K , 27, 19, 20 and 25, clock pulses are supplied that determine the beginning of each micro-operation, as a result of which synchronization of the operation of the device as a whole is ensured.

BU 10 can be implemented as a reprogrammable digital device, the algorithm of which is presented in figure 3.

, где V - скорость передачи в радиосредстве, [] - целая часть. В блоке 10.7 первоначально происходит увеличение значения блока 10.3 на единицу.The operation of the control unit 10 begins with the zero state of block 10.3, where the number of information slots is zero (p = 0), and also with the assignment in block 10.1 of the frequency tuning time Tn = const 1, in block 10.2 - the values of the frequency synthesizer desync time Tr = const 2, in block 10.4 - the values of the number of repetitions of synchronization slots d = const 3 and in block 10.5 - the values of the minimum required number of bits in the service frames e = const 4. Based on the value of block 10.1 in block 10.6, the required number of frequency tuning bits is calculated

where V is the transmission speed in the radio, [] is the integer part. In block 10.7, the value of block 10.3 per unit initially increases.

, где q=[х·λ₂] - количества защитных бит информационного слота, и проверка условия х - целое, где λ₂ - коэффициент, зависящий от количества частоты ППРЧ и априорно известных условий распространения сигнала (например, для фиксированной частоты можно принять λ₂≈3%; для ППРЧ из двух частот - λ₂≈6% и т.д.). Если условие не будет выполнено, то из блока 10.10 по линии "нет" происходит переход к блоку 10.7, а если выполнено, то из блока 10.10 по линии "да" в блок 10.15 вводятся значения х, у и р, а в блоки 10.24.1-10.24.М значения х и р, где рассчитывается число кодовых слов в информационном фрейме

,

, …,

, соответственно (n₁, n₂, …, n_M - длины тех М помехоустойчивых кодов, которые используются в данном радиосредстве).Based on the values of blocks 10.6, 10.2, and 10.7 in block 10.10, the value of the number of information bits of the slot is calculated

, where q = [x · λ ₂ ] is the number of protective bits of the information slot, and checking condition x is an integer, where λ ₂ is a coefficient depending on the amount of frequency hopping frequency and a priori known propagation conditions of the signal (for example, for a fixed frequency, we can take λ ₂ ≈3%; for frequency hopping of two frequencies - λ ₂ ≈6%, etc.). If the condition is not met, then from block 10.10 on the line "no" goes to block 10.7, and if it is met, then from block 10.10 on the line "yes" in block 10.15 the values x, y and p are entered, and in blocks 10.24. 1-10.24.M values of x and p, where the number of codewords in the information frame is calculated

,

, ...,

, respectively (n ₁ , n ₂ , ..., n _M are the lengths of those M error-correcting codes that are used in this radio).

From block 28 to blocks 10.9.1-10.9K, the error probability value per bit in the synchronization channel is received to determine the probabilities of the correct reception of P _pr and false alarm R _lt . In these blocks, the average risks R _j (j = 1 ... K) are calculated according to the formula R = a · R _{cash signal.} + (1-P _pr) + b · P _ots.sign. · (1-P _lt ), where P _ot.sign. - a priori probability of the absence of a signal; R _{cash signal} - a priori probability of the presence of a signal; a and b are weight coefficients depending on how dangerous P _Lt is compared to 1-P _etc. The blocks obtained in blocks 10.9.1-10.9 _. The average risk values R ₁ -R _K go to block 10.8, where the minimum their value is min, which goes to blocks 10.11.1-10.11.K, where in sequence, starting from block 10.9.1, the conditions are checked:

- if the condition min = R ₁ is fulfilled, then on the yes line in block 10.12.1, the value of the sync sequence length L = L _{1 is} assigned, if it is not satisfied, the condition min = R ₂ is checked on the no line in the next block 10.11. 2;

- if the condition min = R ₂ is fulfilled, then on the line “yes” in block 10.12.2, the value of the sync sequence length L = L _{2 is} assigned; if it is not satisfied, on the line “no” the condition min = R ₃ is checked in the next block 10.11. 3 etc.

The value of that of blocks 10.12.1-10.12.K, where the assignment occurred, is loaded into blocks 9, 25 and into block 10.13, where the number of protective bits of the service slot is calculated z = [L · λ ₁ ], where [] is the integer part , and λ ₁ is a coefficient depending on the number of frequency hopping frequencies and a priori known propagation conditions of the signal, similar to that described above.

The values of blocks 10.4 and 10.13 are entered into block 10.15, where the number of bits in the frame is calculated Ψ = (y + L + z) · d + (y + x + q) · p. The values of y, L, x, z, d, Ψ and p are recorded in block 10.17 and loaded into blocks 3 and 19.

и проверка условия Т - целое, где С - необходимая скорость передачи информации. Если условие выполняется, по линии "да" в блок 10.21 записываются величины Т и g, которые затем загружаются в блоки 3 и 19. Если условие не выполнено, по линии "нет" происходит переход к блоку 10.18. Кроме того, значения Т и g из блока 10.21 загружаются в блок 10.22, где рассчитывается скорость ППРЧ

, которая выдается в блоки 6 и 16.The ψ value obtained in block 10.15 and the value of block 10.18 are loaded into block 10.20, where the value of the packet transmission time is calculated

and checking the condition T is a whole, where C is the necessary information transfer rate. If the condition is met, the T and g values are written to the block 10.21 along the yes line, which are then loaded into blocks 3 and 19. If the condition is not met, the no line goes to block 10.18. In addition, the values of T and g from block 10.21 are loaded into block 10.22, where the frequency hopping rate is calculated

, which is issued in blocks 6 and 16.

, [] - целая часть, а если выполнено - то из блока 10.14 по линии "да" в блоке 10.16 происходит присвоение g=0. Значение того из блоков 10.16 или 10.19, где произошло присвоение, загружается в блок 10.18, где увеличивается на единицу.From block 10.15, the value of Ψ, in addition, is loaded into block 10.14, where the condition e≤Ψ is checked. If the condition is not met, then from block 10.14 along the line "no" there is a transition to block 10.19, where the assignment

, [] is the integer part, and if done, then assignment g = 0 from block 10.14 along the yes line in block 10.16. The value of that of blocks 10.16 or 10.19, where the assignment occurred, is loaded into block 10.18, where it is increased by one.

From block 11 to blocks 10.23.0–10.23.M, the error probability per bit in the information channel is received to determine the probabilities of the correct reception of W, W ₁ -W _M code words of those M error-correcting codes that are used in this radio (W is calculated for the case when the error-correcting code is not used). The values of W ₁ -W _M obtained in blocks 10.23.1-10.23.M are received respectively in blocks 10.25.1-10.25.M.

The value of block 10.23.0 also arrives at each of blocks 10.25.1-10.25.M, where the conditions are checked sequentially, starting from block 10.25.1:

- if the condition W ₁ > W is fulfilled, then on the line “yes” in block 10.26.1 the comparison of Ω ₁ with an integer is performed, if it is not fulfilled, on the line “no” the condition W ₂ > W is checked in the next block 10.25.2 ;

- if the condition W ₂ > W is fulfilled, then on the line “yes” in block 10.26.2 the comparison of Ω ₂ with an integer is performed, if it is not fulfilled, on the line “no” the condition W ₃ > W is checked in the next block 10.25.3 ;

...

- if the condition W _M > W is fulfilled, then on the line “yes” in block 10.26. М a comparison is made of Ω _M with an integer, if it is not fulfilled, on the line “no” in block 10.27.0, assignment i = 0.

The values of Ω ₁ , Ω ₂ , ..., Ω ₃ calculated in blocks 10.24.1-10.24.M go respectively to blocks 10.26.1-10.26.M, where the conditions are checked sequentially, starting from block 10.26.1:

- if the condition is satisfied that Ω ₁ is an integer, then the assignment i = 1 occurs on the yes line in block 10.27.1, if the condition is not fulfilled, the condition W ₂ > W in block 10.25.2 is checked on the no line ;

- if the condition is satisfied that Ω ₂ is an integer, then the assignment i = 2 occurs on the yes line in block 10.27.2, if the condition is not fulfilled, the condition W ₃ > W in block 10.25.3 is checked on the no line ;

- if the condition is satisfied that Ω _M is an integer, then on the line "yes" in block 10.27. М is assigned i = M, if it is not fulfilled, on the line "no" the value of block 10.7 increases by one.

The value of that of blocks 10.27.0-10.27.M, where the assignment occurred, is loaded into blocks 4, 17, 26 and 27.

AKS1 11 and AKS2 28 can be implemented, for example, as BER testers [5, chapter 8]. BPA 24 can be implemented in the form of schemes for linking the clock signal to the bit intervals of the received data [5, Chapter 9]. BOES 22 can be implemented as a decisive device [4, Chapter 7.4]. SS 23 ₁ -23 _K can be implemented in the form of discrete matched filters [4, chapter 7.4-7.5].

Modulator 6 and demodulator 16 can be implemented as processors of the Motorola DSP56800 family [7, pp. 1-11, chapter 5].

The implementation of other blocks of the proposed device can be carried out using digital devices known from the technical literature.

As an example of the functioning of the proposed device, suppose that through a radio station having a technical speed of V = 19.2 kBaud, data is transmitted from the data transmission equipment at a speed of C = 12 kbit / s. An example of a time chart of the generated information packet consisting of frames and slots satisfying this case is shown in Fig. 4, from which it follows that the number of information bits in the block is x = 45 and the hopping rate is γ = 300 jump / sec. Three binary M-sequences with L ₁ = 31, L ₂ = 63 and L ₃ = 127 are used as sync sequences, and a discrete matched filter (DSF) is used as a device for their determination at reception [4, p. 275]. It is assumed that the used DSF detects the synchronized sequence in real time [4, pp. 279-282] by uniformly gating each conditional bit not at one but at u = 8 points, which uses signal information more fully: if at least 3 matches in a row of sequences (from the obtained u = 8) with a copy of the signal (with a tolerance of up to u ₀ errors for each sequence), a decision is made to receive the clock signal. The appearance of each of the M-sequences is set by arranging the sequence of trigger cells in the DSF [4, p. 279].

The average risks R _j , where j∈ {1, ..., K}, are calculated by the formula:

where R _s.sign - the a priori probability of the absence of a signal;

P _nal.sign - the a priori probability of the presence of a signal;

a and b are weights, depending on how dangerous P _lt is compared with 1-Ppr.

If in formula (1) we take P _sig.sign = 0.8, P _cash.sign = 0.2 and the ratio a / b = 0.01, then with the probability of error per bit p∈ {0.15, ..., 0.45}, determined by the signal quality analyzer, formula (1) you can calculate the average risks R ₁ , R ₂ , R ₃ .

Figure 5 presents the average risks when taking M-sequences of various lengths. By analyzing FIG. 5, it can be determined that the M-sequence whose schedule lies “below” the others is used as the synchronization for the next packet.

After determining the type of the clock signal, the following problem is solved: determining the need for the use of an error-correcting code under the influence of delayed interference. For this, the error probabilities per bit are calculated: 1

Where

Where:

- мощность сигнала;

- signal power;

- спектральная плотность мощности белого шума;

- spectral power density of white noise;

- спектральная плотность мощности запаздывающей помехи.

- spectral power density of delayed interference.

Figure 6 presents a timing diagram of the information bits of the slot when exposed to delayed interference. For a given timeline:

x _n = [x · θ] is the number of uninfected information bits in the slot;

x _n = x-x _n - the number of affected information bits in the slot; T

- коэффициент запаздывания помехи;Where:

- delay coefficient of interference;

T _SL - time of delayed interference;

T _s - the delay time of the interference.

Finally, the average probability of error per bit is determined by:

If the conditions of signal propagation require a higher guarantee from the user to bring information to the recipient, the timing diagram allows you to "sacrifice" the speed of information transfer to increase the quality of the latter. An example of a timing diagram satisfying this case is shown in FIG. In the case of using majority processing as a noise-resistant code (selection rule 3 of 5), the time diagram takes the form shown in Fig. 7, and the average probability of error per bit, according to [6], is determined:

where ξ is the summation index.

Since in case of using a majority the information rate will decrease from C = 12 ^kbit / _s to β = 2.4 ^kbit / _s , the number of bits of information in the slot will be 396. Therefore, it is possible to calculate the coefficient of improvement in the quality of bit transmission as a ratio of the probability of correct reception of 396 bits of information after and before applying the major

while the coefficient of use of the speed of information is

The dependence of _μqu on τ for the values of the delay coefficient θ = 0.8 and θ = 0.2 are shown, respectively, in Fig. 8 and Fig. 9. Thus, provided that the user selects a criterion for changing speeds

(that is, the user “sacrifices” the transmission rate only if the decrease in the speed by a factor of µ will lead to an improvement in the transmission quality by more than 2µ times) the quality of the information signal is analyzed, which determines the values of τ, θ and φ, from which the values of µ _ck and μ _kach , which are compared according to criterion (10) and the decision is made based on the result of the comparison: whether to change the transmission speed of information or not (that is, whether to apply the noise-immunity protection method or not).

In this case, when θ = 0.8, the majority is applied at τ> 1.7, and at θ = 0.2 - at τ> 4.8.

Figure 10 shows the dependence of µ _Kach on τ and θ for various cases: 1) with φ = 5; 2) at φ = 20,000; 3) the boundaries of the criterion. If as a result of the analysis of the signal quality it is determined that the operating point lies on any of the planes (1 or 2) above plane 3, majority processing is applied.

Thus, the introduction of new blocks and communications in the proposed device allows to increase the reliability of information reception by adapting the clock signal to a change in the noise environment, which allows it to be used in special communications under the influence of intentional interference.

Information sources

1. RF patent for the invention No. 2185029 "Radio line with pseudo-random tuning of the operating frequency", Odoevsky S. M., Eryshov V. G., 2001.

2. RF application for invention No. 2001102653 "Method and device for pseudo-random tuning of the operating frequency", Postnikov VA, Shubenkin VV, 2001.

3. RF patent for the invention No. 2097923 "A method for transmitting discrete information in a radio line with pseudo-random tuning of operating frequencies and its device realizing", Bulychev O.A .; Ignatov V.V .; Schukin A.N. 1997.

4. Noise-like signals in information transmission systems. Ed. prof. V. B. Pestryakova. M., "Sov. Radio", 1973.

5. S.N. Sukhman, A.V. Bernov, B.V. Shevkoplyas. Synchronization in telecommunication systems. Analysis of engineering solutions. - M .: Eco-Trends, 2003.

6. Feer. K. Wireless digital communications. Methods of modulation and spreading: Per. from English / Ed. V.I. Zhuravleva. - M., Radio and Communications, 2000.

7. Technical support for digital signal processing. Directory. Kupriyanov M.S., Matyushkin B.D., Ivanova V.E., Matvienko N.I., Usov D.Yu. - St. Petersburg., "Fort", 2000.

Claims (1)

An adaptive data transmission device with pseudo-random tuning of the operating frequency, comprising an information source whose input is the first input of the device, an information receiver whose output is the second output of the device, a modulator and a first antenna-feeder unit connected in series, the output of which is the first output of the device; a pseudo-random sequence generator and a first frequency synthesizer connected to a second signal input of the modulator in series; a clock generator, a second frequency synthesizer, a demodulator, a second antenna-feeder unit connected in series, the input of which is the second input of the device, a frequency converter and an intermediate frequency amplifier, characterized in that a speed switch, a packetizer, a depacketator, a code sequence generator, a control unit are introduced , signal element identification unit, phase-locked loop unit, first and second signal quality analyzers, first and second demultiplexers, first, second and third multiplexers, M encoders, M decoders and K comparison circuits; in addition, in the information source, modulator, demodulator, pseudo-random sequence generator, first and second frequency synthesizers, it is additionally inputted at the clock input, and in the modulator and demodulator it is additionally inputted at the control input; wherein the input of the information source through the speed switch is connected to the first signal input of the packetizer, the output of which is connected to the signal input of the first demultiplexer, the M outputs of which are connected to the signal inputs of the corresponding M encoders, the outputs of which are connected respectively to the M signal inputs of the first multiplexer, the output of which is connected to the first signal input of the modulator; the demodulator output is connected to the signal input of the second demultiplexer, the M outputs of which are connected to the signal inputs of the corresponding M decoders, the outputs of which are connected respectively to the M signal inputs of the second multiplexer, the output of which is connected to the first signal input of the depacketator, the second signal input of which is connected to (M + 1 ) -th output of the second demultiplexer, and the output of the depacketator is connected to the signal input of the information receiver; also the outputs of the M decoders are connected respectively to the M signal inputs of the first signal quality analyzer, the (M + 1) -th signal input of which is connected to the output of the demodulator; the output of the intermediate frequency amplifier is connected to the first signal input of the phase-locked loop, the output of which is connected to the signal input of the demodulator; the second antenna-feeder unit is configured to separate the signal into service and information components and it additionally introduces a second output connected to the first signal input of the signal element identification unit, the output of which is connected to the signal inputs K of the comparison circuits, the outputs of which are connected respectively to the K signal the inputs of the third multiplexer, the output of which is connected to the second signal input of the phase-locked loop; in addition, the outputs K of the comparison circuits are connected to the K signal inputs of the second signal quality analyzer, the (K + 1) -th signal input of which is connected to the output of the signal element identification unit; the first to tenth outputs of the control unit are connected respectively to the control inputs of the packetizer, first demultiplexer, first multiplexer, modulator, depacketator, second demultiplexer, second multiplexer, demodulator, code sequence generator and third multiplexer, and the output of the code sequence generator is connected to the second signal input of the packetizer ; the outputs of the first and second signal quality analyzers are connected respectively to the first and second inputs of the control unit; the second output of the pseudo-random sequence generator is connected to the signal input of the second frequency synthesizer, the first output of which is connected to an additional third signal input of the modulator, the (M + 1) -th output of the first demultiplexer is connected to an additional fourth signal input of the modulator, and the first frequency synthesizer is additionally introduced the second output connected to the second input of the frequency converter, in the second frequency synthesizer, an additional second output connected to the second signal is introduced th input signal element identification unit; the output of the clock generator is connected to the clock inputs of the information source, speed switch, packetizer, first and second demultiplexers, first, second and third multiplexers, modulator, code sequence generator, control unit, phase locked loop, first and second signal quality analyzers, first and second frequency synthesizers, pseudo-random sequence generator, signal element identification unit, demodulator, depacketator, information receiver, M encoder a, K and M decoders comparison circuits.

Images