RU2356165C1 - Device for transmission of digital information - Google Patents

Abstract

FIELD: physics, communication.

SUBSTANCE: invention is related to devices for transmission of data and may find application in telecommunication systems, systems of radio communication, radio navigation and control. Device comprises unit of data transfer that consists of parallel code transformer into serial one, transducer of binary code in code with three conditions, modulator, transmitter of data and clock pulse generator and unit of data reception comprising data receiver, demodulator, shaper of triple code, unit of clock signal separation, unit of errors correction, unit of erasure duration control, transducer of triple code into binary one and transducer of serial code into parallel one.

EFFECT: increased throughput capacity and noise immunity of communication line.

12 dwg, 3 tbl

Description

The invention relates to data transmission devices and may find application in telecommunication systems, radio communication systems, radio navigation and control, operating in an unfavorable interference environment.

Data transmission systems are known, for example, according to the patents of the Russian Federation 2249914, Н04В 7/00, 2003, 2258313, Н04К 3/00, H04L 27/26, 2004, in which the implementation of the transmission and reception of multi-frequency signals is proposed.

The main disadvantage of these systems is the use of a clock pulse generator on the receiving side, which should be adjusted in the process of receiving information, and this is, firstly, an inertial process, and secondly, it is implemented using a rather complex phase-locked loop.

Closest to the technical nature of the proposed device is a data transmission device described in RF patent 2242789, G06F 13/14, publ. December 20, 2004], taken as a prototype.

Figure 1 shows a block diagram of a prototype device, where indicated:

1 - two-channel parallel-to-serial code converter (PPP);

2 - clock generator;

9 - block forming a clock;

13 - two-channel serial to parallel converter (PPR);

14 - data transmission unit (BPRD);

15 - communication channel;

16 - data receiving unit (BPRM);

17-20 - from the first to the fourth amplifiers;

21, 22 - the first and second adjustable delay elements;

23, 24 - the first and second computers.

The prototype device contains a data transmission unit 14 and a data reception unit 16 connected by a communication channel 15.

The data transmission unit 14 contains a clock pulse generator 2, the output of which is connected to the synchronization input of the BPS 1, the two data outputs of the first and second channels of which are connected respectively to the inputs of the first 17 and second 18 amplifiers, the outputs of which are the outputs of the BPRD 14. In this case, the readiness output of the BPS 1 is connected to the input port of the first computer 23, the output port of which is connected to the group of data inputs PPP 1.

The data receiving unit 16 contains a third 19 and a fourth 20 amplifiers, the outputs of which are connected to the inputs of the first 21 and second 22 adjustable delay elements, respectively, the outputs of which are connected to the corresponding inputs of the clock shaping unit 9 and the corresponding data inputs of the first and second channels Pdr 13, group of outputs the data of which is connected to the first input port of the second computer 24, the second input port of which is connected to the readiness output PPr 13. In addition, the group of control inputs of the first 21 and second 22 adjustable delay elements are connected respectively to the first and second output ports of the second computer 24. In this case, the output of the clock generating unit 9 is connected to the input of the SPR 13. The inputs of the first 19 and second 20 amplifiers are inputs of the BPRM 16.

The prototype device operates as follows. Computer 23 stores data that must be transmitted to computer 24. These data can be generated, for example, by polling sensors or obtained through communication channels (sensors and communication channels are not shown in FIG. 1), etc. The data of the main channel is scrambled and byte-wise transmitted through the output port of computer 23 to PPP 1. Each byte is transmitted before the readout of the ready signal arrives at the input port of computer 23. The next byte is issued by computer 23 to the output port only when it detects the next ready signal in its input port. All processes that occur during data transfer are synchronized by signals from a clock generator 2. This generator generates a continuous sequence of clock pulses with a duty cycle of two. The clock period is equal to the length of the bit interval.

PPP 1 on the positive edge of the clock receives a byte of data and generates at its outputs two sequences of bits - the primary and secondary, which are transmitted through amplifiers 17 and 18 via communication channel 15.

The attenuated signals transmitted through the communication channel 15 are amplified in the amplifiers 19 and 20. The difference in the delay of the signals from the outputs of the amplifiers 19 and 20 is compensated by adjustable delay elements 21 and 22. The time-aligned signals are fed to the corresponding inputs of the clock generation unit 9 and simultaneously fed to the corresponding SPR inputs 13. From the output of block 9, the sync signal is supplied to the corresponding input of the pass-through 13. On the positive edge of the clock signal, the pass-through 13 from parallel data streams forms parallel data streams. The readiness signal of the newly formed byte of the parallel code arriving at the second port of computer 24. From the data output group Ppr 13, the data is read through the first port by computer 24. The received data is stored in the memory of the computer 24 and analyzed. The boundaries of information frames are determined, synchronization bits are removed from the data stream, data received from communication channel 15 are descrambled, and the correctness of the received frames is checked using redundant cyclic codes. A program is performed to search for a health area by decoding information on the position of the boundaries between frames transmitted on both lines of communication channel 15, which allows computer 24 to restore the original structure of data received from the data channel. Then, the computer 24 carries out the process of adapting the prototype device to the delay difference, which accompanies data transfer along the lines of communication channel 15. Several series of experiments are carried out with different delays, and in each experiment, the correctness of data reception on both lines is checked. Moreover, if the parameters of the communication channel 15 periodically change, the adaptation of the prototype device to such changes will be carried out quite often in order to track such changes in time.

The disadvantages of the prototype device are as follows:

- the availability of schemes for scrambling and descrambling data to convert blocks of units and zeros of a binary sequence into blocks with a random combination of zeros and ones, which complicates the implementation of transmitting and receiving devices;

- the presence of two lines of the communication channel, one of which is designed to transmit most of the data, the second - to transmit synchronizing information and the rest of the data, the transmission of which on the second line is possible, due to scrambling due to the non-identity of the lines in terms of propagation time, it requires determining the difference in propagation delay signals along these lines;

- the presence of the block forming the clock signal in the form of a generator with an inertial PLL system;

- the mandatory presence of two computers, which, in addition to other standard operations, implement the adaptation algorithm of the prototype device to the difference in the propagation delay of the signals along two lines of the communication channel.

To eliminate these shortcomings, a device for transmitting digital information, consisting of a data transmission unit (BPRD) and a data receiving unit (BPRM) connected by a communication line, the BPRD contains a parallel to serial converter (PPP), the synchronization input of which is connected to the generator output clock pulses (GTI), BPRM contains serially connected block allocation of the clock signal (BVS) and the converter serial code to parallel (PPR), according to the invention are entered: in BPRD - serial o connected converter of binary code to three-state code (PDT), a modulator and a data transmitter (PRD), the output of which is the output of the BPRD, the synchronization input of the PDT is connected to the output of the GTI, N inputs of the BPS are inputs of the BPRD; in BPRM - a series-connected data receiver (PFP) and a demodulator, the outputs of which are connected to the corresponding inputs of the ternary code generator (FTK), the outputs of which are connected to the corresponding inputs of the BVS, error correction block (BKO) and erase duration control unit (BCD), when this first and second outputs BKO are connected respectively to the first and second inputs of the ternary code to binary converter (PDD), the output of which is connected to the second input of the SPR, N outputs of which are outputs BPRD, and the output of the BCD is connected with the fifth input of the BKO, the third output of which is connected to the fourth input of the BVS, the first output of which is connected to the first input of the control device and the fourth input of the BKO, the sixth input of which is connected to the second output of the BVS.

A block diagram of the proposed device is presented in figure 2, where it is indicated:

1 - parallel-to-serial code converter (PPP);

2 - clock generator (GTI);

3 - a binary code to three state code converter (PDT);

4 - modulator;

5 - data transmitter (PRD);

6 - data receiver (PFP);

7 - demodulator;

8 - shaper ternary code (FTK);

9 - block allocation clock (BVS);

10 - block error correction (BKO);

11 - block control the duration of the erasure (BKD);

12 - converter of ternary code to binary (PDD);

13 - serial to parallel converter (PPR);

14 - data transmission unit (BPRD);

15 - communication line (LS);

16 - data reception unit (BPRM).

The proposed device contains BPRD 14 and BPRM 16 connected by a communication line 15.

BPRD 14 contains series-connected PPP 1, PDT 3, modulator 4 and PRD 5, the output of which is the output of BPD 14. At the same time, the output of the GTI 2 is connected to the synchronization inputs of PPP 1 and PDT 3, the other two outputs of which are connected to the corresponding inputs of modulator 4. N inputs PPc 1 are inputs BAPD 14.

BPRM 16 contains series-connected PFP 6 and a demodulator 7, three outputs of which are connected to the corresponding inputs of the ternary code generator 8, three outputs of which are connected to the corresponding inputs of the BKO 10, two outputs of which are connected to the corresponding inputs of the PDD 12, the output of which is connected to the second input 13, the N outputs of which are the outputs of the BPRM 16. In addition, the outputs of the FTK 8 are connected to the corresponding inputs of the BVS 9 and the BKD 11, the output of which is connected to the fifth input of the BKO 10, the third output of which is connected to the fourth input UA 9, a first output connected to the first input 13 and DRX BKO fourth input 10, a sixth input which is connected to the second output UA 9.

The proposed device operates as follows.

Data from various sources simultaneously arrives at the corresponding inputs of the PPS 1 block, clock pulses from the output of the GTI block 2 are received at its synchronizing input. The PPS 1 block, in accordance with the clock pulses, forms a sequence of binary data (bits), which from its output goes to the input of the block PDT 3, to the synchronizing input of which clock pulses are received from the output of the GTI block 2. In the PDT 3 block, logical operations are performed on the incoming binary symbols at each clock cycle, the result of which is following. If the binary symbol is in an odd position in the block of zeros or ones, then a pulse will appear at the first output of the PDT 3, and at the second and third outputs of the PDT 3 there will be zero values at the same time. That is, at this measure, a ternary code symbol will be formed (a column whose upper element corresponding to the first output of the PDT 3 block is nonzero, and the other two elements are zero) that carries information about this position of the binary symbol in the unit block. For a block of zeros in this case, the ternary code symbol (a column whose lower element corresponding to the third output of the block of PDT 3 is nonzero and the other two are zero) is formed at the output of the PDT block 3, which carries information about this position of the binary symbol in the block of zeros. If the binary symbol occupies an even position in the block of zeros or ones, then the third symbol of the ternary code is formed (a column whose middle element corresponding to the second output of the ПДТ 3 block is nonzero, and the other two elements are zero), which carries information about the corresponding position of the binary symbol in block of zeros or block of units. Moreover, in the stream of symbols of the ternary code there are no adjacent symbols with the same state (two identical adjacent columns). Then, at each clock cycle, the symbols of the ternary code from the outputs of the PDT block 3 are supplied to the corresponding inputs of block 4, where the carrier frequency is modulated by parameters whose values are selected in accordance with the symbol of the ternary code. The modulation can be frequency, phase, code (for example, Barker codes), that is, each symbol of the ternary code is modulated either by its frequency or its phase, etc. From the output of block 4, the modulated signal is fed to the input of the PRD 5 block, from the output of which it is radiated to the LAN 15.

In the data receiving unit 16, useful modulated signals from the output of the BPRD 14 through the LAN 15 are fed to the input of the PFP 6, the output of which is fed to the input of the unit 7, where the distorted ternary code symbols delivered by the signals that are output from the outputs of the unit 7 to the corresponding inputs of the FTK 8 block, where they are corrected. From the outputs of the FTK 8 block, they arrive at the corresponding inputs of the BKO 10, BVS 9, and BKD 11 blocks. In this case, the forming stream of ternary code symbols should not have identical adjacent symbols. In the BKD block 11, the redundancy introduced in this way is used to control the erasure duration, and if the erase duration is more than 1.5 · τ (τ is the duration of the binary information symbol), then a short pulse will arrive from the output of the BKD block 11 to the fifth input of the BKO block 10 reset the device to its original state. If the erasure time is not more than 1.5 · τ, then the erased (suppressed) symbol of the ternary code (zero column) is supplied to the corresponding inputs of the BKO unit 10. At the same time, in the BVS unit 9, clock pulses are selected from the incoming ternary code symbols, which its output goes to the fourth input of the block BKO 10 and the first input of the block PPr 13, coordinating the operation of blocks BKO 10, Ppr 13 and PDD 12. In the block BKO 10, using the fact that there cannot be two identical adjacent symbols of the ternary code, on each a tact isolates a triad of such symbols (mat Ritsa) and logical operations on the elements of the columns of the triad adjust the middle erased character (column) in the triad. Next, the first and third elements of the symbols of the ternary code (column elements) from the outputs of the block BKO 10 go to the corresponding inputs of the block PDD 12, where the logical operations on them restore the stream of received binary symbols. This stream of binary symbols arrives at the second input of the PPR 13 block, where under the control of clock pulses coming from the first output of the BVS block 9, the initial parallel data is generated. If in the BVS block 9 more than one clock pulse is lost or the first or last characters of the ternary code symbol sequence are erased, then from its second output to the sixth input of the BKO block 10, a short pulse will be sent to reset the device to its original state. If the error cannot be corrected in block БСО 10, then this block generates a short pulse to reset the device to its original state.

The implementation of the blocks of the proposed device is not difficult, since the circuit solutions are well known. Blocks PPS 1, GTI 2 and PPR 13 correspond to similar blocks of the prototype. The difference between block 13 in the prototype is that it is two-channel.

A generalized block diagram of an m-position modulator of orthogonal signals (block 4) can be performed, for example, as presented in [B. Sklyar. Digital communication. Moscow, St. Petersburg, Kiev, 2003, pp. 339-341, Fig. 6.4]. The block diagram and description of the operation of the multiphase modulator are given in the same place on pages 223-234, Fig. 4.23. The amplitude-phase modulator (QAM) diagram is shown on pages 585-586, Fig. 9.16. In particular, the three-frequency modulator is a self-oscillator (for example, [Yu.I. Sudakov. Amplitude modulation and self-modulation of transistor generators. M: Energy, 1969, p. 32, Fig. 1-20 (b)]), to the circuit of which with the help of keys, capacities of various sizes are connected. The keys are controlled by the elements of ternary symbols coming from the corresponding outputs of the PDT 6 unit to their control inputs.

Blocks PRD 5 and PRM 6 are easily implemented by radio modules [V. Kuchenko. Miniature radio modules for transmitting digital information. Radio amateur, 11/96, p. 39, fig. 1, fig. 2].

The block diagram of the block PDT 3 is presented in figure 3, where indicated:

3.1. 3.4 - the first and second blocks of summation modulo 2 (mod2);

3.2, 3.3 - the first and second blocks of dynamic memory (DP);

3.5-3.7 - the first second and third blocks of inversion (NOT);

3.8 - block I.

Block ПДТ 3 contains serially connected the first block mod2 3.1 and the second block NOT 3.6, the output of which is connected to the first input of block And 3.8, while the output of block mod2 3.1 is connected to the first input of the first block of DP 3.2, the output of which is connected to the second input of block mod2 3.1 , the first input of which is the input of PDT 3 and connected to the input of the first block NOT 3.5, the output of which is connected to the first input of the second block mod2 3.4, the output of which is connected to the first input of the second block DP 3.3 and the input of the third block NOT 3.7, the output of which is connected to the second block input AND 3.8. The second inputs of the first DP 3.2 and the second DP 3.3 blocks are connected and are the synchronizing input of the PDT 3 block, and the output of the second PD 3.3 block is connected to the second input of the second block mod2 3.4.

The output of the first block mod2 3.1 is the output of the first element of the ternary code symbol, the output of the third block And is the output of the second element of the ternary code symbol, the output of the second block mod2 3.4 is the output of the third element of the ternary code symbol.

Block PDT 3 works as follows.

In the initial state, the value zero is stored in the first and second blocks of DP 3.2 and 3.3.

At the synchronizing input of the PDT 3 unit, a stream of binary symbols in the form of units of units and zeros of various lengths is received, clock pulses are received at the input of the PDT 3 block, while the binary characters are simultaneously fed to the first input of the first block mod2 3.1 and to the input of the first block NOT 3.5, clock pulses simultaneously arriving at the second inputs of the first 3.2 and second 3.3 DP blocks determine the moments of arrival from the outputs of the first 3.2 and second 3.3 DP blocks to the second inputs of the first 3.1 and second 3.4 blocks mod2 of the values stored there. When a binary unit arrives at the input of the PDT block 3, the binary inputs and binary zero respectively arrive at the first inputs of mod2 31. and 3.4, while binary zeros arrive at their second inputs. In this case, the binary unit will be output from the output of the first block of mod2 3.1, binary zero will be output from the output of the second mod2 3.4 block, binary zero and binary one will be received respectively at the first and second inputs of the And 3.8 block and the inputs of the first 3.2 and second 3.3 DP blocks, which means from the output of the AND 3.8 block, binary zero will come out. Thus, zeros will appear at the second and third outputs of the PDT block 3, and one at the first output. This means that the second and third inputs of block 4 (Fig. 2) will be “locked”, and the first input will be “open”, which means that the ternary code symbol (column) will arrive at the inputs of block 4, carrying information that the current binary symbol takes an odd position in the unit block. If the binary one again arrives at the second input of the PDT block 3, then since on this clock in the first block of DP 3.2 the unit is stored instead of zero, which at that moment will go to the second input of the first block of mod2 3.1, it will no longer be output from its output, but zero, while the output of the second block of mod2 3.4 will still produce zero. At the same time, from the outputs of the second 3.6 and third 3.7 blocks NOT to the corresponding inputs of the AND 3.8 block, units will arrive, which means that at its output we get one. Therefore, zeros will appear on the first and third outputs of the PDT block 3, and one will appear on the second output. This means that the first and third inputs of block 4 (Fig. 2) will be “locked”, and the second input will be “open” and a ternary code symbol (column) will arrive at its input, carrying information that the current binary character is in an even position in a unit block, that is, information about the repetition of a binary character in a unit block.

Similarly, the PDT block 3 also works when a block of binary zeros or alternating zeros and ones arrives at its input.

Schematic diagram and operation of blocks mod2 3.1, mod2 3.4 are given in [Microcircuits and their application. Vol. 1070. M .: Radio and communications, 1980, pp. 127-128, fig. 4.23 (a)], as well as in [M. Mandl. 200 selected electronics circuits. / Per. from English under the editorship of J.S. Yitzhoki. M.: Mir, 1980, pp. 183-184, fig. 8.8 (a)]. Implementation options for blocks DP 6.2, DP 6.3 are given, for example, in [F. Meidza. Integrated circuits. Technology and application. M.: Mir, 1981, pp. 129-131, Fig.5.7], [O.N. Lebedev. The use of memory chips in electronic devices. M .: Radio and communications, 1999, pp. 98-104]. Schemes and operation of logical blocks NOT 6.5-NOT 6.7 and 6.8 are presented in [M. Mandl. 200 selected electronics circuits. / Per. from English under the editorship of J.S. Yitzhoki. M .: Mir, 1980, pp. 176-181, fig. 8.3 (b), 8.6 (b)].

The general structural schemes of multi-position demodulators of coherent and incoherent signals (options for constructing a demodulator 7) are given in [A.G. Zyuko, Yu.F. Korobov. Theory of signal transmission. M .: Communication, 1972, pp. 136-140, Fig. 5.8, Fig. 5.9]. A particular embodiment of the m-phase demodulator was developed in [VB Steshenko et al. Maximum likelihood demodulator using intersymbol phase coupling and Viterbi decoder. Digital Signal Processing, No. 1, 2005, pp. 19-25].

The block diagram of the block BKD 11 is presented in figure 4, where indicated:

11.1 - block logical summation (OR);

11.2, 11.5 - the first and second blocks of logical negation (NOT);

11.3, 11.6 - the first and second blocks of differentiation (DB);

11.4 - one-shot (OB);

11.7 - logical multiplication block (I).

Block BKD 11 contains a series-connected block OR 11.1, the first block NOT 11.2, the first block DB 11.3, block OB 11.4, the second block NOT 11.5, the second block DB 11.6 and block 11.7, the output of which is the output of the BCD 11. The output of the first block NOT 11.2 is connected to the second input of the AND block 11.7. Three inputs of the OR block 11.1 are the corresponding inputs of the BKD 11.

Block BKD 11 works as follows.

At each cycle, the inputs of the OR block 11.1 from the corresponding outputs of the FTK 8 block (Fig. 2) receive ternary code symbols (columns) characterizing the position of binary symbols in units of ones and zeros of the original binary sequence. If the symbols of the ternary code are not erroneous, then one of the elements will always be one in the columns, which means that there will be a logical zero at the input of the first DB block 11.3 and at the second input of the AND 11.7 block. In this case, regardless of what arrives at the first input of the And 11.7 block, during these clock cycles there will be a logical zero at its output, which will block the reset of the device to its original state.

If there are erroneous symbols of the ternary code in the corresponding columns, all elements will be zero, which means that the logical unit will go to the second input of the And 11.7 block and to the input of the first DB 11.3 block. At the same time, the pulse from the output of the first DB 11.3 block will be triggered by the single-shot OB 11.4, the output of which will output a pulse of 1.5 · τ duration. In this case, an inverted pulse with a duration of 1.5 · τ (i.e., a logical zero of the same duration) will arrive at the input of the second DB 11.6 block. Therefore, at the end of the zero pulse from the output of the second DB unit 11.6, a short pulse will arrive at the first input of the And 11.7 block. If only one ternary symbol is erroneous, that is, the duration of zero at the input of the second DB 11.6 block is no more than 1.5 · τ, then at the moment of the arrival of a short pulse from the output of the second DB 11.6 block to the first input of the 11.7 block, the output unit is one the first block NOT 11.2 will already give way to zero and a logical zero will exit the output of block And 11.7, blocking the reset of the device to its original state. If two or more characters of the ternary code are erroneous in a row, then at the second input of AND block 11.7, the unit will be stored in time more than 1.5 · τ. Simultaneously with the arrival of this unit at the second input of the And 11.7 block, it also enters the input of the first DB 11.3 block, from the output of which a short pulse starts the one-shot OB 11.4. A pulse with a duration of 1.5 · τ from the output of the single-shot OB 11.4 is inverted by the second block HE 11.5 (erasure) and is fed to the input of the second block of the database 11.6. At the end of this zero (after a time of 1.5 · τ), a short pulse will arrive at the first input of the And 11.7 block from the output of the second DB 11.6 block, but at the same time, one is still fed to the second input of the And 11.7 block. So, from the output of block And 11.7 a short pulse will come out, which will reset the device to its original state.

Thus, the block BKD 11 allows you to go to the inputs of the block BKO 10 only one erased character of the ternary code, that is, it can skip the "ladder" of erased characters. Otherwise, the block BKD 11 resets the entire device to its original state.

The operation of the BKD block 11 in the case of erasures is additionally explained by the time diagrams presented in FIG. 5.

Schematic diagram and operation of the block OR 11.1 (two or more input) are given in [M. Mandl. 200 selected electronics circuits. / Per. from English under the editorship of J.S. Yitzhoki. M.: Mir, 1980, pp. 175-176, Fig. 8.2 (b)]. Implementation options for the DB 11.3, DB 11.6 blocks are given, for example, in [I. S. Gonorovsky. Radio circuits and signals. M .: Sov. Radio, 1977, pp. 222-223, Fig. 6.5 (b)], [S. I. Baskakov. Radio circuits and signals. M.: Higher School, 1983, pp. 252-253]. The circuit and operation of a block of type ОВ 11.4 are presented in [Application of integrated circuits. Practical Guide, book 1. M .: Mir, 1987, pp. 416-417, Fig. 7.7 (a)] or in [W. Titz, K. Schenck. Semiconductor circuitry. M .: Mir, 1982, pp. 98-99, Fig. 8.14].

The block diagram of the BVS 9 is presented in Fig.6, where it is indicated:

9.1-9.3, 9.18, 9.21, 9.30 - from the first to the sixth blocks of logical multiplication (I);

9.4-9.6, 9.20, 9.26, 9.27, 9.33, 9.34 - from the first to the eighth blocks of logical negation (NOT);

9.7-9.12, 9.22, 9.28, 9.29, 9.35, 9.36 - from the first to eleventh differentiation blocks (DB);

9.24, 9.25 - the first and second single vibrators for the duration of the information pulse (S);

9.13-9.16, 9.31, 9.32, 9.37 - from the first to the seventh logical addition blocks (OR);

9.17 - one-shot for a time equal to the duration of the information message minus half the duration of the information pulse (T _message - τ / 2);

9.19 - decimal counter for a given number (MF);

9.23 - one-shot for a time equal to the duration of three information pulses (3τ);

9A is a part of the BVS block 9 generating the first n clock pulses;

9B is a part of the BVS block 9, generating the last three clock pulses.

The BVS block 9 contains a part 9A generating the first n clock pulses and a part 9B generating the last three clock pulses.

Part of block 9A contains the first block AND 9.1, the first block HE 9.4, the first DB 9.7 block and the first block 9.13, the second AND block second, the second HE 9.5 block, the third 9.9 block and the second OR 9.14 block, the third block connected in series And 9.3, the third block is NOT 9.6, the fifth block of the database is 9.11 and the third block is OR 9.15. In addition, the output of the first block And through the second block of the database 9.8 is connected to the second input of the first block OR, the output of which is connected to the first input of the fourth block OR 9.16, the output of the second block And 9.2 through the fourth block of the database 9.10 is connected to the second input of the second block OR 9.14, the output of which is connected to the second input of the fourth block OR 9.16, the output of the third block AND 9.3 through the sixth block of the database 9.12 is connected to the second input of the third block OR 9.15, the output of which is connected to the third input of the fourth block OR 9.16. In this case, the first signal inputs of blocks And 9.1-And 9.3 are inputs for the corresponding elements of ternary symbols (columns) coming from the corresponding outputs of the FTK 8 block (figure 2).

Part of block 9B contains series-connected OB block at T-τ / 2 9.17, fourth block I 9.18, SCh 9.19, fourth block HE 9.20 and seventh block 9.22, series-connected first block OB 9.24, fifth block HE 9.26 and the eighth DB block 9.28, the output of which is connected to the second input of the sixth block OR 9.32 and to the input of the second block ОВ 9.25, the output of which is connected through the sixth block HE 9.27 and the ninth block DB 9.29 in series with the third input of the sixth OR 9.32 block, the eighth block HE 9.34, the tenth DB 9.35, OB at 3τ 9.23, the output of which is connected n with the input of the seventh block NOT 9.33 and the first input of the sixth block AND 9.30, the output of which is connected to the second input of the fifth block OR 9.31, the output of which is the first output of block 9. The output of the OB block at T-τ / 2 9.17 is connected to the input of the eighth block NOT 9.34 and the first input of AND block 9.21, the output of which is connected to the first input of the seventh OR block 9.37, the output of which is the second output of block 9. The output of the DB unit 9.22 is connected to the input of the first OB block 9.24, with the second input of the fifth And 9.21 block and the first input of the sixth block OR 9.32, the output of which is connected to the second input at the sixth block And 9.30. The output of the OB block at 3τ 9.23 is connected to the input of the seventh block of HE 9.33, the output of which is connected to the second inputs of the three blocks And 9.1, 9.2, 9.3, and through the eleventh block of the database 9.36 is connected to the second input of the seventh block OR 9.37. In addition, the output of the fourth block OR 9.16 is connected to the second input of the fourth block And 9.18 and to the first inputs of the fifth block OR 9.31 and OB at T-τ / 2 9.17, the second input of which is the second input of the counter 9.19, and the first input of OB at 3τ 9.23 connected to the fourth input of the BVS 9.

The operation of the BVS unit 9 is explained by the timing diagrams shown in Figs. 7-10. Figure 7 shows the timing diagrams for error-free reception at the most important points of part of block 9A: a) the initial sequence of binary symbols; b), c) and d) - the elements of the ternary code symbols (column elements) coming from the outputs of the FTK 13 to the corresponding inputs of the BVS 9. The first clock pulse from the output of the OR block 9.16 goes to the input of the OB 9.17 block and starts it, at the same time this clock pulse arrives to the first input of the OR block 9.31. While block OV 9.17 outputs one from the output of block And 9.30 and the midrange block 9.19 is working, zero is received at the second input of block OR 9.31, one is output from the output of block NOT 9.33 to the second control inputs of blocks And 9.1-I 9.3, allowing the input to ternary symbols code. Consequently, from the output of the OR block 9.31 all this time, clock pulses will come. Thus, during the duration of the message at each cycle at the output of the BVS 9, a synchronizing pulse is formed.

FIG. 8 shows timing diagrams for error-free reception at the most important points of a portion of block 9B. At the moment the last clock pulse arrives at the input of the midrange 9.19 block (for the time τ / 2 until the end of the operation of the OB 9.17 block), an pulse of duration τ will be output from the output of the midrange 9.19 block. At the end of the operation of the OB 9.17 block, its output will be zero. At this moment, a pulse from the output of the DB unit 9.35 will start the OB 9.23 block, and after a time τ / 2, from the output of the DB 9.22 block, the first additional clock will arrive at the input of the OB 9.24 block and the first input of the OR 9.32 block. At the time of starting the OB 9.23 block from the output of the HE 9.33 block, the second control inputs of the AND 9.1-I 9.3 blocks will receive zero, prohibiting the passage of any signals through these blocks, that is, zero will arrive at the first input of the OR 9.31 block. At the first input of AND block 9.30 from the output of the OV 9.23 block, a unit will be received, allowing the passage of an additional clock from the output of the OR block 9.31. Then, after a time τ, from the output of the DB unit 9.28, the second additional sync pulse will arrive at the second input of the OR 9.32 block and at the input of the OB 9.25 block, and another time after τ from the output of the DB unit 9.29, the third additional clock will arrive at the third input of the OR 9.32 block. These three clock pulses through blocks And 9.30 and OR 9.31 will sequentially go to the output of the BVS block 9. Then, after half a clock cycle, the block ОВ 9.23 will finish the work and from the output of the block DB 9.36 through the block OR 9.37 to the sixth input of block BKO 10 (figure 2), a pulse will arrive reset the device to receive the next message.

Figure 9 shows the timing diagrams at the most important points of the part of block 9B in the case when, due to the action of interference, the MF counter 9.19 will fix the required number of clock pulses before the OB 9.17 block finishes operation. At the same time, an output will be received from the output of the DB unit 9.22 to the second input of the And 9.21 block, and there will still be one at the first input of the And 9.21 block. So, from the output of the OR block 9.37 to the sixth input of the block BKO 10 (figure 2) will receive a reset pulse of the device to its original state.

Figure 10 shows the timing diagrams at the most important points of the part of block 9B in the case when the first character of the ternary code is erased. At the same time, block OB 9.17 will start working one beat later. At the output of the MF 9.19 counter, the pulse will not appear, since it will not fix the required number of clock pulses, therefore, the device will not be reset to its initial state. Upon completion of the operation of the OB 9.17 block, an impulse will be output from the output of the DB 9.35 block, which will start the OB 9.23 block. Until the end of the operation of this block, the device will receive information, but since part of block 9B will not generate three additional clock pulses, the last three characters of the ternary code will remain in the registers CP 8.1-CP 8.3 of the BKO block 10 (Fig. 2) and there will be no correct reception. Upon completion of the operation of the OB 9.23 block from the output of the DB 9.36 block through the OR 9.37 block, the impulse of resetting the device to its initial state will arrive at the sixth input of the BKO block 10 (FIG. 2).

The operation and timing diagrams at the most important points of the part of block 9B in the case when the last character of the ternary code is erased are similar to those described in the last paragraph, except that block OB 9.17 starts with the first clock and starts from the first beat.

The implementation of the midrange 9.19 block is presented in [Microcircuits and their application. Issue 1070. M .: Radio and communications, 1980, pp. 138-139, fig. 4.37 (a)] or in [Shilo V.L. Popular digital circuits. Reference .. M: Radio and communications, 1987 pp. 94-97, Fig. 1.69].

The block diagram of the block BKO 10 is presented in figure 11, where it is indicated:

10.1-10.3 - from the first to the third blocks of three-digit shift registers (SR);

10.4-10.6 - from the first to the third keys (C);

10.7-10.9, 10.14 - from the first to the fourth blocks of logical negation (NOT);

10.10-10.12 - from the first to the third blocks of summation modulo 2 (mod2);

10.13, 10.21 - the first and second blocks of logical summation (OR);

10.15-10.18, 10.20 - from the first to the fourth and fifth blocks of logical multiplication (I);

10.19 - differentiation unit (DB).

Block BKO 10 contains three blocks of three-digit shift registers (SR) 10.1, 10.2 and 10.3, the first signal inputs of which are inputs for the elements of the ternary code symbol (column elements) coming from the corresponding outputs of the FTK 8 block (figure 2), and the fourth outputs the first block 10.1 and the third block 10.3 are connected to the corresponding inputs of the PDD block 12 (figure 2), the second, fourth and sixth inputs of the blocks 10.1-10.3 are connected to the first output of the block BVS 9 (figure 2), blocks And 10.16-10.18, 10.20 and OR block 10.21, connected in series OR block 10.13 and block NOT 10.14, followed by newly connected block And 10.15 and block DB 10.19, series-connected block mod2 10.10, block HE 10.7 and Cl 10.4, series-connected block mod2 10.11, block HE 10.8 and Cl 10.5, series-connected block mod2 10.12, block HE 10.9 and Cl 10.6, third , the fifth and seventh inputs of blocks 10.1-10.3 are connected to the output of the OR block 10.21, the eighth inputs of blocks 10.1-10.3 are connected to the corresponding outputs of the keys 10.4-10.6, the first and third outputs of blocks 10.1-10.3 are connected to the signal inputs of the corresponding blocks of mod 2 10.10-10.12 , the outputs of the blocks are NOT 10.7-10.9 connected to the corresponding inputs of the block And 10.15, the first inputs of the blocks And 10.17, 10.18 are connected to the output of the block mod 2 10.10, the second inputs of the blocks And 10.16 and 10.18 are connected to the output of the block mod 2 10.12, the first input of the block And 10.16 and the second input of the block And 10.18 are connected to the output of the block mod 2 10.11, the second the outputs of blocks 10.1-10.3 are connected to the corresponding inputs of the OR block 10.13, the output of the block NOT 10.14 is connected to the first input of the block And 10.20, the output of the block DB 10.19 is connected to the second input of the block And 10.20, the output of which is connected to the third input of the block OR 10.21, the output of block And 10.16 is connected to the control input of the key 10.4, the output of block And 10.17 is connected to the control th input keys 10.5, 10.18 and output unit connected to the control input of the key 10.6 the first input of OR 10.21 is coupled to the second output UA unit 9 (Figure 2) and its second input connected to the output of BCD block 11 (Figure 2).

The states of the inputs and outputs of all blocks included in the BKO 10 are determined by the state of the contents of the bits of the registers 10.1-10.3. In the initial state, the contents of blocks 10.1-10.3, the timer and the clock counter in the block BVS 9 (Fig.2) are reset, the keys 10.4-10.5 are closed. Block BKO 10 operates as follows.

.Reception without errors, for example, of the following fragment of a sequence of binary symbols: 111101100 ... At the same time, the ternary code symbols (columns) are received at the first signal inputs of CP 8.1-CP 8.3 blocks from the corresponding outputs of FTK 13 (Fig. 2):

.

. При этом на вторых выходах регистров 10.1-10.3 будут нули, которые поступят на соответствующие входы блока ИЛИ 10.13. На выходах блоков mod2 10.10-10.12 будет результат сложения по mod2 содержимого первых и третьих разрядов регистров 10.1-10.3 соответственно: 1⊕ 0=1, 0 ⊕ 0=0, At the moment the first column arrives at the corresponding inputs of blocks 10.1-10.3 from the first output of the BVS block 9 (Fig. 2), clock pulses arrive, under the influence of which the ternary code symbols begin to fill the bits of blocks 10.1-10.3. At each clock cycle, the contents of the bits of blocks 10.1–10.3 can be represented in the form of a matrix (triad of symbols of the ternary code). In this case, the operation of the BKO block 10 will be represented by table 1, in the corresponding columns of which we will record the results of each clock cycle at the output of all its blocks. At the first step, the contents of the third bits of the registers 10.1-10.3 will be replaced by the first column [100] ^T and the contents of the registers will be represented by a matrix

. Moreover, on the second outputs of the registers 10.1-10.3 there will be zeros that will go to the corresponding inputs of the OR block 10.13. The outputs of mod2 blocks 10.10-10.12 will be the result of adding mod2 of the contents of the first and third bits of the registers 10.1-10.3, respectively: 1⊕ 0 = 1, 0 ⊕ 0 = 0,

, ,

. Как видно из блок-схемы фиг.11, эти выходные значения блоков 10.1-10.3, mod2 10.10-10.12 и НЕ 10.7-10.9 будут определять результат выхода остальных блоков БКО 10 на каждом такте. На первом такте на выходе блока ИЛИ 10.13 будет нуль и с выхода блока НЕ 10.14 на первый вход блока И 10.20 поступит единица.0 ⊕ 0 = 0. These values will go to the corresponding inputs of the AND block 10.15. At the same time, the outputs of the blocks NOT 10.7-10.9 will have the inverted values of the results of addition by mod2 of the contents of the first and third bits of the registers 10.1-10.3, respectively:

, ,

. As can be seen from the flowchart of Fig. 11, these output values of blocks 10.1-10.3, mod2 10.10-10.12 and NOT 10.7-10.9 will determine the output of the remaining blocks of BKO 10 at each clock cycle. At the first clock cycle, the output of the OR block 10.13 will be zero and one from the output of the block NOT 10.14 will be sent to the first input of the block AND 10.20.

From the output of block And 10.15, zero will come to the input of block DB 10.19, and since there is no front, then from the output of block DB 10.19, the second input of block And 10.20 will receive zero (see table).

At the same time, a unit will arrive at the first input of block And 10.16 from the output of block mod2 10.11, zero will be received at its second input from the output of mod2 10.12, therefore, zero will come from its output to the control input of key 10.4, the key will be closed and the contents of the second bit of register 10.1 will remain unchanged. At the first input of block And 10.17 from the output of block mod2 10.10, one will be received, at its second input from the output of block mod2 10.12, zero will be received, therefore, zero will come from its output to the control input of key 10.5, the key will be closed and the contents of the second bit of register 10.2 will remain unchanged . Zero will arrive at the first input of block And 10.18 from the output of mod2 10.10, zero will go to its second input from the output of mod2 10.11, therefore, zero will come from its output to the control input of key 10.4, the key will be closed and the contents of the second bit of register 10.3 will also not will change. From the output of the AND block 10.20, the third input of the OR block 10.21 will receive zero. Since an error-free reception is assumed, the first and second inputs of the OR block 10.21 will also receive zeros on this clock cycle, therefore, the device will not be reset to its initial state, and then the next (second) clock cycle of the BKO block 10 will begin. The result of the first clock operation is presented in table 1 in the third column.

At the second step, the contents of the third digits are pushed out by the next column from the sequence of symbols of the ternary code into the second digits. On the third step, all bits of blocks 10.1-10.3 are filled with the received symbols of the ternary code. At the fourth, fifth and subsequent clocks, the elements of the columns from the fourth outputs of blocks 10.1 and 10.3 will go to the corresponding inputs of the block PDD 12 (figure 2). The results of the second, ..., seventh measures are recorded in the corresponding columns of table 1.

The analysis of table 1 shows that with error-free reception, the operation of correcting the contents of the second bits of one of the blocks of CP 10.1-10.3 is carried out only when the first and third characters of the ternary code (matrix columns) are different. Since in this case the second column is error-free, its elements will not change. In all other cases, there is only a shift in the contents of the registers.

Suppose that the first of them is erroneous in the received fragment of the sequence of ternary code symbols, while the reset pulse does not arrive from the output of the BKD block 11 (Fig. 2) to the second input of the OR block 10.23, but at the same time the BVS block 9 does not generate the first clock pulse, which means In this block, the MF counter 9.19 will not get one clock pulse to the specified number and there will be zero on its output, prohibiting the device from resetting to its original state. Block BKO 10 will start working from the second clock, but at the same time block BVS 9 will not give out the last three clock pulses in order to output the last three characters of the ternary code from blocks 10.1-10.3. The message will not be fully received. Then at the end of the operation of the OV 9.23 block of the BVS block 9 (Fig. 2), a short pulse will come out from the output of the DB unit 9.36, which will reset the device to its original state. The operation of the block BKO 10 in this case will be presented in table 2:

As can be seen from table 2, if the first character of the ternary sequence code contains a one-time (detectable) error, then the BVS unit 9 will always reset the device to its original state, as there will be no correct reception.

Similarly, the block BKO 10 works if the last character of the ternary sequence code is deleted.

Given that the block BKD 11 (figure 2) controls the duration of the erasure and resets the device to its original state, if more than one character of the ternary code is erased with a detected error, then we can say that the block BKO 10 will correct the detected errors, which are distributed in sequence characters of the ternary code through one (the so-called ladder), and the first and last characters in the triad must be error free.

Let the following fragment of the binary sequence be transmitted: 1101100 ... Consider the operation of block 10 in the distribution of errors by the “ladder”, that is, in the received fragment of the sequence of ternary code characters, the erased characters are represented by zero columns:

.

.

Table 3 shows the operation of the block BKO 10 for this case. The first measure is no different from the first measure with the error-free reception described above, and on the second measure in the matrix representing the contents of register bits 10.1-10.3, the two extreme columns will be zero. At the same time, there will be zeros at the output of mod2 blocks 10.10-10.12, there will be one at the output of blocks NOT 10.7-10.9, which means that there will be one at the output of OR block 10.13, zero at the output of NOT 10.14 block, and one at the output of AND 10.15 block. Since at the previous clock cycle the value at the output of the And 10.15 block was zero, then a pulse front appeared at the input of the DB 10.19 block at this beat, therefore, a short pulse will arrive from its output to the second input of the And 10.20 block. At the same time, a zero will be received at the second input of the AND 10.20 block from the output of the NOT 10.14 block, which means that resetting the device to its original state on this clock cycle will be blocked. At the same time, zeros will come from the inputs of mod2 blocks 10.10-10.12 to the corresponding inputs of blocks And 10.16-10.18, which means that zeros will come from their outputs to the control inputs of keys 10.4-10.6, so these keys will remain private and the contents of the second bits of the CP 10.1 registers -10.3 will not change.

заменит содержимое второго разряда этого регистра, то есть ошибка будет исправлена. Аналогично БКО 10 работает и далее. То есть при расположении ошибок «лесенкой» блок БКО 10 исправляет стертый символ троичного кода только тогда, когда он находится во вторых разрядах блоков 10.1-10.3. При этом необходимо, чтобы первый и третий символы троичного кода (столбцы) в триаде были различными. Если первый и третий символы троичного кода безошибочны, но одинаковы, а второй символ ошибочен (средний столбец матрицы нулевой), то блок БКО 10 формирует короткий импульс сброса устройства в исходное состояние (столбец 9 таблицы 3).The next clock will shift the contents of registers 10.1-10.3 by one clock cycle. On the third step, the zero column will fill the second bits of the registers 10.1-10.3, and the two extreme columns will be error-free. At the same time, the output of mod2 blocks 10.10-10.12 will be 1, 0, 1, respectively, and the output of blocks NOT 10.7-10.9 - inversions of these values, respectively, 0, 1, 0. At the first input of block And 10.20, one will be received from the output of block NOT 10.14, the output of block And 10.15 will be zero. So, from the output of the DB unit 10.19, the second input of the And 10.20 block will receive zero, prohibiting the reset of the device to its original state. At the same time, zero will arrive at the first input of the And 10.16 block and the second input of the And 10.18 block from the output of mod2 10.11, which means that the keys 10.4 and 10.6 will be locked. Units will be received at both inputs of block And 10.17 from the outputs of blocks mod2 10.10 and 10.12, which means that key 10.5 will be open and the result of a logical comparison of the first and third bits of register 10.2, namely

will replace the contents of the second bit of this register, that is, the error will be fixed. Similarly, BKO 10 works further. That is, when errors are located with a “ladder”, the BKO block 10 corrects the erased symbol of the ternary code only when it is in the second bits of blocks 10.1–10.3. Moreover, it is necessary that the first and third symbols of the ternary code (columns) in the triad be different. If the first and third characters of the ternary code are error-free, but the same, and the second character is erroneous (the middle column of the matrix is zero), then the BKO unit 10 generates a short pulse to reset the device to its original state (column 9 of table 3).

Implementation options for blocks 10.1-10.3 are presented in [Microcircuits and their application. Issue 1070. M .: Radio and communications, 1980, pp. 135-136, fig. 4.35 (a)] or in [Shilo V.L. Popular digital circuits. Reference .. M: Radio and communications, 1987 p. 108, fig. 1.76].

With the agreed bands of the signal spectra and the band of the transmission channel at the output of the DM 7 block (Fig. 2), the signals carrying information overlap in time. Block FTK 8 (figure 2) performs the formation of the symbols of the ternary code that do not overlap in time. This unit is made in the form of a differential amplifier with three inputs and three outputs, the output signals of which are determined by the voltage difference at its two inputs so that the output with the maximum voltage remains open, and the other two outputs are locked with a negative potential [Pavlov VN, Nogin V.N. Circuitry of analog electronic devices, M .: Hot line - Telecom, p. 107, Fig.6.8]. The introduction of the third input and the third output does not change the operation of such a device, since the signals from the output of the demodulator DM 7 appear sequentially in time, which determines the voltage difference at the two inputs of the FTK 8 block. Timing diagrams of the FTK 8 block shown in Fig. 12 further explain the operation of this unit. Here a), b) and c) are the elements of the ternary code symbols (column elements) coming from the outputs of DM 7, 13 to the corresponding inputs of FTK 8; a '), b') and c ') - elements of the ternary code symbols at the outputs of the FTK 8 block.

Block PTD 12 is a widely used trigger, executed on the logic OR NOT [G.I.Pukhalsky, T.Ya. Novoseltseva. Design of discrete devices on integrated circuits. M .: Radio and communications, 1990, pp. 66-68, fig. 2.36]. From the corresponding outputs of the BKO block 10, the first and third elements of the ternary code symbols (columns) are supplied to the two information inputs of the PDD block 12, and the restored binary sequence is received from the direct output of the PDD block 12 to the data input of the PDL 13 block. In this case, the inverse output of the PDD 12 block is not used.

Claims (1)

A device for transmitting digital information, consisting of a data transmission unit (BPRD) and a data reception unit (BPRM) connected by a communication line, while the BPRD contains a parallel to serial converter (PPS), the synchronization input of which is connected to the output of a clock pulse generator (GTI) , BPRM contains a serially connected block of allocation of the clock signal (BVS) and the converter of the serial code to parallel (PPR), characterized in that the following are entered: in BPRD - series-connected binary converter about the code in the code with three states (PDT), a modulator and a data transmitter (PRD), the output of which is the output of the BPS, the input and synchronization input of the PDT are connected respectively to the output of the PPS and to the output of the GTI, N inputs of the PPS are inputs of the BPS; in BPRM - a series-connected data receiver (PFP) and a demodulator, the outputs of which are connected to the corresponding inputs of the ternary code generator (FTK), the outputs of which are connected to the corresponding inputs of the BVS, error correction block (BKO) and erase duration control unit (BCD), when this first and second outputs BKO are connected respectively to the first and second inputs of the ternary code to binary converter (PDD), the output of which is connected to the second input of the SPR, N outputs of which are outputs BPRD, and the output of the BCD is connected with the fifth input of the BKO, the third output of which is connected to the fourth input of the BVS, the first output of which is connected to the first input of the control device and the fourth input of the BKO, the sixth input of which is connected to the second output of the BVS.

Images