RU2344472C1 - Computer - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: computer (PC) for digital processing of signals in real time scale, having modular architecture, contains central processor, one or more programmable signal processors, and also flash ROM and RAM. At that PC additionally contains one or more input-output devices, graphic controller, inputs-outputs of which are connected to busbar of PC system backbone, central processor, comprising microprocessor, nonvolatile ROM, flash nonvolatile storage device, nonvolatile storage device, inputs-outputs of which are connected to busbar of central processor system backbone, and also buffer unit, the first input-output of which is connected to central processor system backbone busbar, and the second input-output is connected to busbar of PC system backbone, programmable processor of signals additionally contains commutator of data input-output, and also commutator of system backbone interfaces.

EFFECT: increase of fast action, increase of reliability and expansion of functional resources of computer.

1 dwg

Description

The invention relates to the field of computer technology and can be used for digital signal processing in radar systems and information management systems located in mobile and stationary objects.

The multi-level computing system is known from the prior art (RU Patent for the invention No. 2193795, published November 27, 2002, IPC: G06F 15/16). The multi-level computing system contains the main and additional digital signal processing processors of the first level, data input buses, the main and additional digital computers of the second level, the digital computers of the third and fourth levels, the operator console, the bi-directional communication buses of the first, second and third levels.

The disadvantage of this multilevel computing system is a complex, hierarchical structure, which causes a relatively low reliability of the system, limiting the throughput of multilevel lines and increasing the response time of the system.

Known electronic computing machine (RU patent for the invention No. 2272317, published August 16, 2004, IPC: G06F 15/00). An electronic computer includes a central processor, read-only non-volatile memory, non-volatile non-volatile memory, non-volatile memory and data input-output device, the inputs and outputs of which are connected by a bi-directional bus.

The disadvantage of this electronic computer is the relatively low speed and limited functionality for signal processing.

The closest technical solution to the claimed one is a digital computer complex (CVC) for processing signals in sonar systems (RU Patent for the invention No. 2207620, published 06.27.2003, IPC: G06F 15/16), which is selected as a prototype .

CVC contains one or several computer modules made on the basis of universal microprocessors, one or several modules of a programmable signal processor (PPS), remote control modules, including monitors, remote computer, keyboard and pointing device. The PPS module combines several digital signal processors (DSPs) and one or more programmable switches in a group. The programmable switch receives data on the radial channel from the input of the CVC and commutes it into the input high-speed ring bus connected to one port of the DSP. Another DSP port is connected to the second bus, providing data exchange between the DSPs of the group and between each DSP and the common memory of the faculty. The CVC contains two Ethernet networks, while the PPS modules are combined with one computer module, and the computer modules are combined with remote control modules with another Ethernet network.

The disadvantage of this CVC is the need to use dual-port DSPs in the faculty, limiting the bandwidth of the sequential in structure ring bus of data input of the faculty and the channels of the local computer network connecting the faculty with a computer, which reduces the functionality and performance, reduces the reliability of the device.

The technical result of the invention is to improve performance, increase reliability and expand the functionality of an electronic computer.

The technical result is achieved due to the fact that the electronic computer (digital computer) for real-time digital signal processing, having a modular architecture, contains a central processor, one or more programmable signal processors, the inputs and outputs of which are connected to the system bus of the computer, and each of them includes one or more digital signal processors, as well as reprogrammable read-only memory and random access memory, whose inputs and outputs x connected to a bus line system programmable signal processor, wherein inputs of programmable signal processors, which are computer-input, coupled to the ADC, the output of one of the programmable signal processor is connected to the input of another programmable signal processor. In this case, the computer additionally contains one or more input-output devices, a graphic controller, the inputs and outputs of which are connected to the bus of the computer system bus, a central processor including a microprocessor, non-volatile read-only memory, non-volatile non-volatile storage device, non-volatile memory device, and non-volatile memory device which are connected to the system bus of the central processor, as well as a buffer device, the first input-output of which is connected to the bus the system mains of the central processor, and the second input-output is connected to the bus of the computer mains, the programmable signal processor further comprises a data input-output switch having two data input buses, which are inputs of the programmable signal processor, and two data output buses, which are outputs of the programmable processor signals, as well as the switch of system trunk interfaces, the input-output of the data input-output switch and the first input-output of the switch of system trunk interfaces The s are connected by the bus of the system main line of the faculty, the second input-output of the switch of the system main interfaces is connected to the bus of the system main line of the computer.

The structural diagram of an electronic computer is shown in the drawing, where:

1 - central processing unit;

2 - microprocessor (MP);

3 - non-volatile read-only memory (ROM);

4 - reprogrammable non-volatile memory device (PEPEZU);

5 - volatile memory device (EZZU);

6 - buffer device (BU);

7 - bus system bus central processor;

8 - graphic controller (GK);

9 - input-output device (I / O);

10 - bus system computer;

11 - programmable signal processor (PPP);

12 - digital signal processor (DSP);

13 - reprogrammable read-only memory (EEPROM);

14 - random access memory (RAM);

15 - switch input-output data (HPC);

16 - system trunk interface switch (KSMI);

17 - bus system trunk PPP;

18 - data entry bus;

19 - data output bus.

A computer is a monoblock device with a modular structure. The composition of the computer includes the following modules: a central processor, a graphics controller, one or more input-output devices, one or more programmable signal processors. The introduction of a computer programmable signal processor converts a computer into a two-level multiprocessor computing system.

Central processor 1 is the main computing device of the computer and provides the execution of universal data processing programs. The central processor 1 contains a microprocessor (MP) 2 implemented on the basis of microcircuits, 2 non-volatile non-volatile memory (PEZU) 3, non-volatile non-volatile memory (ROME) 4, non-volatile memory (EZZU) 5 and a buffer device (BU) 6, inputs and outputs which are connected to the bi-directional bus of the system bus of the central processor 7 of the central processing unit (CPU) 1.

The microprocessor 2 of the Central processor 1 executes the commands of the main computer program.

Permanent non-volatile memory device 3 provides a one-time recording of information in the manufacture of computers and its further storage without the possibility of change.

The reprogrammable non-volatile memory 4 is configured to record information repeatedly when the computer is in operation and to store it when the computer is off.

Volatile memory 5 provides the ability to repeatedly write and read information when executing a computer program.

The buffer device 6 provides coordination of the electrical signals of the bus system bus of the Central processor 7 and the bus system bus of the computer 10.

The system bus of the central processor 7 is a bi-directional parallel system bus and provides the exchange of data and control signals between the devices of the central processor 1.

The graphic controller 8 provides the accumulation of an array of image data, the formation and delivery of a video signal to a display device (monitor).

I / O devices 9 are interface devices and provide data exchange between computers and external devices of the target complex via universal or specialized interfaces.

The system bus of the computer 10 is a bi-directional parallel system bus and provides the exchange of data and control signals between the computer modules.

Programmable signal processor 11 is an additional computer computing device and provides input and software processing of data of digitized signals.

Programmable signal processor 11 includes one or more microcircuits of digital signal processors 12, reprogrammable read-only memory 13, random access memory 14, data input-output switch 15 and system trunk interfaces 16, the inputs and outputs of which are connected to the bi-directional bus of the system bus PPP 17 .

Electronic computer operates as follows. When the power is turned on or when the initial setup signal arrives at the central processor 1, the microprocessor 2 turns to the non-volatile memory device 3, which has a relatively small capacity. The microprocessor 2 reads from the permanent non-volatile memory 3 and executes an auxiliary program loading from the reprogrammable non-volatile memory 4 to the volatile memory 5 of the main computer program code. Downloading the main program is performed by blocks of a certain length with information integrity control using checksums of program blocks. Upon successful completion of the copying of all blocks of information, the microprocessor 2 starts the execution of the main program from the volatile memory 5, starting from the start address. Due to the short access time of a typical non-volatile memory 5 compared with a typical reprogrammable non-volatile memory 4, a relatively high computer speed is provided.

Then, the central processor 1 reads from the reprogrammable non-volatile memory 4 and loads the signal processing program information into the programmable signal processor 11. The Central processor 1 can write the information of the signal processing program to the reprogrammable read-only memory 13. Then the program to turn on the power or the initial setting signal of the programmable signal processor 11 is transferred from the reprogrammable read-only memory 13 to the internal random access memory of the digital signal processors 12. Or the central processor 1 writes the information of the signal processing program to the random access memory 14, and according to the signal Alu loading the digital signal processor 12, program information is transferred to the internal random access memory of the microcircuits of digital signal processors 12. Or the central processor 1 writes the information of the signal processing program directly to the internal random access memory of the microcircuits of digital signal processors 12. After the copying of the signal processing program to the memory of the programmable signal processor is completed 11, the central processor 1 sets the signal processing parameters and starts the execution of prog Amma signal processing with a predetermined address.

At the input of the programmable signal processor 11, which is the input of the computer, the data of the digitized signal are received in real time via the data input bus 18 from the high-speed digital channel. The source of the signal data are analog-to-digital conversion devices ADC1 and ADC2. The data is fed to the input of the data input-output switch 15, which performs the functions of end-to-end data switching from the data input bus 18 to the data output bus 19 - the “tunnel” and data switching from the data input bus 18 to the bus of the PPS 17 system bus — the “bridge”. The data input-output switch 15 performs data input into the random access memory 14 of the programmable signal processor 11 or data distribution between the digital signal processors 12 and data input into their internal memory. The digital signal processors 12 of the programmable signal processor 11 digitally process the signal data in accordance with the signal processing program.

Upon completion of the signal processing procedure, the programmable signal processor 11 outputs the signal processing data in one of three ways. When distributed processing of signal data by several programmable signal processors 11, the intermediate data is transmitted under the control of a digital signal processor 12 through a data input-output switch 15 and a data output bus 19 to a data input bus 18 of another programmable signal processor 11. The resulting signal processing program data is transmitted through a switch system bus interfaces 16 and the bus of the computer system bus 10 to the central processor 1. The programmable signal processor 11 is also m As a result of processing the signal data, it can form an array of image data, the data of which through the switch of the system trunk interfaces 16 and the bus of the system bus of the computer 10 in the direct memory access mode are transmitted to the graphic controller module 8 without the participation of the central processor 1.

For the central processor 1, the programmable signal processor 11 is an input / output device. The switch system trunk interfaces 16 module programmable signal processor 11 performs the functions of data exchange in the modes of "bridge" and "host".

In the "bridge" mode, the system trunk interface switch 16 performs data exchange between devices connected to the system bus of the faculty 17 and devices connected to the computer system bus 10, in one of three ways.

- In slave mode, under the control of a program executed by the central processor 1 or the digital signal processor 12.

- In the slave mode using the interrupt signals of the bus of the system bus of the computer 10 and the bus of the system bus of the faculty 17.

- In the mode of direct access to the memory of devices on the system bus of the computer 10 and the system bus of the faculty 17.

The bandwidth of the system trunk interface switch 16 in the "bridge" mode when exchanging data with buffering in the system trunk interface switch 16 is equal to the smallest bandwidth of the buses involved: the system main bus PPP 17 and the bus system main computer 10. For the claimed computer, the maximum bus bandwidth 10 main system bus (32-bit parallel PCI bus with a clock frequency of 33 MHz) is 1056 Mb / s, and the maximum throughput of the system bus PPP 17 (64-bit parallel bus with a clock frequency of 100 MHz) - 6400 Mbit / s, which significantly exceeds the maximum bandwidth of an Ethernet network - 100 Mbit / s.

In the “host” mode, the system trunk interface switch 16 exchanges data on the initiative of the faculty 11 with the capture of the bus of the system main faculty 17. The exchange begins with the operation of sending data on the computer system bus 10. The register or memory address is transferred to the system trunk interface switch 16 on the bus of the system trunk PPP 17, for the data output operation, the output data is also transmitted. Then, the switch of the system trunk interfaces 16 initiates the corresponding input or output operation on the bus of the system bus of the faculty 17. After the transfer operation is completed on the bus of the system bus of the faculty 17, the switch of the system bus interfaces 16 performs a data transfer cycle to the central processor 1 for the data input operation and then completes the transfer data for operations of input or output of data on the system bus of the computer 10.

The host mode of the system trunk interface switch 16 provides the central processor 1 with access to devices mapped to the address space of the bus of the system trunk PPS 17, including the internal registers and internal memory of the microcircuit of digital signal processors 12, the memory of the reprogrammable read-only memory 13 and the memory random access memory 14. This mode provides the ability to test the central processor 1 devices, data arrays and program code in amyati programmable signal processor 11, if necessary, rewrite the program code and, therefore, a computer configuration change computing devices. And also for remote debugging programs of the programmable signal processor 11 from the central processor 1.

Improving the performance of computers is achieved through the introduction of additional computing devices - programmable signal processors 11, the distribution of program execution between the central processor 1 and one or more programmable signal processors 11, data input to the programmable signal processor 11 via two data input buses 18, data exchange between the bus a computer system bus 10 and a bus system bus PPS 17 having a relatively high throughput through the switch system sweeping interfaces 16, the possibility of exchanging data between programmable signal processors 11 by connecting the data output bus 19 of one and the data input bus 18 of another programmable signal processor 11.

The reliability of a computer is improved by parallelizing the input data stream over two data input buses 18 for each programmable signal processor 11, relaying the data coming through the data input bus 18 of one programmable signal processor 11 to the data input bus 18 of another programmable signal processor 11 through the input switch -data output 15, the possibility of using the host function of the switch interface of the system backbone interfaces 16 for testing by the central processor 1 device c, data arrays and program code in the memory of the programmable signal processor 11, if necessary, rewriting the program code and, thus, changing the configuration of computer computing devices.

The expansion of computer functionality is provided by programmable signal processors 11, oriented to digital signal processing, distribution of program execution between the central processor 1 and one or more programmable signal processors 11, the possibility of processing programmable signal processor 11 of image data and outputting the generated image data array in the mode direct access to the memory of the switch system trunk interfaces 16 in the memory of the graphic con roller 8, building on the basis of two input data bus 18, the data output two tires 19 and the switch input-output data 15 of the programmable signal processor 11 as a serial, including ring and tree structures data exchange channel between the programmable signal processor 11.

Claims (1)

An electronic computer (computer) for real-time digital signal processing, having a modular architecture containing a central processor, one or more programmable signal processors, the inputs and outputs of which are connected to the bus of the computer system bus and each of them includes one or more digital signal processors, as well as reprogrammable read-only memory and random-access memory, the inputs and outputs of which are connected to the system bus of the program a signal processor, wherein the inputs of the programmable signal processors, which are computer inputs, are connected to the ADC, the output of one programmable signal processor is connected to the input of another programmable signal processor, characterized in that the computer additionally contains one or more input / output devices, a graphic controller, the inputs and outputs of which are connected to the bus of the computer system bus, a central processor including a microprocessor, non-volatile read-only memory, reprograms non-volatile non-volatile storage device, non-volatile storage device, the inputs / outputs of which are connected to the bus of the system bus of the central processor, as well as a buffer device, the first input-output of which is connected to the bus of the system bus of the central processor, and the second input-output is connected to the bus of the computer system bus , the programmable signal processor further comprises a data input-output switch having two data input buses that are inputs of the programmable signal processor , and two data output buses, which are outputs of a programmable signal processor, as well as a switch for system trunk interfaces, an input-output of a switch for input / output data and a first input-output for a switch for system trunk interfaces are connected by a bus of the system trunk of the faculty, and the second input-output of a switch for system trunk interfaces connected to the system bus of the computer.