RU2272360C1 - Data transfer device - Google Patents

Abstract

FIELD: general-purpose electronic circuits, such as those for data coding, decoding, and conversion in their transfer between distant subscribers.

SUBSTANCE: proposed device has data transmitting and receiving units connected to opposite ends of communication line. Transmission unit has parallel-to-serial code converter and scrambler; receiving unit has serial-to-parallel code converter and descrambler. These units function to identify definite codes in scrambled bit stream which are formed into random (unknown in advance) time moments. These moments serve as initial marks for determining boundaries between bytes in data bit stream and used for synchronous setting of scrambler and descrambler pseudorandom bit sequence generators in same states. In this way start bits determining boundaries between bytes and service frames designed for code synchronization of scrambler and descrambler are removed from data stream.

EFFECT: enhanced data transfer speed.

3 cl, 20 dwg

Description

The invention relates to general purpose electronic circuits, in particular to encoding, decoding and data conversion schemes for data transmission between subscribers remote from each other.

A device [1] for data transmission, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit contains the first and second exclusive-OR elements, the first amplifier and the first shift register, the inputs of the second exclusive-OR element are connected to the outputs the first shift register, and the output to the first input of the first exclusive OR element, the input of the serial data of the first shift register is connected to the output of the first exclusive OR element and to the input of the first of the amplifier, the synchronization input of the first shift register is the device synchronization input, the second input of the first element is Exclusive OR is the device data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a phase-locked loop generator, the second shift register, the third and fourth elements The exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop, the output of which is connected to the synchronization input The second shift register is the synchronization output of the device, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, the output of which is the device data output, and the second input is connected to the serial data input of the second shift register and with the output of the second amplifier.

In the device [1], the data transmission and reception units perform, respectively, the functions of a scrambler and descrambler. The input data is converted by a scrambler to a form in which they can be considered as pseudo-random. The descrambler performs the inverse transform, i.e. restores the original data. Scrambling data allows you to replace long sequences of zeros or ones (and not only these sequences) with pseudo-random bits, which eliminates the possibility of loss of synchronization between blocks of data reception and transmission. In addition, the energy spectrum of the transmitted signal is leveled, which helps to reduce the level of crosstalk induced on adjacent twisted pairs of wires of the communication cable.

The disadvantage of the device [1] is the propagation of errors that can occur when transmitting a signal over a communication line. So, a single error is converted into a triple, since the error bit is first directly transmitted to the output of the device data, and then, moving along the second shift register, it distortes the output data two more times.

A device [2] for transmitting data is known, comprising a data transmission unit and a data receiving unit connected to opposite sides of the communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first the shift register and the second exclusive OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first element OR to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first element Exclusive OR is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator , the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase by adjusting the frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element.

In the device [2], the shift register of the data receiving unit (descrambler) is logically isolated from the communication line, so there is no multiplication of errors coming from the line.

The device [2] has two disadvantages.

The first drawback is that in order to maintain synchronous operation of the shift registers of the scrambler and descrambler (in case of a device synchronization failure or when the receiver part is turned on for the first time), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long synchronization chains over the communication line bits. This reduces the effective data transfer rate on the line, complicates the exchange protocol and requires a considerable time for the descrambler to wait for the service frame in case of loss of synchronization. During this time, data transfer is not possible.

The second drawback is the lack of hardware for delimiting bytes in the bitstream of data transmitted over the communication line. To specify the boundaries between bytes, redundant bits must be entered into the data bitstream, which reduces the transmission rate. For example, according to US Pat. US 200220091721 A1, to each byte in the bitstream is added a demarcation bit received from a pseudo-random sequence of bits. The data receiver detects the demarcation bits due to their consistent match with the reference pseudo-random bit sequence. Another way of delimiting bytes in a bitstream (US Pat. No. 6,011808) also involves adding a delimitation bit to each byte. This bit is formed by duplication and inversion of the zero bit of the transmitted byte. As a result, the beginning of the byte is accompanied by the transmission of combinations of bits 01 or 10. The data receiver detects the delimitation bits and zero data bits due to their statistically stable coincidence with codes 01 or 10. Both methods of introducing the delimitation bits are uneconomical - there is one service bit for every eight data bits .

Both of the above disadvantages reduce the speed of data transmission through the device [2].

The purpose of the invention is to increase the speed of data transmission through the device.

The goal is achieved in that in a device for transmitting data containing a data transmission unit and a data receiving unit connected to opposite sides of the communication line, the data transmission unit comprises a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains the first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first The exclusive OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator frequencies, the second shift register, the third and fourth elements exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the generator input In the case of phase-locked loop, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element. The data transfer unit further comprises a parallel to serial code conversion unit, the group of data inputs of which is a group of device data inputs, and the byte synchronization output is the first output of the device byte synchronization, the scrambler further comprises a third shift register, a first decoder, a first trigger and a first inverter the output of which is connected to the synchronization input of the first trigger, the input of the first inverter is connected to the synchronization inputs of the first and third shift registers ditch, and also with the bit synchronization output of the parallel code to serial conversion unit, the control input of the first shift register is connected to the output of the first decoder and to the correction input of the parallel code to serial block, the data output of which is connected to the scrambler data input, the input of the third shift data the register is connected to the output of the first XOR element and to the data input of the first trigger, the output of which is connected to the input of the first amplifier, the inputs of the pair The allele data of the first shift register is connected to the outputs of the first decoder, the inputs of which are connected to the outputs of the third shift register, the data receiving unit further comprises a serial to parallel conversion unit, the group of data outputs of which is a group of device data outputs, and the byte synchronization output is the second byte output device synchronization, the descrambler further comprises a fourth shift register, a second decoder, a second and third triggers and a second invert p, the output of which is connected to the synchronization input of the second trigger and to the synchronization inputs of the second and fourth shift registers, the control input of the second shift register is connected to the output of the second decoder and to the correction input of the serial to parallel conversion unit, the data input of which is connected to the output of the third trigger, and the bit synchronization input - with the descrambler synchronization output, the input of the fourth data of the shift register is connected to the second input of the fourth element flashing OR and with the output of the second trigger, the data input of which is connected to the output of the second amplifier, the inputs of the parallel data of the second shift register are connected to the outputs of the second decoder, the inputs of which are connected to the outputs of the fourth shift register, the input of the serial data of the second shift register is connected to the first input of the fourth element An exclusive OR, whose output is connected to the data input of the third trigger, the synchronization input of which is connected to the synchronization output of the descrambler and to the input of the second nvertora.

The parallel-to-serial conversion unit contains a trigger, read-only memory, a parallel register, a shift register, a pulse generator and an inverter, a group of data inputs of the unit is connected to the inputs of the parallel data of the shift register, the serial data output of which is the data output of the unit, and the synchronization input is connected to the output of the pulse generator and with the input of the inverter and is the output of the bit synchronization of the block, the input of the correction block is connected to the input of the trigger data, the input is blue the timing of which is connected to the inverter output and to the parallel register synchronization input, the outputs of which are connected to the shift register control input, to the byte synchronization output of the block and to the inputs of the memory address, the outputs of which are connected to the parallel register data inputs, the trigger output is connected to the address input read-only memory device.

The serial to parallel conversion unit contains the first and second shift registers, an inverter, read-only memory, the first and second parallel registers, the data input of the second parallel register is connected to the data input of the first shift register and is the data input of the block, the synchronization input of the first shift register is connected to the inverter input and is the input of the bit synchronization of the block, the data input of the second shift register is the input of the block correction, the group of outputs of the second pa the parallel register is a group of data outputs of the block, the synchronization input of the second parallel register is connected to the output of the first parallel register and is the output of the byte synchronization of the block, the inverter output is connected to the synchronization inputs of the second shift register and the first parallel register, the outputs of the permanent storage device are connected to the inputs of the first parallel register and the address inputs with the output of the second shift register and with the outputs of the first parallel register.

Figure 1, a and b presents a functional diagram of a known generator of a pseudo-random sequence of bits and a table is a pointer to the points of connection of the feedback circuit of this generator; figure 2 is a functional diagram of a known device [1] for data transmission; figure 3 is a functional diagram of a known device [2] for data transmission; figure 4 is a functional diagram of the proposed device for data transmission; figure 5 is a functional block diagram of the conversion of the parallel code into the serial of the proposed device; figure 6 is a functional block diagram of the conversion of the serial code in parallel to the proposed device; in Fig.7, a - c is a state table of a generator of a pseudo-random sequence of bits, a state diagram of this generator and an example of a code situation that explains the operation of the proposed device; on Fig - timing diagrams of the operation of the scrambler of the proposed device; figure 9 is a timing diagram of the descrambler of the proposed device; figure 10 is a diagram illustrating the process of data transfer by the proposed device in the absence of a signal for correction of boundaries between bytes; 11 is a diagram explaining the data transfer process of the proposed device in the presence of a signal for correction of boundaries between bytes; on Fig - timing diagrams of the data transfer unit of the proposed device in the absence of a signal for correction of boundaries between bytes; on Fig - timing diagrams of the operation of the data transmission unit of the proposed device in the presence of a signal for correction of boundaries between bytes; on Fig - timing diagrams of the operation of the data receiving unit of the proposed device in the absence of a signal for correction of boundaries between bytes; on Fig - time diagrams of the operation of the data receiving unit of the proposed device in the presence of a signal for correction of boundaries between bytes;

The generator 1 of the pseudo-random sequence of bits (Fig. 1, a) contains a shift register 2, the outputs of bits M and N of which are connected to the inputs of the Exclusive OR 3 element, the output of which is connected to the input of the serial data of the shift register 2 and is the output 4 of the generator 1 of the pseudo-random sequence of bits , the input 5 synchronization of the shift register 2 is the synchronization input of the generator 1 of the pseudo-random sequence of bits. The direction of the data shift in register 2 is shown by arrow 6. The bit numbers M and N of register 2 are selected from shown in Fig. 1, b of table 7 — pointer of the connection points of the feedback circuit.

The known [1] device 8 for transmitting data (FIG. 2) contains data transmission unit 10 (scrambler) and data reception unit 11 (descrambler) connected to opposite sides of the communication line 9, data transmission unit 10 contains the first 12 and second 13 exclusive elements OR, the first 14 amplifier and the first 15 shift register, inputs of the second 13 Exclusive element OR connected to the outputs of the first 15 shift register, and the output to the first input of the first 12 element Exclusive OR, the serial data input of the first 15 shift register is connected to the output the first 12 exclusive-OR elements and with the input of the first 14 amplifier, the synchronization input of the first 15 shift register is the device synchronization input 16, the second input of the first 12 exclusive-OR elements is the device data input 17, the output of the first amplifier 14 is connected to the communication line 9, reception block 11 the data contains a phase-locked oscillator 18, a second 19 shift register, a third 20 and a fourth 21 exclusive-OR elements and a second 22 amplifier, the input of which is connected to communication line 9, and the output to the input of generator 18 with automatic frequency locking, the output of which is connected to the synchronization input of the second 19 shift register and is the device synchronization output 23, the outputs of the second 19 shift register are connected to the inputs of the third 20 Exclusive OR elements, the output of which is connected to the first input of the fourth 21 elements of the Exclusive OR, whose output is the output 24 of the device data, and the second input is connected to the serial data input of the second 19 shift register and the output of the second amplifier 22. The data shift directions in the registers 15 and 19 are shown by arrows 25. An external data source 26 (for example, the first computer) is connected to the inputs 16 and 17 of the device 8. An external data receiver 27 (for example, a second computer) is connected to the outputs 23 and 24 of the device 8.

The known [2] device 28 for transmitting data (Fig. 3) comprises data transmitting unit 30 (scrambler) and data receiving unit 31 (descrambler) connected to opposite sides of the communication line 29, data transmitting unit 30 includes a pseudo-random bit sequence generator 32, the first The 33 XOR element and the first 34 amplifier, the pseudo-random sequence of bits generator 32 contains the first 35 shift register and the second 36 XOR element, the inputs of which are connected to the outputs of the first 35 shift register, and the output to the first input to the first 33 exclusive-OR elements and to the serial data input of the first 35 shift register, the synchronization input of which is the scrambler 30 synchronization input 37, the second input of the first exclusive-OR element is the scrambler 30 data input 38, the output of the first amplifier 34 is connected to the communication line 29, block 31 data reception (descrambler) contains a phase-locked oscillator 39, a second 40 shift register, a third 41 and a fourth 42 exclusive-OR elements and a second amplifier 43, the input of which is connected to the communication line 29, output - to the input of oscillator 39 with the phase locked loop, whose output is the output 44 of descrambler synchronization 31, the outputs of the second shift register 40 are connected to the inputs of a third exclusive-OR element 41, whose output is connected to first input 42 of the fourth exclusive-OR element.

In block 30, the output of the first 33 XOR element is connected to the input of the first 34 amplifier. The data receiving unit 31 also contains a multiplexer 45, the output of which is connected to the serial data input of the register 40, and the control input is the control input 46 of the device 28. The first data input of the multiplexer 45 is connected to the first input of the fourth 42 XOR elements. The second data input of the multiplexer 45 is connected to the second input of the fourth exclusive-OR element 42 and to the output of the second amplifier 43. The output of the fourth element 42 Exclusive OR is the data output 47 of the device 28. The synchronization input of the register 40 is connected to the synchronization output 44 of the device 28. The data shift directions in the registers 35 and 40 are shown by arrows 48. An external data source 49 (for example, the first computer) is connected to the inputs 37 and 38 of the device 28. An external data receiver 50 (for example, a second computer) is connected to the outputs 44 and 47 and to the input 46 of the device 28.

The proposed device for transmitting data (Fig. 4) comprises data transmitting unit 52 and data receiving unit 53 connected to opposite sides of the communication line 51, data transmitting unit 52 contains a scrambler 54, containing a pseudo-random sequence of bits generator 55, the first 56 exclusive OR element, and the first 57 amplifier, generator 55 of the pseudo-random sequence of bits contains the first 58 shift register and the second 59 XOR element, the inputs of which are connected to the outputs of the first 58 shift register, and the output to the first input the first 56 exclusive OR element and to the serial data input of the first 58 shift register, the synchronization input of which is the scrambler synchronization input 60, the second input of the first exclusive OR element is the scrambler data input 61, the output of the first amplifier 57 is connected to the communication line 51, reception unit 53 the data contains a descrambler 62 containing a phase-locked loop generator 63, a second 64 shift register, a third 65 and a fourth 66 exclusive-OR elements and a second amplifier 67, the input of which is connected to the line with monitor 51, and the output is to the input of a phase-locked loop generator 63, the output of which is synchronization output of descrambler 62, the outputs of the second 64 shift register are connected to the inputs of the third 65 exclusive-OR element, the output of which is connected to the first input of the fourth 66 exclusive-OR element.

The data transfer unit 52 also contains a parallel to serial code converting unit 69, the data input group of which 70 is a group of device data inputs, and the byte synchronization output 71 is a first byte synchronization output of the device, the scrambler 54 further comprises a third 72 shift register, a first 73 decoder, the first 74 trigger and the first 75 inverter, the output of which is connected to the synchronization input of the first 74 trigger, the input 60 of the first 75 inverter is connected to the synchronization inputs of the first 58 and third 72 shift p registers, as well as with the output of the bit synchronization of the block 69 converting the parallel code into serial, the control input of the first 58 shift register is connected to the output of the first 73 decoder and with the input 76 of the correction unit 69 converting the parallel code into serial, the data output of which is connected to the input 61 of the scrambler data 54, the input of serial data of the third 72 shift register is connected to the output of the first 56 Exclusive OR element and to the data input of the first 74 trigger, the output of which is connected to the input of the first 57 amplifier, inputs 77 of parallel data of the first 58 shift register are connected to the outputs of the first 73 decoder, the inputs of which are connected to the outputs of the third 72 shift register.

The data receiving unit 53 also contains a serial to parallel conversion unit 78, the data output group 79 of which is a device data output group, and the byte synchronization output 80 is a second device byte synchronization output, the descrambler 62 further comprises a fourth 81 shift register and a second 82 decoder, the second 83 and third 84 triggers and the second 85 inverter, the output of which is connected to the synchronization input of the second 83 triggers and to the synchronization inputs of the second 64 and fourth 81 shift registers, controls the input input of the second shift register is connected to the output of the second decoder and to the correction input 86 of the serial to parallel conversion unit 78, the data input 87 of which is connected to the output of the third 84 trigger, and the bit synchronization input to the descrambler synchronization output 68, the fourth serial data input 81 the shift register is connected to the second input of the fourth 66 XOR element and to the output of the second 83 trigger, the data input of which is connected to the output of the second 67 amplifier, inputs 88 of parallel data x the second 64 shift register is connected to the outputs of the second 82 decoder, the inputs of which are connected to the outputs of the fourth 81 shift register, the serial data input of the second 64 shift register is connected to the first input of the fourth 66 exclusive-OR element, the output of which is connected to the data input of the third 84 trigger, input synchronization which is connected to the output 68 of the descrambler synchronization and with the input of the second 85 inverter. Arrows 89 indicate the direction of data shift in registers 58, 64, 72, and 81.

Block 69 converting a parallel code into a serial one (Fig. 5) contains a trigger 90, a read-only memory (ROM) 91, a parallel register 92, a shift register 93, a pulse generator 94 and an inverter 95, the block 70 of the block data inputs is connected to the inputs of the parallel shift data register 93, the output of 61 serial data of which is the output of the data of the block, and the synchronization input is connected to the output of the pulse generator 94 and to the input of the inverter 95 and is the output of 60 bit synchronization of the block, the input 76 of the correction block 69 is connected n with a data input of a trigger 90, the synchronization input of which is connected to the output of the inverter 95 and with the synchronization input of the parallel register 92, the outputs of which are connected to the control input 96 of the shift register 93, with the output 71 of the byte synchronization of the block 69 and with the inputs of the address of the ROM 91, the outputs of which connected to the data inputs of the parallel register 92, the output of the trigger 90 is connected to the input address of the ROM 91. The direction of the data shift in the register 93 is shown by arrow 97.

Block 78 converting the serial code into parallel (Fig.6) contains the first 98 and second 99 shift registers, inverter 100, ROM 101, the first 102 and second 103 parallel registers, the data input of the second 103 parallel register is connected to the data input of the first 98 shift register and is the data input 87 of block 78, the synchronization input of the first 98 shift register is connected to the input of the inverter and is the input 68 of the bit synchronization of block 78, the data input of the second 99 shift register is the input 86 of the correction block 78, the group of outputs of the second o 103 parallel register is a group 79 of the data outputs of block 78, the synchronization input of the second 103 parallel register is connected to the output of the first 102 parallel register and is the output 80 byte synchronization of block 78, the output of the inverter 100 is connected to the synchronization inputs of the second 99 shift register and the first 102 parallel register , the outputs of the ROM 101 are connected to the inputs of the first 102 parallel register, and the address inputs are with the output 104 of the second 99 shift register and with the outputs of the first 102 parallel register. The direction of the data shift in registers 98 and 99 is shown by arrows 105.

Table 106 (FIG. 7 a) provides a list of states of the pseudo-random bit sequence generator 55; the state diagram 107 of this generator (Fig. 7, b) reflects the movement of the current state indicator 108 along the ring path; lines 109 and 110 divide the diagram into four sectors. Table 111 (Fig. 7, b) shows an example of a code situation explaining the operation of the proposed device.

Timing diagrams 112 and 113 (Fig. 8) correspond to the signals at the inputs 60 and 61 of the scrambler 54; chart 114 - the signal at the output of the element Exclusive OR 59; chart 115 - the signal at the output of the element Exclusive OR 56; chart 116 - signals at the outputs of the register 72; chart 117 - the signal at the control input P / S register 58 (point 76); chart 118 - states of the generator 55 of the pseudo-random sequence of bits; chart 119 is a signal at the input of amplifier 57.

Timing diagram 120 (Fig.9) correspond to the signal at the output of amplifier 67; chart 121 - the signal at the output of inverter 85; chart 122 - the signal at the output of the trigger 83; chart 123 - signals at the outputs of the register 81; chart 124 - the signal at the control input P / S * register 64 (point 86); chart 125 - the state of the register 64 of the generator of the pseudo-random bit sequence of the descrambler 62; chart 126 - the signal at the output of the element Exclusive OR 65; chart 127 - the signal at the output of the element Exclusive OR 66; chart 128 is a signal at the input of inverter 85; chart 129 - the signal at the output of 87 descrambler 62.

The sequence of bytes 130 (Fig. 10) received from the inputs of the device 70 in steady state is transmitted over the communication line 51 in the form of a continuous bit stream in which bytes 131 are placed. After receiving them, the output sequence of bytes 132, which coincides with input. Arrows 133 represent the data conversion sequence.

The sequence of bytes 134 (Fig. 11) received from the inputs of the device 70 in the byte boundary correction mode is transmitted over the communication line 51 in the form of a continuous bit stream in which bytes 135 are placed. At the time 136 of the correction, part 137 of the transmitted byte is ignored, after which it retransmitted (byte 138). At the outputs 79 of the device, an output sequence of bytes 139 is formed that matches the input. Arrows 140 reflect the data conversion sequence.

Timing diagrams 141 and 142 (Fig. 12) correspond to the signals at the input and output of inverter 95 (Fig. 5); diagrams 143 and 144 - to signals at the data input and the output of the trigger 90; diagrams 145 and 146 - to signals at points 71 and 96; diagrams 147 and 148 - to signals at points 70 and 61; diagrams 149 and 150 show the signals at the data input and output of the trigger 74 (Fig. 4); diagrams 151 and 152 - signals at the address inputs and outputs of the ROM 91 (figure 5).

Timing diagrams 153 and 154 (Fig.13) correspond to the signals at the input and output of the inverter 95; diagrams 155 and 156 - signals at the input of data and the output of the trigger 90; diagrams 157 and 158 - to signals at points 71 and 96; diagrams 159 and 160 - to signals at points 70 and 61; diagrams 161 and 162 - to the signals at the data input and the output of the trigger 74; diagrams 163 and 164 - signals at the address inputs and outputs of the ROM 91.

Timing diagrams 165, 166 and 167 (Fig. 14) correspond to signals at the data input, synchronization input, and trigger output 83 (Fig. 4); chart 168 is a sequence of bits in the input (leftmost) bit of the register 81; chart 169 shows the signal at point 86; chart 170 - state of the register 64; diagrams 171 and 172 - to the signals at the outputs of elements 65 and 66; diagrams 173 and 174 - to signals at points 68 and 87; chart 175 - 181 - signals in the register 98 (Fig.6); chart 182 - the signal at point 104; diagrams 183 and 184 - signals at the address inputs and outputs of the ROM 101; diagrams 185 and 186 - signals at the input of the upper (according to the scheme) discharge and the output 80 of the register 102; chart 187 - the signals at the outputs 79 of the register 103.

Timing diagrams 188, 189 and 190 (Fig. 15) correspond to signals at the data input, synchronization input, and trigger output 83; chart 191 is a sequence of bits in the input bit of the register 81; diagram 192 - to the signal at point 86; chart 193 - states of the register 64; diagrams 194 and 195 — to signals at the outputs of elements 65 and 66; diagrams 196 and 197 - signals at points 68 and 87; chart 198 - 204 - signals in the register 98; chart 205 - the signal at point 104; diagrams 206 and 207 - signals at the address inputs and outputs of the ROM 101; diagrams 208 and 209 - signals at the input of the upper (according to the scheme) discharge and the output 80 of the register 102; chart 210 - to the signals at the outputs 79 of the register 103.

The following is a brief description of the operation of known devices [1,2].

Scramblers and descramblers typically contain pseudo-random bit sequence generators or fragments of such generators. An example of constructing a generator of a pseudo-random sequence of bits is shown in figure 1 (see the book. P. Horowitz, W. Hill "The Art of Circuit Engineering": In three volumes - M .: Mir, 1993. - 2 tons). Generator 1 is made on the basis of shift register 2 with an exclusive OR (XOR) 3 logic element in the feedback circuit.

In the initial state, any non-zero code is present in register 2 (the initial setup circuit of the register is not shown). Under the influence of the positive edges of the clock signal CLK at input 5, this code circulates in the generator and simultaneously modifies. In each clock cycle (CLK signal period), the code advances in register 2 in the direction indicated by arrow 6, while the data bit from output 4 is entered into the freed register bit. As an output from the generator, you can use the output of the exclusive OR 3 element or the output of any bit of the register.

In the general case, when using the M-bit register 2, the feedback circuit is connected to the digits with the numbers M and N (M> N). In order for a pseudo-random sequence of bits with a repetition period equal to 2 ^m - 1 to be formed at the output of the generator, you should select the connection points of the feedback circuit in accordance with table 7 (Fig. 1, b), which describes a number of generators of different lengths. When the generator is operating in register 2, all possible M-bit codes are generated, except for zero. (Note that in all the devices described below it is possible to use advanced generators that do not have forbidden states, see, for example, Prince B. Shevkoplyas "Microprocessor Structures. Engineering Solutions": Reference. - Supplement One. - M .: Radio and communication, 1993. - 256 p.).

A pseudo-random sequence of bits with a repetition period of 2 ^m - 1 has the following properties.

1. In the full cycle (2 ^m - 1 ticks) the number of logs. 1, formed at the output 4 of generator 1, is one more than the number of log.0. Additional log. 1 appears due to the exclusion of a state in which a zero code would be present in register 2. This can be interpreted so that the probabilities of occurrence of log.0 and log.1 at the output 4 of generator 1 are almost the same.

2. In a full cycle (2 ^m - 1 ticks) half of the series from consecutive logs. 1 has a length of 1, one-fourth of a series is a length of 2, one-eighth of a series of length 3, etc. Series from log.0 have the same properties, taking into account the missing log.0. This suggests that the probabilities of the appearance of "eagles" and "tails" do not depend on the outcome of previous "tosses." Therefore, the probability that a series of consecutive log. 1 or log. 0 ends at the next toss is 1/2.

3. If we compare the sequence of the full cycle (2 ^m - 1 cycles) with the same sequence, but cyclically shifted by any number of cycles W (W is not zero or a multiple of 2 ^m - 1), then the number of mismatches will be one more, than the number of matches.

The most common are two main schemes of devices for data transmission (devices of the "scrambler - descrambler" type): with non-isolated and isolated (from the communication line) generators of pseudo-random bit sequences.

In the device 8 (FIG. 2 [1]), the scrambler 10 and the descrambler 11 are made using fragments of the pseudorandom sequences of bits considered earlier 1 (see FIG. 1). An additional element Exclusive OR 12 is introduced into the feedback circuit of the generator based on the shift register 15. A similar generator based on the shift register 19 with an open feedback circuit is used in the descrambler.

All processes taking place in the device 8 are synchronized from a clock located in an external data source 26 (it can also be placed in block 10). The clock generates a signal CLK - a continuous sequence of clock pulses with a duty cycle equal to two. In each clock cycle, the next bit of the transmitted DATA data is fed to input 17 of the scrambler 10, and in the shift register 15, the accumulated code moves one bit to the right (arrow 25).

If we assume that data source 26 sends a long sequence of log.0 (DATA≡0) to scrambler 10, then the XOR 12 element can be considered as a repeater of the Y1 signal from the output of the XOR OR 13 element. In this situation, register 15 is actually closed in a ring and generates exactly the same pseudo-random sequence of bits as in the generator circuit 1 considered earlier (Fig. 1). If an arbitrary bit sequence is received from data source 26, then it interacts with the bit sequence from the output of the Exclusive OR 13. As a result, a new (scrambled) sequence of SCRD data bits is generated, which is close in structure to random. This sequence, in turn, advances in register 15, forms the bit stream Y1 at the output of the element Exclusive OR 13, etc.

A scrambled SCRD bit sequence passes through an amplifier 14, is transmitted over a communication line 9 (for example, over a twisted pair of wires of a multi-core cable of an urban telephone network) and enters a descrambler 11, where it passes through an amplifier 22. Using a generator 18 with phase-locked loop frequency from the input signal SCRD * (from the output of amplifier 22), a clock signal CLK * is allocated, which is transmitted to the clock input C of register 19 and to the output 23 of device 8.

The generator 18 with phase-locked loop frequency can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215.835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the SCRD * input signal. In this case, the negative edge of the signal CLK * is tied to the moments of change of the signal SCRD * (0 → 1 or 1 → 0), so that the positive edge of the signal CLK * is formed in the middle of the bit interval of the signal SCRD *, which corresponds to its steady-state value. The data shift in register 19 and the reception of the next SCRD * bit in the freed bit occur at the positive edge of the CLK * signal. The descrambled DATA * data arrives at the data receiver 27 and is captured therein along the positive edges of the CLK * signal.

Due to the sufficient inertia of the generator 18, the CLK * signal is practically insensitive to the "jitter" of the SCRD * signal and its other short-term distortions caused by interference in the communication line 9. (Such use of a standard generator with phase-locked loop in telecommunication systems is generally accepted and will not be described further. )

DATA and DATA * data streams match up to a delay in transmission. Indeed, in the steady state, the same codes are present in the shift registers 15 and 19, since the same data SCRD = SCRD * (taking into account the transmission delay) is supplied to the inputs D of these registers, and the clock frequency is the same. Therefore, Y2 = Y1, and, taking this into account, DATA * = SCRD * ⊕Y2 = SCRD⊕Y2 = (DATA⊕Y1) ⊕Y2 = DATA⊕Y1⊕Y1 = DATA⊕0 = DATA.

The considered method of scrambling - descrambling data does not require the use of any special initial synchronization procedure (as in the device [2]). After filling in the shift register 19, as was shown, the pseudorandom bit sequence generators based on registers 15 and 19 work synchronously (their states are always the same) and generate the same signals Y1 and Y2. When a single error occurs in the communication line 9, the code synchronization (the identity of the contents of registers 15 and 19) is temporarily violated, but then automatically restored as soon as the correct data is again filled in the register 19. However, in the process of moving the erroneous bit through the shift register 19, namely, the periods of its falling first on one and then on the other input of the Exclusive OR 20 element, the Y2 signal twice takes the wrong value. This leads to the propagation of a single error - it first appears in the DATA * signal at the moment it arrives from the line and then occurs two more times with a subsequent twofold distortion of the Y signal.

In the device 28 (Fig. 3 [2]), pseudo-random bit sequence generators isolated from the communication line 29 are used. Their initial code synchronization is performed using descrambler hardware and software source 49 and data receiver 50.

The hardware includes a multiplexer 45 (MUX) and a program-controlled output 46 of the data receiver 50, on which the control signal F. is generated. During normal operation of the scrambler-descrambler system, the data receiver 50 constantly supports the output signal F = 0. The signal Z2 from the output of the Exclusive OR 41 element is transmitted to the output of the multiplexer 45, the pseudo-random bit sequence generator based on register 40 is isolated from external influences.

Assume that in the initial state the descrambler is not synchronized with the scrambler. Such a situation may arise, for example, after turning on the supply voltage of the receiving side equipment, after an error in the operation of the descrambler generator 39 due to the influence of interference on the communication line or for other reasons. In the absence of code synchronization between the scrambler and the descrambler, the contents of registers 35 and 40 do not match, the received DATA * data stream is erroneous and does not match the DATA transmitted data stream.

Upon detection of a stable chaotic data stream DATA * (in which there is no separation of information frames caused by the protocol of exchange, etc.), the receiver generates a signal F = 1. As a result, the multiplexer 45 begins to transmit to the input D of the register 40 a signal of scrambled data SCRD *, as in the previously discussed device [1] (see figure 2).

The exchange protocol provides for the transfer of data in the form of a sequence of frames. Groups of regular frames are interspersed with overhead frames. For example, after a group of 1000 ordinary frames, one official follows. In particular, it contains a synchronization sequence of a certain number (for example, 256) of zero bits. When these bits are sent (DATA = 0) to the scrambler, the Exclusive OR 33 element acts as a repeater of the Z1 signal from the output of the Exclusive OR 36 element. Therefore, in this case, the scrambled SCRD signal is a fragment of a “true” pseudo-random bit sequence, in the sense that it not mixed with a stream of arbitrary DATA data and generated only by the 32 scrambler generator.

This sequence is automatically loaded into register 40 and passes through it, since F = 1. After the contents of the registers 35 and 40 are the same, the signal Z2 begins to repeat the signal Z1. Code synchronization is achieved. A continuous sequence of log.0 is supplied to the input of the data receiver 50, since DATA * = DATA = 0. After confidently detecting a sufficiently long (for example, containing 180 bits) sequence of log.0, the receiver 50 generates a signal F = 0 and thereby returns the generator of the pseudo-random sequence of bits of the descrambler to the isolated operation mode. Now, code synchronization is not only achieved, but also “saved” due to the logical isolation of register 40 from communication line 29. After the transmission of the service (synchronizing) frame is completed, the data source 49 proceeds with the transmission of a group of 1000 ordinary frames according to the exchange protocol adopted in the system.

Thus, in the device [2], in order to maintain synchronous operation of the shift registers of the scrambler and descrambler (in case of a violation of the device’s synchronization or when the receiver part is turned on for the first time), it is necessary to periodically interrupt the transmission of useful data and transmit service information frames containing sufficiently long chains over the communication line sync bits (DATA = 0.). As a result, the effective data transfer rate on the line decreases, and the exchange protocol is complicated. In addition, with an increase in the intervals between overhead frames (which is desirable for a more efficient transmission of useful data), the wait time for the descrambler in the event of loss of code synchronization increases. During this time, the transfer of useful data is not possible.

Unlike the device [2], the proposed device (Fig. 4) implements two improvements to increase the data transfer rate.

The first improvement consists in the fact that the restoration of code synchronization between the scrambler and descrambler in case of loss occurs without transferring any service synchronizing code sequences over the communication line. Therefore, the flow of useful data is not interrupted, the synchronization recovery time is reduced.

The second improvement is that information about the position of the boundaries between bytes (or other structural units) is introduced into the bit stream transmitted over the communication line, while the introduced redundancy is less than in known devices.

In general terms, the idea of the first improvement is as follows. The scrambler and descrambler contain pseudo-random bit sequence generators isolated from the communication line with the same feedback structure. The scrambled bit stream is constantly analyzed by the scrambler and descrambler in order to find certain codes in it. The detection of each such code by the scrambler and descrambler leads to the simultaneous installation of both generators of the pseudo-random sequence of bits in a certain state corresponding to this code. Thus, the generators at random moments are simultaneously set to the same state as the transfer of useful data. These events occur relatively rarely, i.e. most of the time, the generators operate in the mode of "natural" sequential transition from the previous state to the next, as was shown in the description of the generator 1 (figure 1). If the code synchronization has not been broken, then the moments of installation of the generators only confirms it. If the code synchronization was previously lost, then it is restored upon the first detection of one of the given codes in the stream of scrambled data.

The second improvement is also based on the fact that data transmission and reception units simultaneously (up to transmission delay) detect predetermined codes in a scrambled data stream. Code detection times are mapped to new boundaries between bytes in the bitstream. If the new boundaries coincide with the old, then the data transfer continues; if these boundaries do not coincide, the transmission of one of the bytes is interrupted, then it is retransmitted in accordance with the newly established boundaries. Subsequent bytes are transmitted in the new frame of reference until another correction of their position occurs, etc.

The following describes the operation of the components of the proposed device.

The shift registers 72 and 81 (Fig. 4) are intended for temporary storage of fragments of SDATA and SDATA * streams of scrambled data. In the steady state, these fragments are the same (coincide up to a transmission delay). Reception of the next bit in the register 72 (81) occurs on the positive edge of the signal at the clock input C of this register. Simultaneously with the reception of the next bit from input D, previously stored data is shifted by one bit to the right (arrow 89). In this example of the construction of the device, the width of the register 72 (81) is chosen to be eight, although it can be greater or less. The dynamics of the operation of the register 72 can be traced to the table 111 of its states (Fig.7, c).

The scrambler 54 pseudorandom bit sequence generator 55 contains a shift register 58 and an exclusive OR element 59. A similar descrambler pseudo random bit sequence generator 55 contains a shift register 64 and an exclusive OR element 65.

Shift registers 58 and 64 are intended for temporary storage of pseudo-random codes SRND and SRND *. In the steady state, these codes are the same (coincide with an accuracy of transmission delay). The next bit in register 58 (64) is received from input D along the positive edge of the signal at synchronizing input C, provided that its control input P / S (P / S *), which sets the mode of parallel or serial data reception, has a log signal .0. Simultaneously with the reception of the next bit from the input D, the previously stored code is shifted by one bit to the right (arrow 89). If at the control input P / S (P / S *) of register 58 (64) a signal log.1 is present, then on the positive edge of the signal at synchronizing input C, a parallel code from the group of inputs 77 (88) is received into the register. In this example of the construction of the device, the width of the register 58 (64) is chosen equal to five, although it can be greater or less. In this case, the connection points of the XOR element 59 (65) to the register 58 (64) are selected in accordance with the table presented in figure 1, b.

The initial state of the register 58 may be any, including zero. The exit from the zero state occurs when a parallel code is written to the register from inputs 77. The scrambler initialization program provides for the input of some CODE ₁ code to its input 61, which is recognized by the decoder 73. If the zero code was initially present in the register 58, then the CODE ₁ code passes without change through the XOR element 56 and is sequentially loaded into the register 72. The decoder 73 responds to it by transferring the register 58 to the parallel loading mode (P / S = 1) and generating a nonzero code LOAD ₁ which is then received in p register 58 from inputs 77. Thus, the generator 55 leaves the forbidden state 000 ... 0. If the initial state of register 58 was nonzero, then issuing CODE ₁ to input 61 is useless, but does not lead to any undesirable consequences. It is also possible to set the register 58 to a nonzero state (the corresponding input of the register 58 is not shown).

The initial state of the register 64 may also be any, including zero. This state is updated (becomes obviously nonzero) when one of the predefined codes (CODE ₁ and, possibly, others) is detected by the decoder 82 in the scrambled data stream.

An exclusive OR element 56 (59, 65, 66) generates a signal of logic 1 at the output only when the input signals have opposite logical values (log 0 and log 1). The exclusive OR elements 59 and 65 form the output signals RND and RND * of the pseudo-random bit sequence generators of the scrambler 54 and the descrambler 62. The exclusive OR elements 56 and 66 form the scrambled SCRD and descrambled DIN data signals.

D-type triggers 74, 83 and 84 receive data bits from input D along the positive edge of the signal at the clock input C. Triggers 74 and 84 generate DLINE and DATA * output signals, in which the signal can change only once at the boundaries between bit intervals, while the input signals SCRD and DIN of these triggers at the boundaries between bit intervals can change many times due to the non-simultaneous occurrence of transients (signal racing) in circuits 58 - 59 - 56; 61 - 56 and 64 - 65 - 66; 83 - 66. Trigger 83 eliminates input signal jitter (edge jitter at the boundaries between bit intervals) almost completely due to the fact that a bit is received in this trigger at the center of the bit interval when the transients of the DLINE * signal have already ended. The residual jitter of the SDIN signal at the output of the trigger 83 is determined by the imperfect CLK * signal at the output of the generator 63. The initial states of the triggers 74, 83, and 84 are arbitrary.

Inverter 75 (85) converts the input signal log.0 to the output signal log.1, and vice versa - the input signal log.1 to the output signal log.0.

Generator 63 with phase-locked loop can be performed according to one of the known schemes (see, for example, US Pat. No. 6,215,835 B1). It is designed to generate a highly stable CLK * clock based on continuous tracking of the DLINE * input signal. The positive edge of the CLK * signal is tied to the moments when the DLINE * signal changes (0 → 1 or 1 → 0), so that the negative edge of the CLK * signal is formed in the middle of the bit interval of the DLINE * signal, which corresponds to its steady-state value.

Due to the sufficient inertia of the generator 63, the CLK * signal is practically insensitive to the jitter of the DLINE * signal and its other short-term distortions caused by noise in the communication line 51. (Such use of a standard phase-locked oscillator in telecommunication systems is generally accepted and will not be described in detail below).

The decoder 73 (82) is designed to isolate in the stream of scrambled data passing through the shift register 72 (81) certain codes CODE ₁ , CODE ₂ , ..., СООЕ _k . When the decoder 73 (82) detects the indicated codes, the corresponding G-bit code LOAD ₁ , LOAD ₂ , ..., LOAD _k is formed at its outputs 77 (88) for subsequent parallel loading of the shift register 58 (64). In this example, the construction of the device K = 4, G = 5. If any code CODE ₁ , CODE ₂ , ..., CODE _{k is} detected, the decoder 73 (82) also generates a single signal at the input P / S (P / S *) of the operating mode of the register 58 (64), preparing it for parallel reception data on the positive edge of the next sync pulse at input C.

Amplifier 57 (67) is designed to transmit (receive) a scrambled data signal to the line (from line) 51. The parameters of amplifiers 57 and 67 are determined by the type of communication line 51, which can be made in the form of a twisted pair of wires, coaxial or fiber optic cable, etc. P.

In block 69 (Fig. 5), the conversion of the parallel code into a serial one contains a clock generator 94, which sets the pace of operation of the entire device. At the output 60 of the generator 94, a continuous pulse train is formed with a duty cycle of two. The T × D data bytes represented by the parallel code are supplied to inputs 70 in response to the positive edges of the T × C signal at output 71. The byte remains unchanged until the formation of the next positive edge of the T × C signal. Byte T × D is written to register 93 on the positive edge of signal C at its synchronization input (point 60) when there is a signal L = 1 at its control input P / S 96. At L = 0, on the positive edges of the signal CLK, a shift occurs in register 93 arrow 97.

In the absence of a correction signal (J = 0) at input 76, block 69 converts the T × D byte stream to a uniform DATA bit stream at output 61. The J = 1 signal causes the byte boundaries in the bit stream to be corrected if the new boundaries do not coincide with the old ones. This signal is temporarily stored in the trigger 90 and enters the firmware control device, made according to the known scheme based on read-only memory (ROM) 91 and the output parallel register 92. The signal J = 1, if necessary, pauses the transmission of the current byte, its repeated parallel reception from inputs 70 (where it remains unchanged) and repeated sequential output through the register 93. Encoding ROM 91 (microprogram) and the sequence of transitions on it are presented in Fig. 5, b.

In block 78 for converting the serial code to parallel (Fig. 6), the shift register 98 converts the serial data stream into parallel, the shift register 99 functions as a delay element for phase alignment of the signals at inputs 86 and 87. Parallel R × DATA data is written to the register 103 by the positive edges of the R × C signal at point 80.

In the absence of a correction signal (J * = 0) at input 86, block 78 converts the DATA * bit stream from input 87 into a uniform R × D byte stream at outputs 79. The correction signal J * = 1 is delayed by register 99 and fed to the firmware control device, made on the basis of ROM 101 and the output parallel register 102. The signal J * = 1 in necessary cases (when the new boundaries do not coincide with the old ones) causes the current byte to be re-formed. In this case, the R × C signal is generated only once, when the re-formed R × DATA byte is prepared for writing to the register 103. The encoding of the ROM 101 and the transition sequences along it are presented in Fig.6, b.

The following is a description of the operation of a larger fragment of the proposed device. This fragment includes a scrambler 54, a communication line 51 and a descrambler 62.

The DATA input data and the accompanying synchronization signal CLK go to the inputs 61 and 60 of the scrambler 54. The positive edges of the CLK signal (moments T0, T1, ..., T18 in Fig. 8) correspond to the boundaries between the bit intervals of the DATA data signal, as shown in diagrams 112 and 113. On the positive edges of the signal CLK, the contents of the register 72 change (diagram 116), the generator 55 transitions to new states (diagram 118). At the same time, for each positive edge of the CLK signal, the next pseudo-random RND bit is formed (diagram 114), which is added modulo two with the DATA data bit and converted into a scrambled SCRD data bit (diagram 115). At the end of the transient processes, at the moment of formation of the negative edge of the CLK signal, the SCRD bit is received in the trigger 74 (DLINE signal diagram 119) and transmitted through the amplifier 57 to the communication line 51.

In the time interval T8 - T9, the decoder 73 generates a signal J = 1 at the input P / S of the control mode of the operation of the register 58 (chart 117), preparing it to receive parallel data at the time T9.

In the absence of parallel loading, the generator 55 of the pseudo-random sequence of bits sequentially, cyclically passes through a series of states S1, S2, S3, ..., S31, S1, S2, etc., as shown in Fig. 7, a, b (table 106 Diagram 107). In state S1 (see the first row of table 106, as well as pointer 108 in diagram 107), a five-digit binary code 11111 ₂ = 1F ₁₆ is stored in register 58, and a signal 0 is generated at the output of RND generator 55. In the next step, the pointer 108 moves clockwise and locks in an adjacent position, the generator 55 switches to state S2, in which SRND = 01111 ₂ = 0F ₁₆ , RND = 0, etc. This process is cyclically repeated, the pointer 108 rotates in a circle, sequentially passing through all possible states S _i .

Parallel loading of the register 58 in an arbitrary cycle leads to the forced installation of the generator 55 in one of the specified states, in this example, in the states S3, S11, S19 or S27. These states are preferably selected so that in diagram 107 arcs S3 - S11, S11 - S19, S19 - S27 and S27 - S3 are approximately equal in length (see indicators 109 and 110, which divide the circle into four approximately equal parts). In the process of operation of the scrambler, the generator 55 is relatively rare, with equal probability is set in these states, and in the intervals between such settings, the pointer 108 continues to uniformly (stepwise) clockwise rotation.

The choice of several (and not one) given states to which the generator 55 goes over at the moments of its parallel loading is advisable in those cases when the number of states of the generator is large enough and during a full turn of the pointer 108 the probability of parallel loading of the register 58 is close to unity. Therefore, if the pointer 108 periodically "breaks" from uniform rotation and falls into the same predetermined state, then the likelihood that he manages to make at least one full revolution becomes low. In other words, some states of the generator 55 will be used less frequently than others, and then the properties of the “canonical” pseudo-random sequence of bits noted earlier (when describing the generator 1, see FIG. 1) will be lost to some extent, which is undesirable. The presence of several fixed installation points, evenly distributed over the diagram 107, evens out the probabilities of using all possible states of the generator 55.

As shown in diagrams 116 and 117, one of the codes causing the generator 55 to be forced to a fixed state is SDATA = CODE ₁ = 62 ₁₆ , = 01100010 ₂ . This code is present in register 72 in the time interval T8 - T9 and, as already noted, the decoder 73 responds to it by preparing register 58 to receive the parallel LOAD ₁ code from inputs 77. This code in this example is 0E ₁₆ = 01110 ₂ and corresponds to the state S11 of the generator 55 (see table 106 in Fig.7, a). Thus, at time T9, the chain of successive transitions ... S16, S17, ..., S23, S24 is broken, and instead of switching to the next state S25, the generator 55 “jumps” to the state S11. After this, a new chain of successive transitions is formed: S11, S12, ..., S18, S19, ... - until the next situation arises in which this circuit breaks, and then the next chain is formed with one of the initial states S3, S11, S19 or S27 etc.

The scrambled DLINE * data received from line 51 synchronizes the generator 63 with phase-locked loop, as a result of which the signal CLK * is generated at its output, and its inverse value is generated at the output of the inverter 85 (diagrams 120, 128, 121 in Fig. 9). The SDIN signal (diagram 122) at the output of the trigger 83 repeats the DLINE * signal with a delay of half the clock period, while the SDIN signal, as already noted, practically does not contain phase distortion (jitter). The scrambled SDIN data passes sequentially through the register 81. After filling it, the SDATA * data (diagram 123), up to the transmission delay, coincides with the SDATA data in the register 72 of the scrambler 54.

This follows from the fact that, firstly, the data source for both registers is common - the output of the Exclusive OR 56 element, and, secondly, nothing prevents the simultaneous (up to a transmission delay) filling of both registers with the same data. Since the decoders 82 and 73 are identical, and the data at their inputs are the same, the signals at the outputs of these decoders are also the same (up to a transmission delay). It follows that the previously considered process of setting the generator 55 to a certain state also proceeds in descrambler 62, namely, in the time interval T8 - T9 (Fig. 9), the signal J * = 1 is formed at the input P / S * of register 64 ( diagram 124), at time T9, a parallel OE ₁₆ code corresponding to state S11 is received in register 64.

Regardless of the history of the generator of the pseudo-random sequence of bits of the descrambler 62, starting from the moment T9 (Fig. 9), this generator is synchronized with the generator 55 of the scrambler 54, in the sense that the bit sequences generated by both generators coincide. Undefined states and signals in the initial period when there was no code synchronization between the generators are marked with “X” in diagrams 125, 126, 127 and 129.

Starting from moment T9, the scrambling RND (diagram 114 in Fig. 8) and the descrambling RND * (diagram 126 in Fig. 9) the bit sequences coincide, therefore, the DIN signal (diagram 127) of the descrambled data coincides with the DATA signal (diagram 113) at the input 61 scramblers accurate to transmission delay. The output signal DATA * (diagram 129) of the data, "cleared" of possible multiple switching at the boundaries between bit intervals, is output to the descrambler 87 and is accompanied by a signal CLK *. Thus, the input signals DATA and CLK are converted into coincident (up to a transmission delay) output signals DATA * and CLK *.

The frequency of repetition of the moments of the synchronous installation of registers 58 and 64 in the same state (the moments of code synchronization) depends on the data transfer rate, as well as on the bit depth and the number K of codes CODE ₁ , CODE ₂ , ..., CODE _k recognized by decoders 73 and 82.

With K = 1 and a register width of 72 (81) equal to 8, in the scrambled data stream, on average, in each 256-bit chain, one sought code will be found, equal to CODE ₁ . With a data transfer rate of 10 Mbit / s, the average repetition rate of synchronization times is 10,000,000 / 256 = 39,062.5 Hz. At K = 4, the frequency of the synchronization moments increases four times and amounts to 156250 Hz.

To reduce the probability of false recognition of codes CODE ₁ , CODE ₂ , ..., CODE _{k by the} descrambler decoder 82, due to the receipt of 81 error bits from the communication line into the register, the bit capacity of this register (as well as register 72) can be increased, for example, to 20 bits .

Below is the operation of the device as a whole.

In the steady state, when zero signals are constantly present at the correction inputs 76 and 86 of blocks 69 and 78 (J = J * = 0), and the synchronization between the transmit and receive blocks 52 and 53 is previously achieved, the byte stream 130 (Fig. 10) from the inputs 70 of the device is transmitted over the communication line 51 in the form of a serial bit stream and then again converted into a stream of bytes 132 at the outputs 79. Moreover, due to the previously achieved synchronization, the receiving unit (more precisely, its firmware) “knows” the position of the boundaries between bytes 131 in the bit data stream transmitted over the line. This allows block 53 to correctly recover bytes 132.

Block 69 converting a parallel code into a serial one works according to the cyclic microprogram (Fig. 5, b), in accordance with which the following sequence of transitions between states is carried out: Z1 - Z2 - Z3 - ... - Z8 - Z1 - Z2, etc. During the execution of this microprogram, in each time interval of eight clock cycles (more precisely, in a clock cycle corresponding to state Z1), the outputs of ROM 91 generate signals Y0 and Y1, which are written to register 92 at the beginning of the next clock cycle as T × C and L signals arrive at points 71 and 96 (diagrams 145, 146, 151, 152 in FIG. 12).

On a positive edge of the T × C signal, a data source (not shown) sends another T × D byte to the device inputs 70 (diagram 147). For L = 1, on the positive edge of the CLK signal, the T × D byte is received in register 93, therefore, in the interval T1 - T2, the DATA signal (chart 148) reflects the state of the zero bit of the 93 bytes newly received in the register (byte bits are arbitrarily numbered from zero to seventh) . After scrambling (diagram 149) and passing through trigger 74 (diagram 150), the zero and subsequent bits are transmitted to line 51. At L = 0, bits 1-7 of the current byte are sequentially output from register 93, then at L = 1, the next byte is received and t .d.

Block 78 converting the serial code into parallel also works according to the cyclic microprogram (Fig.6, b), in accordance with which the following sequence of transitions between states is carried out: Z1 - Z2 - Z3- ... - Z8 - Z1 - Z2, etc. . During the execution of this microprogram in each time interval of eight clock cycles (more precisely, in a clock cycle corresponding to state Z8), the output of ROM 101 generates a signal V0 = 1, which is written to register 102 at the beginning of the next clock cycle and is transmitted as an R × C signal to point 80 (diagrams 185 and 186 in FIG. 14). By the moment of formation of the positive edges of the R × C signal, the next byte is formed at the data inputs of the register 103 (diagrams 174-181), which is stored in this register.

In the mode of correction of boundaries between bytes, synchronization signals J and J * are used, the origin of which was considered earlier. Recall that these signals are generated at previously unknown (random) time instants as a result of the detection of some given code combinations CODE ₁ , CODE ₂ , ..., CODE _k in the scrambled bit stream. It is noteworthy that the signals J and J * are generated in blocks 52 and 53 remote from each other at the same time (up to a transmission delay). This allows you to use them to synchronize the processes taking place in the device, in particular, to indicate the position of the boundaries between bytes in the bitstream data stream.

In the initial state, blocks 52 and 53 may or may not be synchronized with each other. In the situation shown in FIG. 11, these blocks are initially synchronized. The initial sequence of bytes 134 received from the inputs of the device 70 is transmitted over the communication line 51 in the form of a continuous bit stream in which bytes 135 are located. However, at the time of correction 136, blocks 52 and 53 simultaneously change the synchronization mode, i.e. transfer the origin of the boundaries between bytes to the same new point, in this example, offset from the old by four bits. At correction time 136, part 137 of the transmitted byte with conditional number i is ignored, after which it is retransmitted (byte 138). At the outputs 79 of the device, an output sequence of bytes 139 is formed that matches the input.

The signal J = 1 (Fig. 13, diagram 155) is delayed by the trigger 90 by half a clock cycle and is converted into the signal F (diagram 156), which, as the highest order bit of the address, is fed to the input of the ROM 91 and causes a transition to the lower half of the state table (Fig. 5b, state Z13), and then to states Z2, Z3, ..., Z8, Z1, Z2, etc. As a result, at time T21, the current byte is re-received into register 93 (diagram 160) and subsequently output to line 51. For subsequent recognition by block 53 of the fact that the boundaries between bytes are changed, it is essential that the time interval between the bit that generated the correction signal (in this example - bit number 1), and the retransmitted zero bit always amounts to two clock cycles CLK. Due to the fact that in state Z9, the same signals are generated at the outputs of ROM 91 as in state Z1, boundary correction is not performed when new boundaries correspond to old ones.

The serial to parallel conversion unit 78 receives the correction signal J * from input 86 and delays it by two clock cycles (diagrams 192, 205). The firmware (Fig.6, b) responds to the arrival of the signal A0 = 1 by switching to one of the states Z9 - Z16, in this example, to state Z13. Next, the sequential repeated loading of the byte into the register 98 (diagrams 197-204) begins, which ends half a cycle before the moment T25 of the formation of a positive edge of the R × C signal (diagram 209). At time T25, the byte generated at the new time boundaries is written to register 103 (diagram 210). After that, the device works in the new time reference system until the moment of receiving the next pair of correction pulses J and J * if they require shifting the boundaries between bytes. If correction is not required (the new byte boundary reference system is the same as the old), then the correcting pulses are ignored. Losses due to the retransmission of part of the byte are from zero to seven bit intervals against the background of the period between correction times, which can average, for example, 1 s.

In the initial state, the data receiving unit 53 may not be synchronized with the data transmitting unit 52. After receiving the first correcting impulse J * automatically (without using any software), code synchronization between the descrambler and the scrambler is achieved and a single frame of reference for byte boundaries when passing between blocks 52 and 53 is established.

The use of the proposed device can increase the data transfer rate due to two factors. The first factor is the exclusion from the data stream of a relatively large amount of overhead information designed to synchronize the operation of the descrambler with the scrambler, as well as the exclusion from the communication protocols of the corresponding software. The second factor is the reduction in the amount of redundant information sent in the data stream, indicating the boundaries between bytes.

Information sources

1. US Patent No. 5530959 (Fig. 1).

2. US Patent No. 5530959 (Fig. 5) (prototype).

Claims (3)

1. A device for transmitting data, comprising a data transmission unit and a data receiving unit connected to opposite sides of a communication line, a data transmission unit comprising a scrambler comprising a pseudo-random sequence of bits, a first exclusive OR element and a first amplifier, a pseudo-random sequence of bits contains a first shift register and the second exclusive-OR element, the inputs of which are connected to the outputs of the first shift register, and the output to the first input of the first exclusive-OR element and to the serial data input of the first shift register, the synchronization input of which is the scrambler synchronization input, the second input of the first exclusive-OR element is the scrambler data input, the output of the first amplifier is connected to the communication line, the data reception unit contains a descrambler containing a phase-locked oscillator, the second shift register, the third and fourth elements Exclusive OR and the second amplifier, the input of which is connected to the communication line, and the output to the input of the generator with phase-locked loop frequency, the output of which is the descrambler synchronization output, the outputs of the second shift register are connected to the inputs of the third exclusive-OR element, the output of which is connected to the first input of the fourth exclusive-OR element, characterized in that the data transfer unit further comprises a parallel to serial code conversion unit, group the data input of which is a group of device data inputs, and the byte synchronization output is the first output of the device byte synchronization, the scrambler It additionally contains a third shift register, a first decoder, a first trigger and a first inverter, the output of which is connected to the synchronization input of the first trigger, the input of the first inverter is connected to the synchronization inputs of the first and third shift registers, as well as to the bit synchronization output of the parallel code to serial conversion unit, the control input of the first shift register is connected to the output of the first decoder and to the correction input of the block converting the parallel code into serial, data output which is connected to the data input of the scrambler, the input of the serial data of the third shift register is connected to the output of the first XOR element and to the data input of the first trigger, the output of which is connected to the input of the first amplifier, the inputs of the parallel data of the first shift register are connected to the outputs of the first decoder, the inputs of which are connected with the outputs of the third shift register, the data receiving unit further comprises a unit for converting the serial code into parallel, a group of data outputs which the first is the group of device data outputs, and the byte synchronization output is the second byte synchronization output of the device, the descrambler additionally contains a fourth shift register, a second decoder, second and third triggers and a second inverter, the output of which is connected to the synchronization input of the second trigger and to the synchronization inputs of the second and fourth shift registers, the control input of the second shift register is connected to the output of the second decoder and to the correction input of the serial code conversion unit in parallel, the data input of which is connected to the output of the third trigger, and the input of bit synchronization is connected to the output of the descrambler synchronization, the input of serial data of the fourth shift register is connected to the second input of the fourth XOR element and to the output of the second trigger, the data input of which is connected to the output of the second amplifier , the inputs of the parallel data of the second shift register are connected to the outputs of the second decoder, the inputs of which are connected to the outputs of the fourth shift register, the input of the serial GOVERNMENTAL data of a second shift register connected to the first input of the fourth exclusive OR element whose output is connected to the data input of the third flip-flop, the clock input coupled to an output synchronizing descrambler and to the input of the second inverter. 2. The device for transmitting data according to claim 1, characterized in that the parallel-to-serial conversion unit contains a trigger, read-only memory, a parallel register, a shift register, a pulse generator and an inverter, the group of data inputs of the block is connected to the inputs of the parallel data of the shift register , the serial data output of which is the data output of the block, and the synchronization input is connected to the output of the pulse generator and the input of the inverter and is the output of the bit synchronization of the block, input d block correction is connected to the trigger data input, the synchronization input of which is connected to the inverter output and to the parallel register synchronization input, the outputs of which are connected to the shift register control input, the byte synchronization output of the block and the inputs of the memory address, the outputs of which are connected to the inputs parallel register data, the trigger output is connected to the input address of the read-only memory device. 3. The device for transmitting data according to claim 1, characterized in that the serial to parallel conversion unit comprises first and second shift registers, an inverter, read-only memory, first and second parallel registers, the data input of the second parallel register is connected to the data input of the first the shift register and is the input of the block data, the synchronization input of the first shift register is connected to the inverter input and is the bit synchronization input of the block, the data input of the second shift register and is the block correction input, the group of outputs of the second parallel register is the group of data outputs of the block, the synchronization input of the second parallel register is connected to the output of the first parallel register and is the byte synchronization output of the block, the inverter output is connected to the synchronization inputs of the second shift register and the first parallel register, outputs read-only memory devices are connected to the inputs of the first parallel register, and the address inputs are connected to the output of the second shift register and with outputs of the first parallel register.

Images