RU2179334C1 - Data retrieval device - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device is designed for data retrieval and identification in digital communication systems including networks for transmitting data on Frame Relay (FR) and High-Level Data Link Control (HLDLC) protocols standardized by International Electric Communications Union as well as for quality control of communication channel and control-based selection of FR or HDLC protocol in data transmission networks incorporating provision for identifying communication protocols FR and HDLC, controlling quality of data exchange using protocol FR or HDLC, and also for identifying change of protocol by remote station. Device has switches, registers, comparison unit, correction unit, retrieval strategy register, deciphering unit, and channel quality control unit. EFFECT: enlarged functional capabilities. 3 cl, 13 dwg

Description

 The invention relates to telecommunications and can be used to search for information and identification used in digital communication systems and, in particular, in data transmission networks (SPD) of communication protocols Frame Relay (FR) and High-Level Data Link Control (HDLC), standardized The International Telecommunication Union, as well as the quality control of the communication channel and the choice to work in the SPD, based on the control protocol FR or HDLC.

 A device for searching for information is known (see, for example, AS 1621049 USSR, IPC G 06 F 15/40, 1989) containing boundary registers that add up and subtract counters, comparison circuits, memory blocks, calculation blocks, and a number of other elements that allow you to search for information.

 A well-known analogue searches for information in a statistical way. However, this analogue has a drawback - a low probability of correct recognition, which limits its scope.

 A device for searching information (see, for example, RF patent N 2094845, IPC G 06 F 15/40, publ. 10/27/97), containing a switch, a shaper of reset signals, selection units, decoders, summing counters, search strategy register, block Indications that allow you to search for information.

 A well-known analogue searches for information only according to protocol rules. However, this analogue has a drawback. The known device has a low probability of correct recognition, which limits its scope.

 A device for searching information (see, for example, RF patent N 2100839, IPC G 06 F 15/40, publ. 12/27/97), containing a switch, a first, second and third register, a comparison unit, a correction unit, a search strategy register, decryption unit, allowing to search for information.

 A well-known analogue uses a syntactic method for recognizing communication protocols, which provides real-time decision making.

 The disadvantage of the analogue is the low reliability of the recognition of communication protocols, since the recognition of protocols is performed only on one element of the structure of data blocks - the control byte.

 The closest in technical essence to the claimed is a device for searching for information on the patent of the Russian Federation N 2133500, IPC G 06 F 15/40, publ. 07/20/98. A known information retrieval device consists of a first switch, a first register, a comparison unit, a correction block, a first search strategy register, a second register, a third register, a first decoder, a control signal generator, a second search strategy register, a fourth register, a fifth register, a second decoder, an encoder, a second switch, a selection unit, a timer unit, a third decoder, a fourth decoder, a third search strategy register, an indication unit.

 The clock input of the correction unit is connected to the clock inputs of the first register and the comparison unit and is the clock input of the information retrieval device. The information input of the first register is connected to the information inputs of the first switch and the correction unit and is the information input of the information retrieval device. The output of the first switch is connected to the information input of the third register.

 The first, second, third, fourth, fifth, sixth, seventh and eighth information outputs of the first register are connected to the corresponding information inputs of the comparison unit, the output of the comparison unit is connected to the control input of the first register of the search strategy. The output of the correction block is connected to the clock inputs of the first register of the search strategy and the third register. The output of the first register of the search strategy is connected to the input of the second register and the control input of the first decoder. The output of the second register is connected to the control input of the third register.

 The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth information outputs of the third register are connected to the corresponding information inputs of the first decoder, the first control output of the first decoder is connected to the sixth control input of the driver of control signals, and the second control output of the first decoder is connected to the fourth information input of the encoder. The first and second control inputs of the driver of the control signals are connected respectively to the output of the comparison unit and the output of the first register of the search strategy.

 The first and second control outputs of the control signal generator are connected respectively to the first and second control inputs of the first switch, and the third control output of the control signal generator is connected to the control input of the second search strategy register, the clock input of which is connected to the output of the correction block. The output of the second register of the search strategy is connected to the input of the fourth register, the control input of the second decoder and the third control input of the driver of control signals. The output of the fourth register is connected to the control input of the fifth register, the information input of the fifth register is connected to the output of the first switch, and the clock input of the fifth register is connected to the output of the correction block.

 The first, second, third, fourth, fifth, sixth, seventh and eighth information outputs of the fifth register are connected to the corresponding information inputs of the second decoder. The first and second information outputs of the second decoder are connected respectively to the fourth and fifth control inputs of the driver of the control signals, the third, fourth and fifth information outputs of the second decoder are connected respectively to the first, second and third information inputs of the encoder. The first, second and third information outputs of the encoder are connected to the corresponding information inputs of the second switch.

 The first, second and third information outputs of the second switch are connected to the corresponding information inputs of the selection block, the fourth, fifth and sixth information outputs of the second switch are connected respectively to the first, second and third information inputs of the fourth decoder. The first, second and third information outputs of the selection block are connected to the corresponding information inputs of the third decoder and the information outputs of the timer block, the input of which is connected to the control output of the selection block.

 The first control output of the third decoder is connected to the second control output of the fourth decoder, the output of the display unit and to the first control input of the third register of the search strategy. The second control output of the third decoder is connected to the second control input of the third register of the search strategy. The third control output of the third decoder is connected to the third control output of the fourth decoder and the second control input of the display unit. The first control output of the fourth decoder is connected to the first control input of the display unit. The first and second control outputs of the third register of the search strategy are connected respectively to the first and second control inputs of the second switch.

 Information retrieval device - the prototype uses as a feature both the structure of data blocks (frames) and the rules for exchanging them (protocol rules) during a data transfer session, providing increased recognition accuracy of the FR communication protocol.

 The disadvantage of the prototype is a narrow scope, because the known device allows you to identify only one type of protocol, in particular, the communication Protocol FR.

 The aim of the invention is to develop an information retrieval device that can be used in a wider field, in particular, for recognition of communication protocols FR and HDLC, quality control of data exchange carried out using the FR or HDLC protocol, as well as for identifying a protocol change by a remote station.

 This goal is achieved by the fact that in the known information search device containing a first switch, the first information output of which is connected to the information input of the third register, the control input of which is connected to the output of the second register, the control input of which is connected to the output of the search strategy register and the third control input of the first switch, information and clock inputs of the first register are connected respectively to the information and clock inputs of the correction unit and are simultaneously but the information and clock inputs of the device, the first, second, third, fourth, fifth, sixth, seventh, eighth outputs of the first register are connected to the corresponding information inputs of the comparison unit, the clock input of which is connected to the clock input of the correction unit, the information input of which is connected to the information input the first switch, the output of the comparison unit is connected to the control input of the search strategy register and the second control input of the first switch, the clock input of the third register is connected to ovym inputs search strategy register, second register and to the output correction unit is further introduced decoding unit, first and second quality channel control units, the second switch.

 The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth outputs of the third register are connected to the corresponding information inputs of the decryption unit. The first control input of the second switch is connected to the second control output of the decryption unit, the fourteenth, tenth, ninth information inputs of which are connected respectively to the first, second, third information inputs of the second switch, the second control input of which is connected to the output of the second register. The control input of the decryption unit is connected to the output of the search strategy register.

 The first and second control outputs of the second channel quality control unit are connected respectively to the first and fourth control inputs of the first switch. The control input of the second channel quality control unit is connected to the first control output of the decryption unit, the first and second information outputs of which are connected respectively to the information outputs of the second and first channel quality control units and are simultaneously the first and second information outputs of the device. The first, second, third outputs of the second switch are connected to the corresponding inputs of the first channel quality control unit. The second information output of the first switch is connected to the information input of the second channel quality control unit, the clock input of which is connected to the output of the correction unit.

 The decryption unit consists of a first decoder, the first and second outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first input of the trigger. The second trigger input is connected to the third output of the first decoder, which is simultaneously the first control output of the block. The control input of the first decoder is connected to the control input of the second decoder and is simultaneously the control input of the block. The first, second, third, fourth, fifth, sixth, seventh, eighth inputs of the first decoder are the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth information inputs of the block, respectively. The first, second, third, fourth, fifth, sixth, seventh, eighth inputs of the second decoder are respectively the first, second, third, fourth, fifth, sixth, seventh, eighth information inputs of the block. The output of the second decoder is the second control output of the block. The first and second outputs of the trigger are respectively the first and second information outputs of the block.

, управляющий вход счетчика искаженных кадров подключен ко второму выходу триггера. Первый выход триггера подключен к первому входу элемента исключающее

второй вход которого подключен к выходу коммутатора и первому информационному входу триггера. Информационный вход коммутатора является первым входом блока. Первый и второй входы элемента И-НЕ являются соответственно вторым и третьим входами блока. Выход дешифратора является информационным выходом блока.The first channel quality control unit consists of an NAND element, the output of which is connected to the control input of the switch, the trigger input of the trigger, the clock input of the counter of distorted frames, and the clock input of the frame counter. The output of the frame counter is connected to the second information input of the trigger and the control input of the decoder, N information inputs of which are connected to the N outputs of the counter of distorted frames. The information input of the counter of distorted frames is connected to the output of the element exclusive

, the control input of the counter of distorted frames is connected to the second output of the trigger. The first output of the trigger is connected to the first input of the element exclusive

the second input of which is connected to the output of the switch and the first information input of the trigger. The information input of the switch is the first input of the block. The first and second inputs of the AND element are, respectively, the second and third inputs of the block. The decoder output is the information output of the block.

 The second channel quality control unit consists of a first search strategy register, the first output of which is connected to the first output of the second search strategy register and is simultaneously the first control output of the block. The second output of the first register of the search strategy is connected to the control input of the first register, the second output of the second register of the search strategy, the control input of the decoder and is simultaneously the second control output of the block. The output of the first register is connected to the control input of the second register, the output of which is connected to the information input of the decoder, the second output of which is connected to the control input of the second register of the search strategy. The clock input of the first register of the search strategy is connected to the clock inputs of the first, second registers, the second register of the search strategy and is simultaneously the clock input of the block. The information input of the second register and the control input of the first register of the search strategy are respectively the information and control input of the block. The first output of the decoder is the information output of the block.

 Thanks to a new set of essential features, due to the introduction of a decryption unit, the first and second channel quality control units, and the second switch, recognition of the FR and HDLC protocols, quality control of the communication channel and selection based on the control of the FR or HDLC protocol, as well as identification of the protocol change by the remote station are provided. This achieves the possibility of using the claimed device in a wider field, in particular for operation in non-stationary communication channels.

 The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features that are identical to all the features of the claimed technical solution are absent, which indicates compliance of the claimed device with the patentability condition of "novelty". Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the impact provided by the essential features of the claimed invention transformations to achieve the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

The claimed device is illustrated by drawings, in which:
in FIG. 1 shows an electrical functional diagram of the proposed device;
in FIG. 2 is an electrical functional diagram of a decryption unit;
in FIG. 3 is an electrical functional diagram of a first channel quality control unit;
in FIG. 4 is an electrical functional diagram of a second channel quality control unit;
in FIG. 5 - a syntax recognition algorithm for the local control interface of the FR protocol with a synchronous-simplex control strategy on a constant dedicated channel;
in FIG. 6 - format of the information frame of the Protocol FR;
in FIG. 7 - format of the control frame "Status Request" Protocol FR;
in FIG. 8 - format of the control frame "Channel status, channel active" protocol FR;
in FIG. 9 - format of the control frame "Channel status, channel is inactive" FR protocol;
in FIG. 10 - event counters used to synchronize the control processes of the LMI FR protocol;
in FIG. 11 - time counters used to synchronize the control processes of the LMI FR protocol;
in FIG. 12 is an HDLC frame format;
in FIG. 13 is a structure of a frame management area of a main format of communication protocols of a subset of HDLC.

 The information retrieval device shown in FIG. 1, comprises a first switch 1, a first register 2, a comparison unit 3, a correction unit 4, a search strategy register 5, a second register 6, a third register 7, a decryption unit 8, a first channel 9 quality control unit, a second channel 10 quality control unit, second switch 11. The first information output of the first switch 1 is connected to the information input of the third register 7, the control input of which is connected to the output of the second register 6, the control input of which is connected to the output of the search strategy register 5 and the third control input of the first 1. mmutatora information and the clock inputs of the first register 2 are respectively connected to the information and the clock inputs of the correction block 4 and are both information and clock inputs. The first, second, third, fourth, fifth, sixth, seventh, eighth outputs of the first register 2 are connected to the corresponding information inputs of the comparison unit 3. The clock input of the comparison unit 3 is connected to the clock input of the correction unit 4, the information input of which is connected to the information input of the first switch 1. The output of the comparison unit 3 is connected to the control input of the search strategy register 5 and the second control input of the first switch 1. The clock input of the third register 7 is connected to the clock inputs of the strategy register by claim 5, second register 6 and to the output of correction block 4.

 The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth outputs of the third register 7 are connected to the corresponding information inputs of the decryption unit 8. The first control input of the second switch 11 connected to the second control output of the decryption unit 8, the fourteenth, tenth, ninth information inputs of which are connected respectively to the first, second, third information inputs of the second switch 11, the second the branching input of which is connected to the output of the second register 6. The control input of the decryption unit 8 is connected to the output of the search strategy register 5. The first and second control outputs of the second quality control block of channel 10 are connected respectively to the first and fourth control inputs of the first switch 1. The control input of the second block quality control channel 10 is connected to the first control output of the decryption unit 8, the first and second information outputs of which are connected respectively to the information outputs of the second 10 and the first 9 channel quality control blocks and are simultaneously the first and second information outputs of the device. The first, second, third outputs of the second switch 11 are connected to the corresponding inputs of the first quality control unit of channel 9. The second information output of the first switch 1 is connected to the information input of the second quality control unit of channel 10, the clock input of which is connected to the output of the correction unit 4.

 The decryption unit 8 shown in FIG. 4, is designed to connect the first 9 or second 10 channel quality control unit to the digital stream when exchanging data using the HDLC or FR protocol, respectively, as well as issuing a signal to the ZPD equipment of the local station to change the protocol when receiving the corresponding command from the remote station, consists of the first decoder 8.1, the second decoder 8.2, the element OR 8.3, trigger 8.4. The first and second outputs of the first decoder 8.1 are connected respectively to the first and second inputs of the OR element 8.3, the output of which is connected to the first input of trigger 8.4. The second input of trigger 8.4 is connected to the third output of the first decoder 8.1 and is simultaneously the first control output of block 8. The control input of the first decoder 8.1 is connected to the control input of the second decoder 8.2, which is also the control input of block 8.

 The first, second, third, fourth, fifth, sixth, seventh, eighth inputs of the first decoder 8.1 are respectively the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth information inputs of block 8. The first, second, third, fourth, fifth , sixth, seventh, eighth inputs of the second decoder 8.2 are respectively the first, second, third, fourth, fifth, sixth, seventh, eighth information inputs of block 8. The output of the second decoder 8.2 is the second control output of block 8. Pe vy and second outputs of the flip-flop 8.4 are respectively first and second data output unit 8.

9.4, счетчика искаженных кадров 9.5, счетчика кадров 9.6, схемы сравнения 9.7. Выход элемента И-НЕ 9.1 подключен к управляющему входу коммутатора 9.2, тактовому входу триггера 9.3, тактовому входу счетчика искаженных кадров 9.5, тактовому входу счетчика кадров 9.6. Выход счетчика кадров 9.6 подключен ко второму информационному входу триггера 9.3 и управляющему входу дешифратора 9.7, N информационных входов которого подключены к N выходам счетчика искаженных кадров 9.5.The first channel quality control unit 9 shown in FIG. 3, is designed to control the quality of the communication channel when operating the equipment of the HFA according to the HDLC protocol and issuing a signal to the equipment of the HPS of the local station to enter into communication by the FR protocol, for a given quality of the communication channel, consists of an AND-NOT 9.1 element, a switch 9.2, a trigger 9.3 , element exclusive

9.4, the counter of distorted frames 9.5, the counter of frames 9.6, the comparison scheme 9.7. The output of the AND-NOT element 9.1 is connected to the control input of the switch 9.2, the clock input of the trigger 9.3, the clock input of the counter of distorted frames 9.5, the clock input of the frame counter 9.6. The output of the frame counter 9.6 is connected to the second information input of the trigger 9.3 and the control input of the decoder 9.7, N information inputs of which are connected to the N outputs of the counter of distorted frames 9.5.

9.4, управляющий вход счетчика искаженных кадров 9.5 подключен ко второму выходу триггера 9.3. Первый выход триггера 9.3 подключен к первому входу элемента исключающей

9.4, второй вход которого подключен к выходу коммутатора 9.2 и первому информационному входу триггера 9.3. Информационный вход коммутатора 9.2 является первым входом блока 9. Первый и второй входы элемента И-НЕ 9.1 являются соответственно вторым и третьим входами блока 9. Выход дешифратора 9.7 является информационным выходом блока 9.The information input of the counter of distorted frames 9.5 is connected to the output of the element exclusive

9.4, the control input of the counter of distorted frames 9.5 is connected to the second output of trigger 9.3. The first output of trigger 9.3 is connected to the first input of the exclusive element

9.4, the second input of which is connected to the output of the switch 9.2 and the first information input of the trigger 9.3. The information input of the switch 9.2 is the first input of block 9. The first and second inputs of the NAND 9.1 element are the second and third inputs of block 9, respectively. The output of the decoder 9.7 is the information output of block 9.

 The second channel quality control unit 10 shown in FIG. 4, is designed to control the quality of the communication channel during the operation of the HW equipment using the FR protocol and issuing a signal to the HW equipment of the local station to enter into communication using the HDLC protocol when receiving the “Channel is not active” frame, consists of the first register of the search strategy 10.1, the first register 10.2 , second register 10.3, decoder 10.4, second register search strategy 10.5. The first output of the first register of search strategy 10.1 is connected to the first output of the second register of search strategy 10.5 and is simultaneously the first control output of block 10. The second output of the first register of search strategy 10.1 is connected to the control input of the first register 10.2, the second output of the second register of search strategy 10.5, control input decoder 10.4 and is simultaneously the second control output of block 10. The output of the first register 10.2 is connected to the control input of the second register 10.3, the output of which is connected to information Nome entry decoder 10.4, the second output of which is connected to the control input of the second register search strategy 10.5. The clock input of the first register of the search strategy 10.1 is connected to the clock inputs of the first 10.2, second 10.3 registers, the second register of the search strategy 10.5 and is simultaneously the clock input of block 10. The information input of the second register 10.3 and the control input of the first register of the search strategy 10.1 are respectively the information and control input block 10. The first output of the decoder 10.4 is the information output of block 10.

9.4 и триггера 9.3. Вариант построения коммутаторов представлен в книге Шило В.Л. Популярные цифровые микросхемы: Справочник. - М. : Радио и связь, 1987. - 352 с.: ил. - (Массовая радиобиблиотека. Вып. 1111) стр. 226, рис.2.27 и может быть реализован на микросхемах серии К555ИП7.The first switch 1 is for switching the input digital sequence to the input of the third register 7 and the second channel quality control unit 10. The second switch 11 is for switching the input digital sequence to the input of the first channel quality control unit 9. Switch 9.2 is designed for switching the input digital sequence to the input exclusive items

9.4 and trigger 9.3. A variant of the construction of switches is presented in the book Shilo V.L. Popular Digital Chips: A Guide. - M.: Radio and communications, 1987. - 352 p.: Ill. - (Mass Radio Library. Issue 1111) p. 226, Fig. 2.27 and can be implemented on the K555IP7 series microcircuits.

The first register 2 is for sequentially extracting eight elements of the input digital stream entering its information input, the search strategy register 5 is for delaying the control signal received at its control input by sixteen clock cycles, the first register of the search strategy 10.1 is for delaying the control signal, arriving at its control input, at fifty six and sixty four cycles, the second register of the search strategy 10.5 is designed to delay the control signal, the post ayuschego at its control input, twenty-four and thirty-two measures, the third register 7 for sequentially assigning sixteen elements of the input digital stream, the second register 10.3 is designed to sequentially release the eight elements of the input digital stream. Register schemes are known and described, for example, in a. from. 1591072 USSR, IPC ⁶ G 11 C 19/00, declared 11.23.88, publ. 09.09.90 and can be implemented on chips of the K555IR8 series.

 The comparison unit 3 is designed to determine the presence on its first to eighth information inputs of the code combination 01111110 corresponding to the “flag”. A variant of constructing a comparison block is presented in the book Shilo V.L. Popular digital microcircuits: Directory.-M .: Radio and communications, 1987. - 352 p. : ill. - (Mass Radio Library. Issue 1111) p. 273, fig. 2.68 and can be implemented on chips of the K555SP1 series.

 Correction block 4 is designed to detect and remove bits of "transparency" included in the digital sequence and at the transmitting station in order to prevent accidental occurrence of the combination corresponding to the "flag". An embodiment of the construction of the correction block is known and shown in FIG. 2 in RF Patent N 2100839 IPC G 06 F 15/40, publ. 12/27/97. In particular, such a scheme can be implemented on K555 series microcircuits.

 The second 6, the first 10.2 registers are identical and are designed to generate a control impulse to zero the contents of the cells of the third 7 and second 10.3 registers, respectively, after reading information from them. A variant of building registers is presented in the book Shilo V.L. Popular digital microcircuits: Handbook.-M.: Radio and communications, 1987. - 352 pp., Ill. - (Mass Radio Library. Issue 1111) p. 78, Fig. 1.57 and can be implemented on chips of the K555TM9 series.

 The first decoder 8.1 is designed to convert the octets "SABM" and "DM" within the HDLC frame (Fig. 13), the third octet of the local control channel (LMI) within the FR frame (Fig. 8.9), received from the third register 7, information about the presence of one of the three messages of the HDLC or FR protocols. The second decoder 8.2 is designed to convert the second octet within the frame of the HDLC (Fig. 12), received from the third register 7 into information about the operation of the hardware ZPD according to the HDLC protocol. A variant of the construction of decoders is known and described, for example, in the book by V. Shlyapobersky. Fundamentals of discrete messaging technology. - M .: Communication, 1973, p. 146, Fig. 3.36 and can be implemented on the K555ID7 series microcircuits.

 Element OR 8.3, element NAND 9.1 are intended for the logical isolation of signals between the inputs and outputs of microcircuits. Options for constructing elements OR, AND NOT known and described, for example, in the book B. Tarabrin Integrated Circuits: A Guide. - M .: Energoatomizdat, 1985, p. 282 and can be implemented, respectively, on the K555LL1, K555LA3 series microcircuits.

 Trigger 8.4 is designed to generate a control signal at the first or second output, depending on the control signal, respectively, at its first or second input. A variant of the construction of the trigger is presented in the book by Shilo V. L. Popular digital microcircuits: a Handbook. - M .: Radio and communications, 1987. - 352 p. : ill. - (Mass Radio Library. Issue 1111) p. 63, Fig. 1.42.

 Trigger 9.3 is designed to delay the input signal by one clock cycle. A variant of the construction of the trigger is presented in the book Shilo V.L. Popular Digital Chips: A Guide. - M.: Radio and communications, 1987. - 352 p.: Ill. - (Mass Radio Library. Issue 1111) p. 78, Fig. 1.57 and can be implemented on chips of the K555TM9 series.

9.4 предназначен для логической развязки сигналов между входами и выходами микросхем. Вариант построения элемента исключающее

представлен в книге Шило В.Л. Популярные цифровые микросхемы: Справочник. - М.: Радио и связь, 1987. - 352 с.: ил. - (Массовая радиобиблиотека. Вып. 1111) стр.57, рис. 1.35. Счетчик искаженных кадров 9.5 предназначен для подсчета числа перезапросов от удаленной станции.Exclusive element

9.4 is intended for the logical isolation of signals between the inputs and outputs of microcircuits. The option to build an element is exclusive

presented in the book Shilo V.L. Popular Digital Chips: A Guide. - M.: Radio and Communications, 1987. - 352 p.: Ill. - (Mass Radio Library. Issue 1111) p. 57, Fig. 1.35. The counter of distorted frames 9.5 is designed to count the number of retransmissions from a remote station.

The counter of distorted frames is a sequential register. Register schemes are known and described, for example, in A.S. 1591072 USSR, IPC ⁶ G 11 C 19/00, declared 11.23.88, publ. 09.09.90 and can be implemented on chips of the K555IR8 series.

 Frame counter 9.6 is designed to count the total number of information and supervisor HDLC frames, i.e. interval for monitoring the quality of the communication channel. A variant of the construction of the counter is presented in the book Shilo V.L. Popular Digital Chips: A Guide. - M.: Radio and Communications, 1987. - 352 p.: Ill. - (Mass radio library. Issue 1111) p. 94, fig. 1.69 and can be implemented on the K155IE8 series microcircuits.

 The decoder 9.7 is designed to convert information about the number of units at the outputs of the counter of distorted frames 9.5 into information about the quality of the communication channel. A variant of the construction of decoders is known and described, for example, in the book by V. Shlyapobersky. Fundamentals of discrete messaging technology. - M.: Communication, 1973, p. 146, Fig.3.36 and can be implemented on chips of the K555ID7 series.

 The decoder 10.4 is designed to convert the octets "Channel state information element identifier" and an octet indicating that the channel is "not active" (Fig. 9), received from the second register 10.3, respectively, into the control signal at the control input of the second strategy register search 10.5 and a control signal at the first information output of the information retrieval device. Variants of the construction of the decoder are known and described, for example, in the book by V. Shlyapobersky. Fundamentals of discrete messaging technology. - M.: Communication, 1973, p. 146, Fig. 3.36 and can be implemented on chips of the K555ID7 series.

 The device operates as follows.

 The information retrieval device is designed to recognize the communication protocols FR and HDLC, control the quality of data exchange carried out using the FR or HDLC protocol and provide a signal to the ZPD equipment of the local and remote stations about the use of one of two types of protocols depending on the signal-noise situation in the channel communication.

 The FR protocol was created to replace the HDLC protocol on high-speed communication channels. Like HDLC, it provides many independent virtual channels in one physical communication channel, but does not have the means of correction and recovery when errors occur. Therefore, with good quality of the communication channel, it is more expedient to work according to the FR protocol, providing a high data transfer rate, and when the quality of the channel is lower than the specified one, it is logical to switch to HDLC operation. If there are no redundant communication channels between the local and remote stations that can be used with poor quality in the working channel, the stations should include a device to determine the transition of the interacting station to work using the FR or HDLC protocol, as well as analyze the quality of the communication channel and initiate work according to one of the protocols depending on the state of the channel.

 Initially, the connection is carried out according to the FR protocol.

 The FR protocol does not provide for the transmission of signaling messages (no command (or supervisor) frames). For the transmission of service information, a specially dedicated control channel (Local Management Interface - LMI) is used, inside which supervisor frames are transmitted.

 In a recognizable protocol described in the book by D. A. Melnikov. Information processes in computer networks. Protocols, standards, interfaces, models. - M: KUDITS-IMAGE, 1999 .-- 256 p. on pages 146-165, three types of frames are used, one of which is transmitted from the user to the network, and two from the network to the user.

Actually, the algorithm of functioning of the local control interface of the FR protocol with the synchronous-simplex constant channel control (PVC) strategy is as follows (Fig. 5): the user sets the connection mode to the FR network by sending a message type "a" to the network ("Request state ") (Fig. 7), while the user from the initial state S ₁ switches to state S ₂ , if the network did not respond to the user within the time T391 (Fig. 11), then the user resumes the transmission of type" a "message, if the network after lane If a message of type “A” is sent to it, a message of type “C” is sent (“the channel is inactive) (Fig. 9), then the user repeats the transmission of a message of type“ A ”after a time interval T391. This process will be repeated until A message has been received about the availability of the channel, or it will not be canceled by the user.

If the channel is available, then the network transmits a message of type "B"("channelactive") (Fig. 8) and the user switches to information transfer mode (state S ₃ ), in which messages of type "i"("Informationframes" are transmitted) ) (Fig. 6). After a certain time interval (T391), the user stops transmitting information, returns to state S _1, and sends a type “a” message to the network in order to confirm the integrity of the connection, to which the network responds with type “B” messages containing the required element of communication integrity information.

 The LMI interface counts the number of polls. After a certain number of transmitted messages "a" (this interval has the international designation - N391 (Fig. 10)), the subscriber requests information about the so-called full state from the network, also using message "a".

 In case of errors, the FR network in the “Status” message sets the “active PVC” bit to “O”, thereby indicating the temporary unavailability of the channel (message type “B”). When the error is resolved, the network sets the “active PVC” bit to “1” (message type “c”). However, these network actions do not occur immediately when errors occur, but only when the set "threshold" is exceeded. This threshold is defined by the FR protocol and can be changed by the user. The network counts errors (the maximum value of this number has the international designation - N392) that occur within a specified period (this interval has the international designation - N393). If the interval N393 is exceeded, the N392 threshold is exceeded, then the network puts the channel in an inactive state. The way out of it is the network receives an error-free message of type "a".

 However, the FR standard does not introduce procedures on the basis of which it is unambiguously determined that the error situation has been eliminated and the subscriber can transmit messages of type "a". There is only one way to determine if a N392 event occurs without error.

 In some cases (deliberate interference with the communication channel), deadlocks may occur when the channel will be inactive for a long time. In this regard, it is more expedient when receiving a “c” type message from the network not to expect when the signal-noise situation in the communication channel changes, but to immediately switch to a more noise-resistant protocol (for example, HDLC), thereby reducing the response time of the equipment to changing environmental conditions.

 At the same time, when working with ZPD equipment using the HDLC protocol, described in the books Protocols of information and computer networks. Reference book./ Anichkin.S. A, Belov S. A., Bernstein A. A. et al. Ed. I.A. Mizina, A.P. Kuleshov. - M.: Radio and Communications, 1990.- 504 p. on pages 96-109; Melnikov D.A. Information processes in computer networks. Protocols, standards, interfaces, models. - M: KUDITS-IMAGE, 1999.- 256 p. on pages 47-51, 226-239, monitoring the status of the communication channel, you can switch to a higher-speed FR protocol when the quality of the channel is higher than the specified one (the number of errors for a certain interval).

Thus, the equipment should include devices allowing:
- identify the digital stream on its belonging to the FR or HDLC protocol (decryption unit 8);
- control the quality of the communication channel when operating under the FR or HDLC protocol (the first 9 and second 10 channel quality control blocks);
- according to the results of the monitoring (the first 9 and second 10 channel quality control blocks), as well as in the case of receiving the appropriate command from the remote station (decryption unit 8), issue a command to the ZPD equipment to transfer the equipment to work under the FR or HDLC protocol.

 The identification of communication protocols in the device is based on an analysis of the structure of data blocks (frames). A second octet of the input digital sequence can be used to identify the HDLC protocol. If the second octet corresponds to the octet shown in FIG. 12, a decision is made on whether the received frame belongs to the HDLC protocol, because the second octet of none of the types of FR protocol messages (Figs. 6,7,8,9) has an identical structure.

 It is possible to control the quality of the communication channel during operation using the HDLC protocol by the number of retransmissions from the remote station transmitted as part of the HDLC information and supervisor frames (Fig. 13). For this purpose, it is sufficient to compare the sixth bit of the third octet of the HDLC frame N-1 and the Nth frame. The appearance in a row of values 0 or 1 in the compared bits indicates a re-request from the remote station.

 The quality control of the communication channel when operating under the FR protocol is implemented on the basis of a number of counters (Fig. 10). Therefore, the quality control unit of the channel FR is sufficient in the received digital stream to identify the message LMI type "c" (Fig. 9).

 The connection of HDLC frames to the first quality control unit of channel 9, as well as the LMI channel to the second quality control unit of channel 10 is provided by decryption unit 8.

 Identification of a protocol change by a remote station is provided by received messages about entering into communication by a protocol different from the current one. Entering into communication using the HDLC protocol for duplex DDS operating in the AVM mode (most often used in practice) is performed using the SABM command, and in some cases with the DM command and then SABM (Fig. 13). Entering into communication via the FR protocol is carried out using the LMI channel.

 In the case of receiving a frame that does not correspond to the protocol currently used by the APD equipment, the frame is erased, however, the decryption unit 8 identifies the message data and issues a command about the transition of the APD equipment to another protocol.

The input signals for the information retrieval device (Fig. 1) are the digital signal sequence F _s and the clock signal F _t coming from the modem.

 The first switch 1 is intended for switching the input digital sequence to the input of the third register 7 and the second quality control unit of channel 10. When the control signal arrives at the second control input of the first switch 1, the input stream that goes to the information input of the first switch 1 is switched to its first information exit. When the control signal arrives at the third control input of the first switch 1, the information input of the first switch 1 is disconnected from its first information output. Upon receipt of the control signal at the first control input of the first switch 1, the input stream, coming to the information input of the first switch 1, is switched to its second information output. When the control signal arrives at the fourth control input of the first switch 1, the information input of the first switch 1 is disconnected from its second information output.

 The first register 2 is intended for the sequential allocation of eight elements of the input digital stream received at its information input.

The comparison unit 3 is designed to determine the presence on its first to eighth information inputs of the code combination 01111110 corresponding to the “flag”. In the case of a positive decision, a control signal is generated at the output of the comparison unit 3. Clock synchronization of the first register 2 and the comparison unit 3 is provided using F _t .

Correction block 4 is designed to detect and remove bits of "transparency" included in the digital sequence and at the transmitting station in order to prevent accidental occurrence of the combination corresponding to the "flag". This goal is achieved by removing from F _{t the} clock pulse corresponding to the bit "transparency". The adjusted F _ti coming from the output of the correction block 4 ensures clock synchronization of the operation of the first register of the search strategy 5, second 6 and third 7 registers, as well as the second channel quality control block 10.

The search strategy register 5 is designed to determine the time during which the bits of the input digital stream corresponding to the second and third octets within the FR or HDLC frame are located on the cells of the third register 7 and ensure frame synchronization of the operation of the decryption unit 8. The search strategy register 5 is sixteen-bit sequential register in which, upon receipt of a control pulse at its control input, 1 is recorded in the first cell and the contents of other cells are zeroed. The movement of the control pulse received from the comparison unit 3 is carried out under the influence of F _ti . After passing sixteen clock pulses F _{ti, the} control pulse appears at the output of the first register of the search strategy 5.

 The second register 6 is designed to generate a control pulse to zero the contents of the cells of the third register 7 after reading information from it. It is a D-trigger, the output of which the control signal is fed to the control input of the third register 7.

 The third register 7 is intended for the sequential allocation of sixteen elements of the input digital stream received at its information input. In the presence of a control pulse at the control input, the content of the cells of the third register 7 is reset.

 Decryption unit 8 is designed to connect the first 9 or second 10 channel quality control unit to the digital stream when exchanging data using the HDLC or FR protocol, respectively, as well as transmitting a signal to the ZPD equipment of the local station to change the protocol upon receipt of the corresponding command from the remote station.

 The first channel 9 quality control unit is designed to control the quality of the communication channel during operation of the HW equipment using the HDLC protocol and to issue a signal to the HW equipment of the local station to enter the communication using the FR protocol for a given quality of the communication channel.

 The second channel 10 quality control unit is designed to control the quality of the communication channel when the equipment of the HFA using the FR protocol is used and to issue a signal to the HEC equipment of the local station to enter into communication using the HDLC protocol when receiving the “Channel is not active” frame.

 The second switch 11 is intended for switching the fourteenth, tenth, ninth bits of the third octet of the input digital sequence to the input of the first quality control unit of channel 9. When the control signal is received at the first control input of the second switch 11 (operation via the HDLC protocol), the input stream arriving at the first, second and third information inputs of the second switch 11, respectively, to its first, second and third output. When the control signal arrives at the second control input of the second switch 11, the information inputs of the second switch 11 are disconnected from its information outputs.

 Decryption unit 8 (Fig. 2) works as follows.

 The first decoder 8.1 is designed to convert the octets "SABM" and "DM" within the HDLC frame (Fig. 13), the third octet of the local control channel (LMI) within the FR frame (Fig. 8.9), received from the third register 7, information about the presence of one of the three messages of the HDLC or FR protocols. The control signal appears at the first output of the first decoder 8.1 if the received sequence corresponds to the message "SABM" (00111111), at the second output, if the received sequence corresponds to the message "DM" (00011111), at the third output, if the received sequence corresponds to the channel LMI (00000001). The first decoder 8.1 is triggered when the control signal arrives from the output of the search strategy register 5.

 The second decoder 8.2 is designed to identify the operation of the hardware ZAP according to the HDLC protocol, by determining the belonging of the second octet of the received frame to the message "Address" within the HDLC frame (Fig. 12). A control signal at the output of the second decoder 8.2 will appear if the received sequence corresponds to the message "Address" (00000001). The second decoder 8.2 is triggered when the control signal arrives from the output of the search strategy register 5.

 A control signal at the output of the OR element 8.3 appears in the case of a control signal at its first or second input.

 Trigger 8.4 is designed to identify protocol changes by the ZPD equipment of the remote station. Trigger 8.4 initially has a high level at the second output (FR protocol operation). When a control signal arrives at the first input of trigger 8.4, the latter is triggered, and a high level will appear at its first output (command from a remote station to operate the APD equipment using the HDLC protocol.). When the control signal arrives at the second input of trigger 8.4, it is triggered, and a high level appears at its second output (command from the remote station to operate the APD equipment using the FR protocol).

 The first channel quality control unit 9 (Fig. 3) operates as follows.

 Element NAND 9.1 excludes from further analysis service (unnumbered) HDLC frames (Fig. 13) that do not contain information about the need for retransmission of frames.

9.4. При поступлении на управляющий вход коммутатора 9.2 управляющего сигнала осуществляется коммутация шестого бита третьего октета, поступающего на информационный вход коммутатора 9.2 к его выходу.Switch 9.2 is designed for switching the sixth bit of the third octet of an HDLC frame to the input of trigger 9.3 and an exclusive element

9.4. Upon receipt of the control signal at the control input of the switch 9.2, the sixth bit of the third octet is switched, which is fed to the information input of the switch 9.2 to its output.

 Trigger 9.3 is designed to delay the input digital sequence by one clock cycle. It is a D-trigger, from the first output of which a control signal is supplied to the first input of element 9.4. From the second output of trigger 9.3, the control signal is supplied to the control input of the counter of distorted frames 9.5 to reset the contents of its cells after reading information from the counter.

9.4 предназначен для сравнения значения шестого бита третьего октета предыдущего и принимаемого кадра HDLC. При совпадении уровня сигнала с коммутатора 9.2 и триггера 9.3 (запрос от удаленной станции на повторную передачу кадра) на выходе элемента исключающее

19.4 появится управляющий сигнал.Exclusive element

9.4 is intended to compare the values of the sixth bit of the third octet of the previous and received HDLC frame. If the signal level from switch 9.2 and trigger 9.3 coincide (request from the remote station for retransmission of the frame) at the element output, exclusive

19.4 a control signal appears.

9.4).The counter of distorted frames 9.5 is designed to count the number of retries from a remote station (the number of control signals at the output of the element is exclusive

9.4).

 Frame counter 9.6 is designed to count the total number of information and supervisor HDLC frames, i.e. interval for monitoring the quality of the communication channel.

 The decoder 9.7 is designed to convert information about the number of units at the outputs of the counter of distorted frames 9.5 into information about the quality of the communication channel. If the number of units (errors) does not exceed the selected threshold, then at the decoder output a control signal appears in the ZPD equipment of the local station for switching to operate according to the FR protocol. The operation of the decoder 9.7 is carried out at the time of the arrival of the control signal from the second output of trigger 9.3.

 The second block of quality control channel 10 (Fig. 4) works as follows.

The first register of the search strategy 10.1 is designed to determine the time during which the bits of the input digital stream corresponding to the eleventh octet (Figs. 11, 12) within the FR frame are located on the cells of the second register 10.3 and ensure frame synchronization of the operation of the decoder 10.4. The first register of the search strategy 10.1 is a sixty-four-bit sequential register, in which, upon receipt of a control pulse at its control input, 1 is recorded in the first cell and the contents of other cells are zeroed. The movement of the control pulse received from the decryption unit 8 is carried out under the influence of F _ti . After passing fifty-six clock pulses F _{ti, the} control pulse appears on the first output of the first register of the search strategy 10.1. After sixty four clock pulses F _{ti have} passed, the control pulse appears on the second output of the second register of the search strategy 10.1.

 The first register 10.2 is designed to generate a control pulse to zero the contents of the cells of the second register 10.3 after reading information from it. It is a D-trigger, from the output of which a control signal is supplied to the control input of the second register 10.3.

 The second register 10.3 is intended for the sequential allocation of eight elements of the input digital stream received at its information input. In the presence of a control pulse at the control input, the content of the cells of the second register 10.3 is reset.

 The decoder 10.4 is designed to convert the octet "Identifier of the information element about the state of the channel" and an octet indicating whether this channel is active or not (Fig. 8.9). The control signal appears on the first output of the decoder 10.4 if the received sequence corresponds to the message "channel is inactive" (1000-000) (Fig. 9), on the second control output, if the received sequence corresponds to the message "Channel element information element identifier "(01010111) (Fig. 8.9). The operation of the decoder 10.4 is carried out at the moment of arrival of the control signal from the second outputs of the first 10.1 or second 10.5 register search strategy.

The second register of the search strategy 10.5 is designed to determine the time during which the bits of the input digital stream corresponding to the fifteenth octet (FIG. 11, 12) within the FR frame are located on the cells of the second register 10.3 and ensure frame synchronization of the operation of the decoder 10.4. The second register of the search strategy 10.5 is a thirty-two-bit sequential register in which, upon receipt of a control pulse at its control input, 1 is written to the first cell and the contents of other cells are zeroed. The movement of the control pulse received from the decoder 10.4 is carried out under the influence of F _ti . After the passage of twenty-four clock pulses F _{ti, the} control pulse appears on the first output of the second register of the search strategy 10.5. After passing thirty-two clock pulses F _{ti, the} control pulse appears on the second output of the second register of the search strategy 10.5.

Claims (4)

 1. An information search device containing a first switch, the first information output of which is connected to the information input of the third register, the control input of which is connected to the output of the second register, the control input of which is connected to the output of the search strategy register and the third control input of the first switch, information and clock inputs the first register are connected respectively to the information and clock inputs of the correction unit and are both information and clock inputs of the devices , the first, second, third, fourth, fifth, sixth, seventh, eighth outputs of the first register are connected to the corresponding information inputs of the comparison unit, the clock input of which is connected to the clock input of the correction unit, the information input of which is connected to the information input of the first switch, the output of the comparison unit connected to the control input of the search strategy register and the second control input of the first switch, the clock input of the third register is connected to the clock inputs of the search strategy register, the second histra and to the output of the correction unit, characterized in that the decryption unit, the first and second channel quality control units, the second switch, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth are additionally introduced , thirteenth, fourteenth, fifteenth, sixteenth outputs of the third register are connected to the corresponding information inputs of the decryption unit, the first control input of the second switch is connected to the second control output of the decryption unit, fourteenth, the tenth, ninth information inputs of which are connected respectively to the first, second, third information inputs of the second switch, the second control input of which is connected to the output of the second register, the control input of the decryption unit is connected to the output of the search strategy register, the first and second control outputs of the second channel quality control block connected respectively to the first and fourth control inputs of the first switch, the control input of the second channel quality control unit is connected to the first the control output of the decryption unit, the first and second information outputs of which are connected respectively to the information outputs of the second and first channel quality control units and are simultaneously the first and second information outputs of the device, the first, second, third outputs of the second switch are connected to the corresponding inputs of the first channel quality control unit , the second information output of the first switch is connected to the information input of the second channel quality control unit, the clock input of which dklyuchen to the output correction unit.  2. The device according to p. 1, characterized in that the decryption unit consists of a first decoder, the first and second outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first input of the trigger, the second input of which is connected to the third output of the first of the decoder, which is simultaneously the first control output of the unit, the control input of the first decoder is connected to the control input of the second decoder and is simultaneously the control input of the unit, the first, second, third, even The third, fifth, sixth, seventh, eighth inputs of the first decoder are respectively the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth information inputs of the block, the first, second, third, fourth, fifth, sixth, seventh, eighth inputs of the second decoders are respectively the first, second, third, fourth, fifth, sixth, seventh, eighth information inputs of the block, the output of the second decoder is the second control output of the block, the first and second outputs of the trigger are I am the first and the second information unit outputs. 3. The device according to claim 1 or 2, characterized in that the first channel quality control unit consists of an NAND element, the output of which is connected to the control input of the switch, the trigger input, the clock input of the distorted frame counter, the clock input of the frame counter, output which is connected to the second information input of the trigger and the control input of the decoder, N information inputs of which are connected to N outputs of the counter of distorted frames, the information input of which is connected to the output of the element EXCLUSIVE

the control input of the counter of distorted frames is connected to the second output of the trigger, the first output of which is connected to the first input of the element EXCLUSIVE

the second input of which is connected to the output of the switch and the first information input of the trigger, the information input of the switch is the first input of the block, the first and second inputs are NAND elements, respectively, the second and third inputs of the block, the output of the decoder is the information output of the block.  4. The device according to claim 1 or 2, characterized in that the second channel quality control unit consists of a first search strategy register, the first output of which is connected to the first output of the second search strategy register and is simultaneously the first control output of the block, the second output of the first strategy register the search is connected to the control input of the first register, the second output of the second register of the search strategy, the control input of the decoder and is simultaneously the second control output of the block, the output of the first register is connected n to the control input of the second register, the output of which is connected to the information input of the decoder, the second output of which is connected to the control input of the second register of the search strategy, and the clock input of the first register of the search strategy is connected to the clock inputs of the first, second registers, the second register of the search strategy and is simultaneously the clock input of the block, the information input of the second register and the control input of the first register of the search strategy are respectively information and control inputs b eye, the first output of the decoder is the data output unit.

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