RU2033696C1 - Device for clock synchronization - Google Patents

Abstract

FIELD: electric communication. SUBSTANCE: device for clock synchronization has controlled frequency divider 1 which incorporates frequency divider 2 and controlling element 3, master generator 4, first storage 5, unit 6 of fast Fourier transform, adder 7, subtracter 8, switch 9, timer 10, second and third storages 11 and 12, signal converter 13 including unit 14 of fast Fourier transform and n correcting elements 15₁-15_n and signal extractor 16 composed of 2n storage cells 17₁-17₂ and switch 18. EFFECT: enhanced precision of clock synchronization. 1 dwg

Description

 The invention relates to telecommunication technology and can be used in discrete information transmission systems for clock synchronization.

 The aim of the invention is to improve the accuracy of clock synchronization.

 The drawing shows a structural electrical diagram of a clock synchronization device.

It contains a controlled frequency divider 1, which includes a frequency divider 2 and a control element 3, a master oscillator 4, a first memory unit 5, a fast Fourier transform (FFT) 6, adder 7, subtractor 8, switch 9, timer 10, and the second and a third memory blocks 11 and 12, a signal converter 13, comprising a FFT block 14 and n correction elements 15 ₁ -15 _n , and a signal extraction unit 16 containing 2n memory elements 17 ₁ -17 _2n and a switch 18.

 The clock device operates as follows.

 Using a controlled frequency divider 1, the moments of separation of samples from the received signal are determined. The decision to add or subtract the required number of pulses is made based on the clock error signal.

 To determine the clock synchronization signal, four samples are taken from each unit interval of the signal, while the IV sample in the steady state falls between unit intervals. Information about the clock error of the signal is taken from the I and III samples of the unit interval, and information about the belonging of the samples to this unit interval is taken from the II and IV samples.

 Using 4, 8, and 16 or 32 point FFT 6 blocks, the signals of the first samples, then the third, then the second and fourth samples of the corresponding unit intervals are converted for clock synchronization. The difference of the sum (without the carrier frequency signal) in the frequency domain of the first and third samples is supplied to the control element 3 of the controlled frequency divider 1. After summing (without carrier frequency) in adder 7, the sum from the first samples is entered into memory block 5. From this sum, the sum of third samples (the same without carrier frequency) is subtracted from subtractor 8 and the difference is passed through timer 10, memory blocks 11 and 12 are sent to control element 3. By analogy with the second and fourth samples.

The signal to the adder 7 can be supplied from the input (or from the output after entering into communication) of the correction elements 15 ₁ , 15 ₂ , 15 _n through the corresponding memory elements 17 ₁ , 17 ₂ , 17 _n (17 _{n + 1} , 17 _{n + 2} , 17 _2n ) and switch 18. When the signal converter 13 operates in the frequency domain, a synchronous detector is not required, since the carrier frequency from the signal can be excluded by the conversion block 13, i.e. the carrier frequency can be omitted from the input of the inverse fast Fourier transform block. In this case, the FFT 6 can be removed, since the necessary signal to the error signal allocation unit of the synchronization signal can be extracted from the output of the FFT 14 or from the outputs of the correction elements 15 ₁ , 15 ₂ , 15 _n .

Then, upon entering into communication, the signal is removed from the output of the FFT 14, and after entering into communication, the signal is removed from the outputs of the correction elements 15 ₁ , 15 ₂ , 15 _n , which allows to further increase the accuracy of synchronization, since the signal is removed from the outputs of the correction elements corrected. In this case, using the FFT unit 14, the error signal is first allocated for synchronization, and then the same signal samples using the FFT unit 14 are converted for input through the correction elements to the input of the FFT unit and then to the decision circuit.

 From the correction elements 15, the signals for block 7 and the signals for the corrector controller are recorded in the memory elements 17 in different cells.

Claims (1)

 A TACT SYNCHRONIZATION DEVICE comprising a fast Fourier transform (FFT) coupler in series, an adder, a first memory block, a subtractor, a switch and a timer, the outputs of which are connected to the inputs of the second and third memory blocks, the outputs of which are connected to the inputs of a controlled frequency divider, the input of which connected to the output of the master oscillator, the other output of the adder is connected to another input of the subtractor, characterized in that, in order to improve the accuracy of clock synchronization, it is introduced a signal converter, made in the form of an FFT block, the outputs of which are connected respectively to the inputs of n correction elements, and a signal extraction unit, made in the form of 2n memory elements, the outputs of which are connected to the corresponding inputs of the switch, while the signal input of the FFT block is connected to the signal input of the block FFT of the signal converter, the inputs and outputs of n correction elements of which are connected to the inputs of the corresponding 2n memory elements of the signal extraction unit, the output of the switch of which is connected to The appropriate input of the adder.