RU2029365C1 - Three-channel asynchronous system - Google Patents

Abstract

FIELD: automatics and computer engineering. SUBSTANCE: three-channel asynchronous system comprises three computing units, three units for forming failure signals, generator, three code converters, two trunk switching units, two groups of comparison units, three majority elements, five registers, two groups of registers, three counters, four flip-flops, three groups of AND gates, two groups of OR gates, seven one-shot multivibrators, decoder, three delay elements, fifteen OR gates, eighteen OR gates. The system is characterized in that the possibility of asynchronously performing control and computing algorithms realized according to different versions is provided, rapid tracking of the "pace" and correctness of performance of problems by channels and rejection on this basis of failed channels are carried out, furthermore the possibility of recovery of the state of computing units after failure, the possibility of obtaining reliable solution at two non-crossing failures or failure of one of the the computing units and the operation in a single-channel configuration are provided. EFFECT: enhanced reliability, widened operating capabilities. 6 dwg, 3 tbl

Description

 The invention relates to automation and computer technology and can be used to build fault-tolerant control and computer systems in which redundant channels operate asynchronously due to an alternative implementation of task execution algorithms.

 The aim of the invention is to expand the scope of the system.

 The essence of the invention is to provide the possibility of asynchronous execution of control or computational algorithms implemented in various versions (alternatives), operational tracking of the pace and correct execution of tasks by channels and rejection of failed channels on this basis, the possibility of restoring the state of computing units after failures, the possibility of the system working in single-channel configuration, obtaining the correct solution by the system when two computing units fail (failures that do not completely intersect) and when e one computing unit at the failed one or two computing units.

 Figure 1, 2 and 3 shows a functional diagram of a three-channel asynchronous system; figure 4 is a functional diagram of a computing unit; figure 5 is a functional diagram of a block generating fault signals; figure 6 is a timing diagram of the system when disjoint failure of two computing units in the second mode.

), первый 70, второй 71 и третий 72 управляющие входы вычислительного блока 1. i(i =

), третью группу информационных входов 73 вычислительного блока 1. i(i =

), первый 74, второй 75, третий 76, четвертый 77 и пятый 78 сигнальные выходы вычислительного блока 1.i(i =

), вторую группу информационных выходов 79.i. 1-79.i.4 вычислительного блока 1.i(i =

), информационные входы-выходы 80, сигнальный вход 81, первую группу информационных выходов 82 вычислительного блока 1.i(i =

), шестой вход 83 блока 2.i(i =

) формирования сигналов отказа пятый одновибратор 84, четвертый вход 85 блока 2. i(i =

) формирования сигналов отказа, первый 86, третий 87 и вторые 88 информационные выходы блока 2.i(i =

) формирования сигналов отказа, первый 89 и второй 90 установочные входы режима работы системы, выход 91 отказа системы, вход 92 запуска системы, первый сигнальный режимный выход 93 системы, выходы 94.1-94.4 элементов И 65.1-65.3 и элемента ИЛИ 67, информационный выход 95 системы, выход 96 достоверности информации системы, вход 97 начальной загрузки системы, второй сигнальный выход 98 системы.The three-channel asynchronous system (FIGS. 2 and 3) contains computing blocks 1.1-1.3, failure signal generation blocks 2.1-2.3, a generator 3, a first code converter 4, a first trunk switch 5, a first group of comparison blocks 6.1-6.3, a second trunk switch 7, second 8, first 9 and third 10 majority elements, third 11 and fourth 12 registers, first group of registers 13.1-13.3, fifth register 14, second 15 and third 16 counters, fourth 17, third 18 and first 19 triggers, fourth 20, fifth 21, seventh 22 elements AND, the second group of registers 23.1-23.3, WTO I am grouping the group of comparison blocks 24.1-24.3, the third group of elements AND 25.1-25.3, the thirteenth 26, the fourteenth 27, the sixteenth 28, the fifteenth 29, the tenth 30, the eleventh 31, the twelfth 32, the ninth 33 and the eighth 34 elements AND, the first group of elements OR 35.1 -35.3, third OR element 36, second trigger 37, twelfth OR element 38, first group of AND elements 39.1-39.3, fourth OR element 40, seventh 41, fifteenth 42, fifth 43 and eleventh 44 OR elements, fourth 45, first 46, seventh 47, sixth 48 and third 49 single vibrators, third delay element 50, thirteenth OR 51, air the eleventh element And 52, the first counter 53, the decoder 54, the second code converter 55, the second group of elements OR 56.1-56.3, the ninth element OR 57, the seventeenth element And 58, the sixth element And 59, the tenth element OR 60, the second delay element 61, the eighth OR element 62, second one-shot 63, first delay element 64, second group of AND elements 65.1-65.3, third code converter 66, fourteenth 67 and sixth 68 OR elements, control output 69 of computing unit 1. i (i =

), the first 70, second 71 and third 72 control inputs of the computing unit 1. i (i =

), the third group of information inputs 73 of computing unit 1. i (i =

), first 74, second 75, third 76, fourth 77 and fifth 78 signal outputs of the computing unit 1.i (i =

), the second group of information outputs 79.i. 1-79.i.4 computing unit 1.i (i =

), information inputs-outputs 80, signal input 81, the first group of information outputs 82 of computing unit 1.i (i =

), the sixth input 83 of block 2.i (i =

) failure signal generation fifth one-shot 84, fourth input 85 of block 2. i (i =

) the formation of failure signals, the first 86, third 87 and second 88 information outputs of block 2.i (i =

) the formation of fault signals, the first 89 and second 90 installation inputs of the system operation mode, output 91 of the system failure, input 92 of the system start, the first signal mode output 93 of the system, outputs 94.1-94.4 of the elements AND 65.1-65.3 and the element OR 67, information output 95 system output 96 system information reliability, input 97 system boot, the second signal output 98 of the system.

) (фиг.4) содержит таймер 99, микропроцессор 100, первый 101 и второй 102 параллельные программируемые адаптеры, контроллер 103 прерываний, память 104, элементы И 105, 106 и 107, одновибраторы 108, 109 и 110.Computing block diagram 1.i (i =

) (Fig. 4) contains a timer 99, microprocessor 100, first 101 and second 102 parallel programmable adapters, interrupt controller 103, memory 104, AND elements 105, 106, and 107, single vibrators 108, 109, and 110.

) формирования сигналов отказа (фиг.5) содержит счетчик 111, первый 112, второй 113 и третий 114 триггеры, первый 115 и второй 116 элементы И, элемент ИЛИ 117.Block Diagram 2.i (i =

) the formation of failure signals (Fig. 5) contains a counter 111, first 112, second 113 and third 114 triggers, first 115 and second 116 elements AND, element OR 117.

 The purpose of the elements of a three-channel asynchronous system.

) предназначены для решения задач пользователя.Computing blocks 1.i (i =

) are intended to solve user problems.

) формирования сигналов отказа предназначены для формирования сигнала тестирования вычислительного блока 1.i, если число последовательных сбоев вычислительного блока 1.i превысило число n (порог счетчика 111), и фиксирования сигнала отказа вычислительного блока 1.i, если его тест прошел неуспешно.Blocks 2. i (i =

) failure signal generation are designed to generate a test signal for computing unit 1.i if the number of consecutive failures of computing unit 1.i has exceeded the number n (counter threshold 111), and to fix the failure signal of computing unit 1.i if its test failed.

Generator 3 is designed to issue two sequences of clock pulses τ ₁ and τ ₂ from outputs 3.1 and 3.2, respectively. Clock Period
T = T ₁ + T ₂ , where T ₁ is the time between the clock pulse τ ₁ from output 3.1 and the clock pulse τ ₂ from output 3.2, which exceeds the time of transients on the main switch 7, comparison blocks 6.1-6.3, elements I 25.1-25.3, 26, 27, 30, majority element 10, trigger 19, OR element 67, code converter 66;
T ₂ is the time between the clock pulse τ ₂ from output 3.2 and the clock pulse τ ₁ from output 3.1.

 The generator 3 has a control input 92, a single signal at the control input 92 turns on the generator 3, the zero signal turns off.

 The first code converter 4 is designed to issue sets of control signals to the trunk switch 5 in order to control the movement of information flows and to select the majorization function of the trunk switch depending on the set of input control signals. In the table. 1 shows the correspondence between the input and output sets of the code converter 4.

) с шиной DO магистрального коммутатора 5. В качестве магистрального коммутатора 5 можно использовать микросхему К 583 ХЛ1.The first backbone switch 5 is designed to perform the function of bitwise majorization of information of inputs and outputs 80.1-80.3 and return information to inputs and outputs 80.1-80.3 in the recovery mode and perform the function of bi-directional movement of information of inputs and outputs 80.i (i =

) with the DO bus of the main switch 5. As the main switch 5, you can use the chip K 583 HL1.

) cравнения предназначен для поразрядного сравнения информации на его входах. Если информация сравнилась, то на выходе появляется нулевой сигнал, в противном случае - единичный.Block 6.i (i =

) comparisons are intended for bitwise comparison of information at its inputs. If the information is compared, then a zero signal appears at the output, otherwise, a single signal.

), либо для соединения выхода решения системы с выходом одного из вычислительных блоков 1. i(i =

). В качестве магистрального коммутатора 7 можно использовать микросхему К 583 ХЛ1.The second backbone switch 7 is designed either to majorize the information issued by the computing units 1.i (i =

), or to connect the output of the solution to the system with the output of one of the computing units 1. i (i =

) As the main switch 7, you can use the chip K 583 HL1.

 The second 8, first 9 and third 10 majority elements are designed to majorize comparison signals of sequential solutions of computing blocks 1.1-1.3, failure of computing blocks 1.1-1.3 and reliable comparison of information at the channel output with the outputs of the majority element block, respectively. They perform the function "2 of 3".

нулевой сигнал, то входы регистра находятся в высокоимпедансном состоянии, если единичный сигнал, то выходы регистра в высокоимпедансном состоянии. Регистр состоит из D-триггеров, у которых синхровходы и входы

объединены.The third register 11 is intended for fixing signals of readiness of the decision of each computing unit 1.1-1.3. The register consists of D-flip-flops, in which the sync inputs and R-inputs are combined. The fourth register 12 is designed to capture information from the bus of the main switch 5 and to provide information to the bus of the main switch 5. The inputs and outputs of the register can be in a high impedance state. If at the entrance

zero signal, then the register inputs are in a high impedance state, if a single signal, then the register outputs are in a high impedance state. The register consists of D-flip-flops that have sync inputs and inputs

combined.

 The first group of registers 13.1-13.3 is intended for fixing information from the outputs of computing blocks 1.1-1.3. The outputs of the registers 13.1-13.3 can be in a high impedance state when a zero signal is applied to the input of the EO registers 13.1-13.3. Each register consists of D-flip-flops with combined V-inputs, EO-inputs and sync inputs.

 The fifth register 14 is intended for fixing reliable information for solving a problem by computing units 1.1-1.3 and consists of D-flip-flops with integrated clock inputs.

 The second counter 15 is intended for fixing the signal of non-comparison of solutions at the outputs of computing blocks 1.1-1.3. If after the arrival of the readiness signal for solving a problem of one of the computing units, the information reliability signal was not generated by the majority element 10 in a time equal to the passage of n clock pulses from the output 3.2 of the generator 3, then the counter 15 is blocked and generates an enable signal to the V-input of the counter 53. The third counter 16 it is intended for issuing a signal for channel recovery, if for a time equal to the passage of K clock pulses from the output 3.2 of the generator 3, from the moment the signal of reliability of the information is received, the signal 96 m, that the problem is solved from the lagging channel. Counter 16 is cyclic.

 The fourth trigger 17 is an RS-trigger for setting the operating mode of the system and can be set to a single or zero state using external inputs 89 and 90, respectively. If the trigger 17 is set to a single state, then the system operates using the channel recovery mode, if in the zero state - without using the channel recovery mode. In the RS flip-flop 17, the R-input has an advantage over the S-input. The third trigger 18 is an RS-trigger and is designed to control the And 20. element. The trigger is set to a single state when an impulse is sent to restore channels and is reset if all three channels gave signals that they are ready to load a new task. The first trigger 19 is an IK trigger and is designed to fix the signal of information reliability at the output 96 until the next task is loaded.

) формирования сигналов отказа не выдал сигнал на тестирование одного из вычислительных блоков 1.1-1.3.The fourth element And 20 is designed to transmit a pulse to test three computing units, if during the time set for the restoration of channels, signals are not issued by serviceable channels about readiness for loading (thereby trigger 18 is reset). The fifth element And 21 is designed to synchronize the issuance of information by computing units 1.1-1.3 to the inputs of the main switch 5 and control the operation of the register 12. The seventh element And 22 is designed to transmit a pulse to restore the computing units, if one of the blocks 2.i (i =

) the formation of failure signals did not give a signal for testing one of the computing units 1.1-1.3.

-вход регистров единичного сигнала. Каждый регистр состоит из D-триггеров с объединенными V-входами,

-входами и синхровходами.The second group of registers 23.1-23.3 is intended for fixing information from the outputs of computing blocks 1.1-1.3. The output registers 23.1-23.3 may be in a high impedance state when applied to

- input registers of a single signal. Each register consists of D-flip-flops with combined V-inputs,

- inputs and sync inputs.

) cравнения предназначен для поразрядного сравнения информации на его входах. Если информация сравнилась, то на выходе нулевый сигнал, в противном случае единичный.Block 24. i (i =

) comparisons are intended for bitwise comparison of information at its inputs. If the information is compared, then the output is zero signal, otherwise a single one.

 The third group of elements I 25.1-25.3 is intended for generating information comparison signals from the outputs of the corresponding registers 13.1-13.3 (23.1-23.3) with the DO outputs of the main switch 7 if a signal is ready for the decision of this processor and it is working.

The thirteenth element And 26 is designed to generate a signal that all the computing units 1.1-1.3 issued signals of readiness for solution. The fourteenth element And 27 is designed to generate a signal that the information was compared at the outputs of three computing units. The sixteenth element And 28 is designed to generate a channel recovery signal if the information at the output of one of the channels did not coincide with the information at the output of the remaining channels. The fifteenth element And 29 is designed to skip clock pulses from the output 3.2 of the generator 3 to the counting input of the counter 15, if there is a ready signal for solving one of the computing units and there is no signal of reliability of information from the output of the OR 67 element. The tenth element And 30 is designed to skip the clock pulses τ ₂ s output 3.2 of generator 3 to the R-input of counter 15, if a signal of information reliability came from the output of OR 67. Eleventh element And 31 is used to skip clock pulses from output 3.2 of generator 3 to the counting input of the count ika 16 if system operation mode is set to the restoration (flip-flop 17 is set to one state), a signal reliability of the information at the output latch 19 and no signal readiness solutions from all channels. The twelfth element And 32 is designed to skip clock pulses from the output 3.2 of the generator 3 to the R-input of the counter 16, if the operating mode of the system with recovery is set (trigger 17 is set to a single state) and there are decision ready signals from all computing blocks 1.1-1.3. The ninth AND 33 element is designed to generate a task loading signal immediately when an information reliability signal appears at the output of the OR 67 element if the mode without recovery of channels is set (i.e., trigger 17 is set to zero). The eighth element And 34 is designed to generate a load signal of the task in the recovery mode if the solution of a delayed computing unit coincides with the solution of the remaining computing units.

 The first group of elements OR 35.1-35.3 is intended for supplying to the inputs 70.1-70.3 testing, respectively, of the computing blocks 1.1-1.3 test signals of the computing blocks 1.1-1.3. The third element OR 36 is designed to generate a test signal of one of the computing units 1.1-1.3.

) либо для фиксирования факта отказа двух вычислительных блоков. Триггер имеет два R-входа, объединенных функцией И, и два S-входа, объединенных функцией И. В RS-триггере 37 R-входы имеют преимущество над S-входами.The second trigger 37 is an RS-trigger and is designed to record the fact of testing one or two processors in case of failure of at least one computing unit 1.i (i =

) or to record the fact of failure of two computing units. The trigger has two R-inputs combined by the And function, and two S-inputs combined by the I. function. In the RS flip-flop 37, the R-inputs take precedence over the S-inputs.

 The twelfth element OR 38 is designed to generate a mode setting signal with restoration upon successful completion of testing of computing units 1.1-1.3 or with an external installation by applying a single signal to input 89.

), если не сравнились последовательные решения данным вычислительным блоком одной и той же задачи.The first group of elements And 39.1-39.3 is designed to generate a test signal of the computing unit 1.i (i =

) if consecutive solutions by the given computing unit of the same problem were not compared.

 The fourth element OR 40 is designed to generate a signal to set the operating mode of the system without recovery when testing one of the computing units 1.1-1.3, the failure of at least one of the computing units 1.1-1.3, or when the mode is set externally by applying a single signal to the input 90. The seventh element OR 41 is designed to control the register 12. The fifteenth element OR 42 is designed to generate a signal of readiness for solving at least one of the computing units. The fifth element of OR 43 sets the trigger 37 to a single state in case of failure of two of the computing units 1.1-1.3 or testing at least one of the computing units 1.1-1.3. The eleventh element OR 44 is designed to form a combined signal load computing units 1.1-1.3.

 The fourth one-shot 45 is designed to generate a test signal of the computing units 1.1-1.3, if the recovery process failed. The first one-shot 46 is designed to generate a short recovery signal of the computing units 1.1-1.3. The seventh one-shot 47 is designed to form a time interval during which the process of restoring the computing units 1.1-1.3 during its normal passage should be reliably completed. The sixth one-shot 48 is designed to form a time interval exceeding the transients on the element And 115, the counter 111, the element OR 36. The one-shot 48 has two triggering inputs. The third one-shot 49 is designed to generate a load signal of the task.

 The third delay element 50 is designed to delay the reset of the signal of information reliability at the output 96 of the system.

 The thirteenth OR element 51 is designed to generate a failure signal of at least one of the computing units 1.1-1.3, enables the trigger 37 and sets the trigger 17 to zero (i.e., the mode without restoring the state of the channels).

 The eighteenth element And 52 is designed to generate a system failure signal at the output 91 in the event of a failure of all computing units 1.1-1.3.

 The first counter 53 is cyclic, designed to count the control pulses from the output 3.2 of the generator 3 after the counter 15 is blocked, that is, the solutions of the computing blocks 1.1-1.3 did not match. It has two R-inputs combined by an OR function, and a V-input enable counter.

 Decoder 54 is designed to distribute control pulses.

 The second code converter 55 is intended for generating a task loading signal after testing or restoring computing units 1.1-1.3. In the table. 2 shows the correspondence between the input and output sets of the code converter 55.

 The second group of OR elements 56.1-56.3 is intended to form a high-impedance state of the output of the group of registers 13.1-13.3 or the group of registers 23.1-23.3.

 The ninth element OR 57 is designed to combine the three control signals.

) при работе системы с одним вычислительным блоком. Шестой элемент И 59 предназначен для третьего запуска задачи при несравнении двух предыдущих решений при работе системы с одним вычислительным блоком.The seventeenth element And 58 is intended to organize the comparison of sequential solutions of computing unit 1.i (i =

) when the system operates with one computing unit. The sixth element And 59 is intended for the third task launch when two previous solutions are not compared when the system works with one computing unit.

 The tenth element OR 60 is designed to generate a signal that gates the state of the blocks 24.1-24.3 comparison.

 The second delay element 61 is designed to delay the signal, the gate state of the comparison blocks 24.1-24.3, for a time longer than transients on the OR elements 56.1-56.3, the group of registers 13.1-13.3 (23.1-23.3) and the comparison blocks 24.1-24.3.

 The eighth element OR 62 is designed to form a combined task reload signal.

 The second one-shot 63 is designed to generate a pulse signal reloading tasks.

 The first delay element 64 is designed to delay the gating signal for a time longer than transients on the OR element 60, the delay element 61 and the group of elements AND 65.1-65.3.

 The second group of elements And 65.1-65.3 is intended for gating the moments of comparing successive solutions with intact computing units 1.1-1.3 of the same task.

 The third code converter 66 is designed to issue sets of control signals to the backbone switch 7 in order to operate as a majority element or multiprexor, depending on the set of input control signals. Table 3 shows the correspondence between the input and output sets of the code converter 66.

 The fourteenth element OR 67 is intended to generate a signal for the appearance of reliable information for solving the problem. The sixth element OR 68 is designed to combine control signals that reset the counter 15.

) является выходом сигнализации того, что за время, назначенное для решения данной задачи, вычислительный блок 1.i не выдал сигнала готовности решения данной задачи.The control output 69 of the computing unit 1.i (i =

) is the alarm output that, during the time assigned to solve this problem, the computing unit 1.i did not give a signal of readiness to solve this problem.

) является входом тестирования вычислительного блока 1.i. Второй управляющий вход 71 вычислительного блока 1. i(i =

) является входом восстановления вычислительного блока 1.i. Третий управляющий вход 72 вычислительного блока 1. i(i =

) является входом загрузки вычислительного блока 1.i задачей.The first control input 70 of the computing unit 1.i (i =

) is the input of testing the computing unit 1.i. The second control input 71 of the computing unit 1. i (i =

) is the input of the recovery of the computing unit 1.i. The third control input 72 of the computing unit 1. i (i =

) is the input of the computational unit 1.i loading.

) предназначена для ввода информации в вычислительный блок 1.i.The third group of inputs 73 of the computing unit 1.i (i =

) is intended to enter information into the computing unit 1.i.

)предназначен для выдачи импульсного сигнала успешного завершения тестирования вычислительного блока 1.i. Второй сигнальный выход 75 вычислительного блока 1.i(i =

) предназначен для выдачи импульсного сигнала неуспешного завершения тестирования вычислительного блока 1.i. Третий сигнальный выход 76 вычислительного блока 1.i(i =

)предназначен для выдачи сигнала о том, что неисправно оборудование для восстановления вычислительных блоков 1.1-1.3 во время тестирования вычислительного блока 1.i. Четвертый сигнальный выход 77 вычислительного блока 1.i(i =

) предназначен для выдачи сигнала разрешения загрузки задачи в данный вычислительный блок после тестирования или восстановления. Пятый сигнальный выход 78 вычислительного блока 1. i(i =

) предназначен для выдачи сигнала решения задачи данным вычислительным блоком 1.i.The first signal output 74 of the computing unit 1.i (i =

) is intended for issuing a pulse signal for successful completion of testing of computing unit 1.i. The second signal output 75 of the computing unit 1.i (i =

) is intended for issuing a pulse signal of unsuccessful completion of testing of computing unit 1.i. The third signal output 76 of the computing unit 1.i (i =

) is intended to give a signal that the equipment for restoring computing units 1.1-1.3 is faulty during testing of computing unit 1.i. The fourth signal output 77 of the computing unit 1.i (i =

) is intended for issuing a permission signal for loading a task into a given computing unit after testing or recovery. The fifth signal output 78 of the computing unit 1. i (i =

) is intended to provide a signal for solving the problem by this computing unit 1.i.

) вычислительного блока 1.i(i =

) предназначена для выдачи информации управления оборудованию восстановления вычислительных блоков 1.1-1.3 и взаимодействия между вычислительными блоками 1.1-1.3: выход 79.i.1 предназначен для управления состоянием шин магистрального коммутатора 5 и выполнения магистральным коммутатором 5 функции мажоритирования информации; выход 79.i,2 предназначен для управления направлением передачи информации коммутатора 5 и регистра 12; выход 79.i.3 предназначен для указания двум другим вычислительным блокам, что данный вычислительный блок тестирует оборудование восстановления; выход 79. i.4 предназначен для управления направлением передачи информации при тестировании вычислительным блоком оборудования восстановления.The second group of information outputs 79.i (i =

) computing unit 1.i (i =

) is intended for the issuance of control information for the recovery equipment of computing units 1.1-1.3 and the interaction between the computing units 1.1-1.3: output 79.i.1 is designed to control the state of the buses of the main switch 5 and perform the main switch 5 functions of majorization of information; output 79.i, 2 is designed to control the direction of transmission of information of the switch 5 and the register 12; output 79.i.3 is intended to indicate to two other computing units that the given computing unit is testing recovery equipment; output 79. i.4 is designed to control the direction of information transfer during testing by the computing unit of recovery equipment.

 Inputs-outputs 80 are designed to exchange information with recovery equipment. The signal input 81 is intended to receive feedback that the register 12 and the backbone switch 5 are prepared to write information to the register 12. The first group of outputs 82 is designed to provide a solution to the problem by computing units 1.1-1.3.

) формирования сигналов отказа является входом разрешения записи информации в триггер 113 и счетчик 111.Sixth information input 83 of block 2.i (i =

) the formation of failure signals is the input enable recording information to the trigger 113 and the counter 111.

 The fifth one-shot 84 is designed to generate a load signal for a new task at the end of the channel recovery process.

) формирования сигналов отказа является входом поступления сигнала сбоя решения от данного вычислительного блока 1.i.The fourth information input 85 of block 2.i (i =

) the formation of fault signals is the input of the decision failure signal from the given computing unit 1.i.

) формирования сигналов отказа является внешним выходом неисправности соответствующего вычислительного блока 1.i. Третий выход 87 блока 2.i(i =

) формирования сигналов отказа является внешним выходом неисправности оборудования восстановления, проверяемого данным вычислительным блоком 1.i. Второй выход 88 блока 2.i(i =

) формирования сигналов отказа предназначен для формирования сигнала тестирования вычислительного блока 1.i, если у него произошло подряд n сбоев.The first output 86 of block 2.i (i =

) the formation of fault signals is an external fault output of the corresponding computing unit 1.i. Third output 87 of block 2.i (i =

) the formation of failure signals is an external output of the malfunction of the recovery equipment verified by this computing unit 1.i. Second output 88 of block 2.i (i =

) the formation of failure signals is intended to generate a testing signal of the computing unit 1.i if it has successively n failures.

 The first installation input 89 of the three-channel asynchronous system is the installation input of the second system operation mode with channel recovery. The second installation input 90 of the three-channel asynchronous system is the installation input of the first mode of operation of the system without channel recovery.

 The output 91 of the failure of the three-channel asynchronous system is the output signaling the failure of the device.

 Input 92 start three-channel asynchronous system is the input enable clock 3.

 The first signal mode output 93 of the three-channel asynchronous system is designed to generate a signal to reload the task. The outputs 94.1-94.4 of the group of elements AND 65.1-65.3 and the element OR 67 are outputs for comparing information of sequential solutions of problems and output of the appearance of reliable information of the solution, respectively. The group of information outputs 95 of the three-channel asynchronous system is designed to provide information for solving the problem. The output 96 of the reliability of the solution of the three-channel asynchronous system is designed to issue a signal of reliability of information at the output 95.

 A three-channel asynchronous system boot input 97 is a task boot input. The second signal mode output 98 of the three-channel asynchronous system signals that the computing units can be loaded with another task.

) предназначен для формирования импульса тестирования вычислительного блока 1.i, если задача решается больше отведенного ей времени решения (записывается до решения задачи в таймер 99), т.е. нет сигнала готовности решения задачи. В качестве таймера можно использовать, например, ИМС КР 580 ВИ 53.The timer 99 of the computing unit 1.i (i =

) is intended to generate a testing impulse for computing unit 1.i if the problem is solved more than the time allotted to it (it is recorded in timer 99 before solving the problem), i.e. there is no signal of readiness for solving the problem. As a timer, you can use, for example, IC KR 580 VI 53.

) предназначен для непосредственной обработки информации. В качестве микропроцессора можно использовать, например, ИМС КР580 ИК80А.The microprocessor 100 of the computing unit 1.i (i =

) is intended for direct processing of information. As a microprocessor, you can use, for example, IC KR580 IK80A.

 The first 101 and second 102 parallel programmable adapters are used to exchange information of the microprocessor 100 with external devices. As a parallel programmable adapter can be used, for example, IC KR580 BB55.

 The interrupt controller 103 is designed to process three interrupt requests: for testing, restoring, and loading computing units. The highest priority is the request for testing, the lowest request to download the task. As an interrupt controller, you can use, for example, IC KR580 VN59.

 The memory 104 consists of RAM and ROM. The ROM contains interrupt handling programs for testing computing units and external recovery equipment, for recovering computing units 1.1-1.3, and for loading a task into computing units 1.1-1.3.

) предназначен для формирования сигнала успешного окончания тестирования данного вычислительного блока 1.i. Второй элемент И 106 вычислительного блока 1.i(i =

) предназначен для формирования сигнала неуспешного окончания тестирования данного вычислительного блока 1. i. Третий элемент И 107 вычислительного блока 1.i(i =

) предназначен для формирования сигнала управления направлением передачи информации регистра 12 и магистрального коммутатора 5 при тестировании данным вычислительным блоком оборудования восстановления.The first element And 105 of the computing unit 1.i (i =

) is intended to generate a signal of successful completion of testing of this computing unit 1.i. The second element And 106 of the computing unit 1.i (i =

) is intended to generate a signal of unsuccessful completion of testing of this computing unit 1. i. The third element And 107 computing unit 1.i (i =

) is designed to generate a control signal for the direction of information transfer of the register 12 and the backbone switch 5 when tested by the recovery unit with this computing unit.

)предназначен для задания максимального интервала времени, в течение которого процесс успешного тестирования должен достоверно закончиться. Одновибратор 108 имеет два входа запуска. Второй одновибратор 109 вычислительного блока 1.i(i =

) предназначен для формирования импульсного сигнала по окончании времени достоверного окончания тестирования, из которого формируется либо сигнал успешного завершения тестирования вычислительного блока 1.i, либо неуспешного завершения тестирования. Третий одновибратор 110 вычислительного блока 1.i(i =

) предназначен для формирования короткого импульса сброса второго адаптера 102. Он имеет два запускающих входа.The first one-shot 108 of the computing unit 1.i (i =

) is intended to set the maximum time interval during which the process of successful testing should reliably end. The single vibrator 108 has two trigger inputs. The second one-shot 109 of the computing unit 1.i (i =

) is intended to generate a pulse signal at the end of the time of a reliable completion of testing, from which either a signal of successful completion of testing of computing unit 1.i or of unsuccessful completion of testing is generated. The third one-shot 110 of the computing unit 1.i (i =

) is intended to form a short reset pulse of the second adapter 102. It has two triggering inputs.

) формирования сигналов отказа предназначен для подсчета числа последовательных сбоев вычислительного блока 1.i и, если их число превышает порог счетчика 111 (n), то счетчик блокируется и формируется сигнал на тестирование данного вычислительного блока 1.i.Block 111 counter 2.i (i =

) the formation of failure signals is designed to count the number of consecutive failures of the computing unit 1.i and, if their number exceeds the threshold of the counter 111 (n), the counter is blocked and a signal is generated for testing this computing unit 1.i.

)формирования сигналов отказа является D-триггером с разрешающим V-входом и предназначен для сохранения сигнала сбоя данного вычислительного блока 1.i при решении предыдущей задачи. Третий триггер 114 блока 2.i(i =

)формирования сигналов отказа является IK-триггером и предназначен для фиксирования сигнала отказа данного вычислительного блока 1.i.The first flip-flop 112 is an IK-flip-flop and is designed to record the failure signal of the recovery equipment being tested by this computing unit. Second trigger 113 of block 2.i (i =

) the formation of failure signals is a D-flip-flop with an enabling V-input and is designed to save the failure signal of this computing unit 1.i when solving the previous problem. Third trigger 114 of block 2.i (i =

) the formation of failure signals is an IK-trigger and is designed to fix the failure signal of this computing unit 1.i.

) формирования сигналов отказа предназначен для пропускания синхроимпульсов на счетный вход счетчика 111, если решили задачи все вычислительные блоки 1.1-1.3 и у данного вычислительного блока 1.i произошел сбой при решении этой и прошлой задач. Второй элемент И 116 блока 2.i(i =

) формирования сигналов отказа предназначен для пропускания синхроимпульса на сброс счетчика 111, если при решении данной задачи у вычислительного блока 1.i не было сбоев и счетчик 111 не заблокировался.The first element And 115 block 2.i (i =

) the formation of failure signals is designed to transmit clock pulses to the counting input of the counter 111, if all the computing units 1.1-1.3 have solved the problems and this computing unit 1.i has failed to solve this and past problems. The second element And 116 block 2.i (i =

) the generation of failure signals is designed to pass a clock pulse to reset counter 111, if, when solving this problem, computing unit 1.i had no failures and counter 111 was not blocked.

 The OR element 117 of the failure signal generation unit is intended to generate a reset signal of the counter 111.

 Three-channel system operates as follows.

 In the initial state, computing units 1.1-1.3 are in standby mode for loading a task, registers 11, 12, 13.1-13.3, 14, 23.1-23.3, counters 15, 16, 53, 111, triggers 17, 18, 19, 92, 94 are in the zero state, trigger 37 is in the single state. The chains of setting registers 11, 12, 13.1-13.3, 14, 23.1-23.3, counters 15, 16, 53, 111 and triggers to the initial state are not shown.

 The operation of a three-channel asynchronous system begins with the inclusion of a generator of 3 clock pulses when a single signal is input to 92. The system can operate in two main modes: without restoring the computing units 1.1-1.3 (trigger 17 of the mode in the zero state) and restoring the state of the computing blocks 1.1-1.3 (trigger 17 of the mode in the single state).

 The system can work in the second mode only in the three-channel version, and in the first mode in the three-channel version (according to the user installation, failure of the recovery equipment, or when testing one or two channels), in the two-channel version (when one channel fails) and in the single-channel version (when failure of two channels). In the mode with restoration of the state of computing units 1.1-1.3, the system can operate in a submode of recovery of a failure of a task from one of the computing units 1.1-1.3. In both modes, the system can operate in a sub-mode of testing computing blocks 1.1-1.3 (one, two, or three).

 The mode of operation of the system with the restoration of the state of the computing units 1.1-1.3 is set by applying a single signal to the input 89 of the system when the trigger 17 is translated into a single state.

) начинает решать задачу. Одновременно сигнал загрузки запускает одновибратор 110, который формирует короткий импульс, достоверно сбрасывающий адаптер 102. Поскольку вычислительные блоки 1.1-1.3 решают одну и ту же задачу, но по различным алгоритмам, то время их решения не может быть одинаковым. Пусть, например, первым решил задачу вычислительный блок 1.1 и выставил на своем выходе 70.1 единичный сигнал того, что задачи данным вычислительным блоком решены, сбрасывающий таймер 99. Сигналы готовности решения всех вычислительных блоков фиксируются в регистре 11 и результаты решения фиксируются в регистрах 23.1-23.3 по синхроимпульсам с выхода 3.1 генератора 3, так как на V-входы регистров 23.1-23.3 подан единичный сигнал с первого выхода дешифратора 54.To boot the system, an impulse is fed to input 97, which passes through the OR element 44 and starts the one-shot 49. The latter generates a pulse passing through the OR 62 element and starts the one-shot 63, which generates a pulse received at the inputs 72 of the computing units 1.1-1.3, which are the inputs of the controller 103 interrupt download tasks. According to the download signal, the microprocessor 100 interrupts and starts receiving information about the task from the group of information inputs 73, working on a program stored in the ROM. At the end of the information input, the timer 99 loads the time limit for solving this problem (transmitted along with the task information) and the timer starts, after which the computing unit 1.i (i =

) begins to solve the problem. At the same time, the load signal is triggered by a single-shot 110, which generates a short pulse, reliably resetting the adapter 102. Since the computing units 1.1-1.3 solve the same problem, but using different algorithms, the time for their solution cannot be the same. Suppose, for example, that computing unit 1.1 was the first to solve the problem and set out at its output 70.1 a single signal that the tasks were solved by this computing unit, resetting timer 99. Ready signals for the solution of all computing units are recorded in register 11 and the results of the solution are recorded in registers 23.1-23.3 clock pulses from the output 3.1 of the generator 3, since the V-inputs of the registers 23.1-23.3 filed a single signal from the first output of the decoder 54.

 From the output of register 11, a single signal of readiness for solving a computing unit 1.1 is supplied to the direct input of the AND 25.1 element, passes through the OR 42 element, and arrives at the first input of the And 29 element. Since the computing units 1.2 and 1.3 have not yet solved the problem, as a result, the And 25.2 and 25.3 are closed, then at the output of the majority element 10 there is a zero signal and, since the elements AND 65.1-65.3 are closed, then at the output of the element OR 67 there is a zero signal, which, arriving at the inverse input of the element And 29, opens it for passing synchronization pulses from output 3 , 2 gene Rathore 3 to the count input of the counter 15. The counter threshold 15 depends on the maximum time difference for solving the problems of computational units 1.1-1.3. Elements And 65.1-65.3 are closed, so the code converter 66 forms a control combination that tunes the main switch 7 to the majority information from the buses D1, D2 and D3 and its output to the bus D0.

 If the problem was solved, for example, by computing unit 1.2 until the counter 15 was blocked, then when the decision information on the D0 bus of the backbone switch 7 coincides with the information of the registers 23.1-23.2, comparison blocks 6.1-6.2 generate zero signals and, since the computing blocks 1.1-1.3 are operational, then the elements AND 25.1-25.2 form single signals and at the output of the majority element 10 a single signal of information reliability is formed, which passes through the OR element 67 and opens the And 30 element, as a result of which the next clock pulse with the output and 3.2 of generator 3 passes through the AND element 30, sets the trigger 19 to a single state and, passing through the OR element 68, zeroes the counter 15. Information on the solution of the problem is written to the register front on the leading edge of the unit signal 14, and the solution to the problem is output at system output 95, followed by a single signal at the output 96 of the reliability of the information.

).In the second mode, the And 33 element is locked, and the And 31 and 32 elements are unlocked, since there is a single signal at the output of the trigger 17 of the mode. Until the signal is ready for the decision of the computing unit 1.3 at the output of the And 26 element, a zero signal that opens the And 31 element and closes the And 32 element. Thus, the clock pulses from the output 3.2 of the generator 3 pass through the And 31 element and arrive at the counting input of the counter 16, the threshold To which is determined by the maximum waiting time for the arrival of the signal of readiness to solve the last lagging computing unit 1.i (i =

)

 If the decision ready signal for the lagging computing unit 1.3 arrives earlier than this time, then a single signal appears on the output of the And 26 element, which closes the And 31 element and opens the And 32 element. As a result, the next clock goes through the And 32 element, resets the counter 16 and, if the solution of the lagging computing unit 1.3 coincided with the solution of the remaining computing units, then a single signal appears at the output of the And 27 element, which closes the And 28 element and opens And 34. The clock from the output of And 32 passes through the AND element 34 and the OR element 44 and launches the one-shot 49, which generates a load signal for the next task.

 If the solution of the last deciding computing unit 1.3 does not coincide with the solution of the other two computing units, then at the output of the comparison unit 6.3 there remains a single signal that closes the And 25.3 element, resulting in a zero signal at the output of the And 27 element, which opens And 28 and closes element And 34. As a result, the clock pulse from the output of the element And 32 passes through the element And 28 and starts the single-shot 48 on the leading edge.

 If, when solving the previous problem, the computing unit 1.3 had a failure, then this is reflected by the zero state of the trigger 113 of the failure signal generation unit 2.3. Since the input 83 of the failure signal generation unit 2.3 contains a single signal from the output of the And 26 element, and its input 85 has a zero signal, since the And 25.3 element is closed, the next clock goes through the And 115 element and increases the counter state 111 on the rising edge per unit, at the trailing edge of this clock pulse, a zero signal is recorded in trigger 113 (i.e., in this problem, computing unit 1.3 is lost). Thus, only consecutive failures of the computing units are recorded in the counter 111. In blocks 2 for generating failure signals of failed computing blocks, the clock passes through the AND 116 and OR 117 elements and resets the corresponding counter 111 to the zero state.

 If the lagging computing unit 1.3 did not give a ready signal in the time determined by the threshold of the counter 16, then a single signal appears at the output of the counter 16, along the leading edge of which the one-shot 48 is triggered. The pulse duration of the one-shot 48 exceeds the transients on the I 115, counter 111, element OR 36.

-вход единичный сигнал и закрывая элемент И 116, и выдает на выход 88 блока 2.i(i =

) формирования сигналов отказа единичный сигнал, который проходит через элемент ИЛИ 36, закрывая элемент И 22, тем самым не пропуская сигнал на восстановление вычислительных блоков 1.1-1.3, проходит через элемент ИЛИ 40 и устанавливает триггер 17 режима в нулевое состояние (т.е. первый режим), а также проходит через соответствующий элемент ИЛИ 35. i и поступает на вход 70 тестирования вычислительного блока 1.i.If one of the counters 111 has reached its threshold, then it will self-lock, applying to

-input a single signal and closing the element And 116, and gives the output 88 of the block 2.i (i =

) of the formation of failure signals, a single signal that passes through the OR element 36, closing the AND element 22, thereby not passing the signal to restore the computing units 1.1-1.3, passes through the OR element 40 and sets the mode trigger 17 to the zero state (i.e. the first mode), and also passes through the corresponding element OR 35. i and enters the input 70 of the testing of the computing unit 1.i.

 Since the output of the OR element 67 is a single signal, after the trigger 17 is set to the zero state, the And 33 element opens and the next clock pulse from the output 3.2 of the generator 3 passes through the And 30 and 33 elements, the OR element 44 and starts the one-shot 49, which generates a load signal next task. Two computing units begin to load and complete the task, and the third computing unit 1.i begins to be tested, since the test request has a higher priority.

-вход регистра 12, переводя его в режим приема информации, и на вход 81 вычислительного блока 1.i. Считав единицу с входа 81, вычислительный блок 1.i выставляет значение на шине 80. i и выставляет единичное значение на выходе 79.i.1, по которому кодопреобразователь 4 формирует сигналы управления магистральным коммутатором 5 так, что значение с шины 80.i попадет на вход регистра 12. После этого на выводе 79. i. 2 направления передачи устанавливается нулевой сигнал, по заднему фронту сигнала значение записывается в регистр 12 и направление передачи меняется на обратное. Вычислительный блок считывает значение с шины 80.i и сравнивает посланное и полученное значения.We describe the testing process of one computing unit 1.i. From the output 70, the signal is fed to the interrupt request input of the interrupt controller 103 and, on a rising edge, starts the one-shots 108 and 110. The one-shot 108 generates a pulse whose duration exceeds the testing time of the computing unit 1.i. The single-vibrator 110 generates a short reset pulse of the adapter 102. Upon request for testing, the microprocessor 100 switches to the testing routine located in memory 104, during which the microprocessor tests itself, interrupt controller 103, memory 104, adapters 101 and 102, and recovery equipment. The microprocessor 100 tests the recovery equipment as follows: passes several values one after the other through the main switch 5 and writes it to register 12, then reads the values and compares them with the original ones. The algorithm for testing the recovery equipment is as follows: the microprocessor 100 through the adapter 102 outputs single signals at the outputs 79.i.2 and 79.i.3, through which the And 107 element generates a single signal 79.i.4, which passes through the OR 41 to the sync input and

-input of the register 12, translating it into the mode of receiving information, and at the input 81 of the computing unit 1.i. After reading the unit from input 81, the computing unit 1.i sets the value on the bus 80. i and sets the unit value at the output 79.i.1, by which the code converter 4 generates control signals for the main switch 5 so that the value from the bus 80.i to the input of the register 12. After that, at the conclusion 79. i. 2 of the transmission direction, a zero signal is set, along the trailing edge of the signal, the value is recorded in register 12 and the transmission direction is reversed. The computing unit reads the value from the bus 80.i and compares the sent and received values.

 If the testing of the computing unit was successful, then a single signal is set at the second output of channel C, otherwise, nothing is set at the output of adapter 102 after it is reset.

 If the testing of the computing unit 1.i was successful, then in the case of unsuccessful testing of the recovery equipment, a single signal is set at the third output of channel C. After the successful testing of the computing unit 1.i at the fourth output of channel C of the adapter 102, a single signal to enable the download of the task is set.

 At the end of the maximum testing time, the single-shot 109 starts at the trailing edge of the pulse generated by the single-shot 108. If the test of the computing unit 1.i and the recovery equipment was successful, the pulse from the output of the single-shot 109 passes through the element 105 of the successful completion of the test and from the output of the 74 computational of block 1.i goes to the input of block 2. i of the formation of failure signals, which passes through the OR element 117 and resets the counter 111. The signal from the output 74 of computing block 1. i also passes through the OR element 38 and sets the trigger 17 of the mode in a single state, passing into the mode with the restoration of the computing units.

 If the test of the computing unit 1.i is successful, and there is no recovery equipment, then the counter 111 of the failure signal generation unit 2.i is reset, and the system operation mode remains the same, i.e. without restoring the channels, since in this case a single signal from the output of the computing unit 76 passes to the input of the failure signal generating unit 2.i, is recorded in the trigger 112 and from the output 87 of the unit passes through the OR element 40 to the R-input of the trigger 17. Since The R-input of the trigger 17 has the advantage, then no signals supplied to the S-input of the trigger 17, do not change its state.

 If testing of the computing unit 1.i is unsuccessful, then the pulse from the output of the one-shot 109 passes through the And element 106 and from the output 75 of the computing unit 1.i is fed to the input of the failure signal generating unit 2.i, is recorded in the trigger 114 and from the output of the 86 unit closes AND elements 25.i, 65.i, passes through OR elements 51, 40 and enters the R-input of trigger 17, preventing it from switching to a single state.

 Upon completion of successful testing of the computing unit 1.i, the microprocessor 100 clears the request register of the interrupt controller 103 and the computing unit 1.i starts the execution of the next task.

 If none of the counters 111 of the failure signal generation block reaches its threshold, then at the output of the OR 36 element there is a zero signal that opens the And 22 element. The one-shot 47 generates a pulse whose duration exceeds the maximum duration of the recovery process.

 The pulse from the output of the single vibrator 47 sets the trigger 18 to a single state and, on the leading edge, starts the single vibrator 46, which generates a short pulse that is input to the input 71 of the computing units 1.1-1.3. Upon these requests, the microprocessor 100 of the computing units 1.1-1.3 switches to the recovery routine. Recovery mode algorithm.

-вход и синхровход регистра 12 и на входы 81 вычислительных блоков 1.1-1.3. После появления единичных сигналов на входах 81 вычислительных блоков 1.1-1.3 вычислительные блоки 1.1-1.3 выставляют значение на шине 80, которое нужно восстановить, после этого все вычислительные блоки выдают сигнал 79.i.1, при появлении которого кодопреобразователь 4 формирует сигнал управления магистральным коммутатором 5 так, что он выполняет функцию мажоритирования информации с входов D1, D2, D3 на выход D0. После этого вычислительные блоки 1.1-1.3 меняют сигнал 79.i.2 направления на нулевой. По заднему фронту сигнала мажоритированный байт записывается в регистр 12, направление передачи меняется на обратное и мажоритированный байт с выхода регистра 12 проходит через магистральный коммутатор 5 на шины 80 вычислительных блоков 1.1-1.3. Процесс восстановления одного байта повторяется столько раз, сколько байтов нужно для дальнейшего решения задачи.Computing blocks 1.1-1.3 at the outputs 79.i.2 of the transmission direction set single signals. After all the computing units have set signals, the output of the AND 21 element is set to a single signal, which passes through the OR element 41 and is fed to

-input and sync input of the register 12 and the inputs 81 of the computing units 1.1-1.3. After the appearance of single signals at the inputs of 81 computing blocks 1.1-1.3, computing blocks 1.1-1.3 set the value on bus 80, which needs to be restored, after that all computing blocks give a signal 79.i.1, when it appears, the code converter 4 generates a control signal for the main switch 5 so that it performs the function of majorizing information from inputs D1, D2, D3 to output D0. After that, the computing units 1.1-1.3 change the signal 79.i.2 direction to zero. On the trailing edge of the signal, the majorized byte is recorded in register 12, the direction of transmission is reversed and the majorized byte from the output of register 12 passes through the main switch 5 to the bus 80 of the computing units 1.1-1.3. The process of recovering one byte is repeated as many times as many bytes are needed to further solve the problem.

 At the end of the recovery process, the computing units set out at the outputs 77 a single task load resolution signal, in the presence of which the code converter 55 generates a single signal. It resets the trigger 18, triggers the one-shot 84 at the output edge of the trigger 18, the pulse from the output of which passes through the OR element 44 and starts the one-shot 49, which generates a load pulse for the next task.

 If any of the computational units 1.1-1.3 did not set a single signal at the output 77 and there is no signal that the computational unit is faulty, then trigger 18 is not reset and a single vibrator 45 is launched at the trailing edge of the pulse formed by single-vibrator 47, the output of which is short the pulse passes through the And 20 element (trigger 18 in a single state) and through the OR 35.1-35.3 elements it enters the inputs 70 of the testing of computing blocks 1.1-1.3.

 This signal starts testing the computing units and recovery equipment in the same way as described above in the testing sub-mode of one computing unit. In this case, the recovery equipment is tested in turn, and the computing unit that tests the recovery equipment sets a single signal at the output 79.i.3 and, while it is installed, other computing units are waiting. Since this increases the test time, the waiting computing units restart the single-shot 108 with a signal from the first output of channel C of the adapter 102.

At the end of testing computing blocks 1.1-1.3, three situations may arise:
All computing units 1.1-1.3 passed the test successfully. At their outputs 77, single signals are generated, which are fed to the code converter 55. It generates a single signal by which the trigger 18 is reset. A one-shot 84 is launched at the trailing edge of the signal at the output of the trigger 18, the pulse from the output of which passes through the OR element 44 and starts the one-shot 49 loading the next task. If the recovery equipment is serviceable, the system continues to work in recovery mode, if the recovery equipment is faulty, it goes into non-recovery mode.

 Two or one of the computing units have been tested successfully. In this case, the code converter 55 generates a single signal resetting the trigger 18. On the trailing edge of the signal at the output of the trigger 18, a single-shot 84 is launched, the pulse from the output of which passes through the OR element 44 and starts the single-shot 49 loading another task. The system will continue to operate without recovery.

 Three computing units failed. Then the element And 52 forms a single signal and gives it to the output 91 of the failure of the system.

) на счетчик 15 проходят n импульсов и на выходе мажоритарного элемента 10 не получен сигнал достоверности полученного решения, то счетчик 15 блокируется и выдает единичный сигнал на разрешающий вход счетчика 53.If, after the arrival of the ready signal, the solutions of one of the computing units 1.i (i =

) n pulses pass to the counter 15 and the reliability signal of the obtained solution is not received at the output of the majority element 10, then the counter 15 is blocked and provides a single signal to the enable input of the counter 53.

 According to the next clock pulse from the output 3.2 of the generator 3, the counter 53 increases its state by one and a single signal appears on the second output of the decoder 54, which allows writing to the registers 13.1-13.3, transfers the outputs of the registers 23.1-23.3 to the high-impedance state and removes the outputs of the registers from the high-impedance state 13.1-13.3. A single signal from the second output of the decoder 54 passes through the OR element 62 and starts the single-shot task re-vibrator 63 and outputs it to the output 93 of the task reload system. The pulse from the output of the single-shot 63 passes through the OR element 68 and resets the counter 15, and also enters the input 72 of the loading of the computing units 1.1-1.3. Computing blocks through the information inputs 73 re-accept the problem. At the end of the second decision, the actions described above take place, except that the results of the second decision are recorded in registers 13.1-13.3 (the first decision is recorded in registers 23.1-23.2).

 If, after a second decision, the counter 15 is not blocked, then the actions described above occur. If during the second solution the counter 15 is again blocked (i.e., a single signal is supplied to the V-input of counter 53), then according to the next clock pulse from the output 3.2 of generator 3, counter 53 increases its state by one and a single signal appears on the third output, but as at the output of the trigger 37 a zero signal, which closes the elements And 58, 59, then nothing happens. According to the next clock pulse, the unit appears on the fourth output of the decoder 54, thereby connecting the outputs of the register 13.1 to the outputs of the first computing unit 1.1, and the registers 23.2 and 23.3, respectively, to the outputs of the remaining blocks. Thus, the first solutions of computing blocks 1.2 and 1.3 and the second solution of computing block 1.1 are compared. If two of them are equal, then at the output of the majority element 10, an information reliability signal appears and the system operates as described above. If the comparison does not occur, then the next pulse from the output 3.2 of the generator 3 increases the state of the counter 53 by one and the unit appears on the fifth output of the decoder 54. Thereby, the first solutions of the computing units 1.1 and 1.3 are compared (outputs of the registers 23.1 and 23.3, respectively) and the second solution computing unit 1.2 (register output 13.2). If a comparison occurs, then the system continues to function normally, if not, then with the advent of a unit at the sixth output of the decoder, the first solution of computing units 1.1 and 1.2 is compared with the second solution of computing unit 1.3.

) сравняются, то данный блок 24.i сравнения выдает нулевой сигнал, открывающий элемент И 65.i.If the comparison does not occur again, a single signal appears on the seventh output of the decoder 54, which passes through the OR element 68, resets the counter 15, passes through the OR element 60 and the delay element 61, and opens the AND elements 65.1-65.3. The outputs of the registers 23.1-23.3, respectively, are connected to the first group of inputs of the comparison blocks 24.1-24.3 (i.e., the solutions issued by the computing blocks 1.1-1.3 after the first start), and the outputs of the registers 13.1-13.3 are in a high impedance state. The second group of outputs of the comparison blocks 24.1-24.3 is connected to the group of outputs 82 of the computing blocks 1.1-1.3, respectively, which are connected to the outputs of the channel B registers of the adapter 101, in which the solutions to the problem are written after the corresponding computing blocks 1.1-1.3 are restarted. Thus, comparison blocks 24.1-24.3 compare the first and second solutions of the corresponding computing unit, and the result of the comparison or non-comparison is output to the first inverse inputs of the corresponding elements AND 65.1-65.3. If two solutions of any computing unit 1.i (i =

) are compared, then this comparison unit 24.i gives a zero signal, the opening element And 65.i.

), на который выдан сигнал сравнения повторного решения блоком 24.i.A single signal from the output of the OR element 60 passes the delay element 61 (to end the transient processes on the comparison blocks 24.1-24.3 and the outputs of the registers 13.1-13.3 and 23.1-23.3 associated with the switching commutation) and gates the And 65.1-65.3 elements. Since all the computing units are operational, a single signal appears only at the output of that element AND 65.i (i =

) to which a comparison signal of the second decision is issued by block 24.i.

), то срабатывает мажоритарный элемент 8, единичный сигнал с выхода которого проходит через элементы ИЛИ 35.1-35.3 и, поступая на входы 70 вычислительных блоков 1.1-1.3, соответственно отправляет их на тестирование. По окончании тестирования происходят вышеописанные процессы, за исключением того, что по окончании тестирования формируется сигнал повторной загрузки задачи на выходе 93, а не очередной задачи, так как триггер 18 обнулен, и одновибратор 84 поэтому не запускается.If a single signal appears at the output of more than one AND element 65. i (i =

), then the majority element 8 is triggered, a single signal from the output of which passes through the elements OR 35.1-35.3 and, arriving at the inputs 70 of the computing blocks 1.1-1.3, respectively, sends them for testing. At the end of testing, the above processes occur, except that at the end of testing a signal is generated to reload the task at the output 93, and not the next task, since the trigger 18 is zeroed, and therefore the one-shot 84 does not start.

), то этот сигнал закрывает элемент И 39.i. Единичный сигнал с седьмого выхода дешифратора 54, пройдя через элемент 64 задержки (для установки сигналов на инверсных входах элементов И 39.1-39.3), обнуляет счетчик 53 и проходит через незапертые элементы И 39.1-39.3, т.е. через все, кроме 39.i. Единичные сигналы с выходов открытых элементов И 39.1-39.3 проходят через соответствующие элементы ИЛИ 35.1-35.3, запускают на тестирование соответствующие два вычислительных блока и через элемент ИЛИ 40 обнуляют триггер 17, т.е. устанавливают работу системы в режиме без восстановления.If a single signal appears only at the output of one AND element 65. i (i =

), then this signal closes AND 39.i. A single signal from the seventh output of the decoder 54, passing through the delay element 64 (to set the signals on the inverse inputs of the AND 39.1-39.3 elements), resets the counter 53 and passes through the unlocked AND 39.1-39.3 elements, i.e. through everything except 39.i. Single signals from the outputs of the open AND 39.1-39.3 elements pass through the corresponding OR 35.1-35.3 elements, run the corresponding two computing units for testing, and the trigger 17 is reset via the OR 40 element, i.e. set the system to work without recovery.

 At the same time, a single signal from the output of the And 65.i element passes through the OR element 67 and opens the And 30 element. The code converter 66, by a single signal at the output of the And 65.i element, commutes the output D0 with the input Di. A reliable solution from the output 82 of the computing unit 1.i passes through the main switch 7 and goes to the D-inputs of the register 14.

The next clock pulse τ ₂ from the output 3.2 of the generator 3 passes through the And 30 element, sets the trigger 19 to a single state, on the leading edge from the output of which reliable information is recorded in register 14 and issued at the output 95 of the system decision, accompanied by a single signal at the output of the 96 reliable system solutions.

 At the same time, the sync pulse, passing through the AND 33 element (since the system works in the first mode) and the OR element 44, starts the one-shot 49 downloading the next task. The clock passes through the OR element 68 and resets the counter 15. The pulse of loading a new task from the output of the one-shot 49 resets the counter 53, passes through the OR 62 and starts the one-shot 63 by reloading the task, and also passes to the input of the delay element 50, resetting the trigger after some time 19, i.e. the signal of information reliability at the output of system 96 is reset.

 The pulse from the output of the one-shot 63 is fed to the input of the loading of computing units 1.1-1.3 and they begin to load information about the next task (only those computing units that are not tested, since the priority of interrupting testing is higher than the priority of interrupting loading). Further, the system continues to work in the first mode with one computing unit performing the task and two testing computing units.

 If there is no single signal at one output of AND 65.1-65.3 elements, then all computing blocks 1.1-1.3 are sent for testing. At the end of the test, a single signal is generated by the code converter 55, which passes through the OR element 62 and starts the task re-load single-vibrator 63, which initiates the re-loading of the task into the computing units 1.1-1.3 in case of their successful testing and resets the counter 15.

 Thus, if among the six solutions obtained, at least two are the same, then the system issues them to the output of the solution and loads a new task. Consider the operation of the system in the mode without restoring the state of the computing units 1.1-1.3 with the functioning of three computing units. This mode differs from the second in that there is no expectation of a solution to the third lagging channel if the results of the first two solutions are compared, i.e. a single signal appears at the output of the majority element 10, which passes through the OR element 67 and opens the And 30 element. The next sync pulse passes through the And 30 and 33 elements (trigger 17 in the zero state), OR 44 and starts the one-shot 49 downloading the next task.

 Let us consider the operation of the system in the mode without restoring the state of computing units 1.1-1.3 when two computing units are functioning (one computing unit is faulty). The operation of the system with two functioning computing units coincides with the operation of the system with three functioning computing units in all, except, for example, that the computing unit 1.i has failed and at the output 86 of the failure signal generation unit 2.i there will be a single signal that locks elements And 65. i and 25.i, thereby excluding from the evaluation of the results of the comparison the result of the failed channel. In this case, the trigger 17 is reliably set to the zero state, the second S- and first R-inputs of the trigger 37 are supplied from the output 86.i through the element OR 51 single signal. Trigger 37 is in a single state if two channels are working, and in a zero state if one channel is working and the other is being tested or failed (the third has already failed).

 Consider the operation of the system in the mode without restoring the state of computing units 1.1-1.3 when one computing unit is functioning (the other two are in failure or one is in failure, and the other is being tested). When operating in this mode, the triggers 17 and 37 are in the zero state. Let, for example, the computing unit 1.i (i = 1,3) function. Then, after solving the problem, the computational unit 1.i writes the result to register 23.i and gives an output signal 78.i ready to solve the problem, which is fixed in register 11 and through the element OR 42 opens the element And 29 for the passage of clock pulses. The counter 15 is necessarily blocked, because from the group of elements AND 25.1-25.3 only the element And 25.i is open, therefore, at the output of the majority element 10, the signal is always zero. A single signal from the output of the locked counter 15 allows the counter 53 to work. Another pulse from the output 3.2 of the generator 3 increases the state of the counter by one and a single signal appears on the second output of the decoder 54, which allows writing to the registers 13.1-13.3 and connects their outputs to the bus, and disables the outputs of the registers 23.1-23.3. This single signal also passes through the OR element 62 and starts the single-shot 63 reloading tasks. The pulse from the output of the single-shot 63 resets the counter 15 and initiates the reloading of the task into the computing unit 1.i. At the end of the second decision, the above actions occur, but the second result is written to register 13.i, and according to the next clock pulse from the output 3.2 of generator 3, a single signal appears on the third output of the decoder 54, which causes the output of register 23. i to be connected to the bus and to the first input block 24.i comparison, to the second input of which is connected a group of outputs 82 of the computing unit 1.i. It is connected to the output of the channel B register of the adapter 101, in which the second solution of the problem is recorded.

 A single signal from the third output of the decoder passes through the open elements AND 59, OR 60, the delay element 61 and gates the element And 65.i. If the first and second solutions are compared, then the output of the AND 65.i element will be a single signal that passes through the OR element 67 and opens the And 30 element. The code converter 66 sets the main switch 7 to the multiplexer mode connecting the Di bus to the D0 bus. The next clock pulse from the output 3.2 of the generator 3 passes through the And 30 element, resets the counter 15 and sets the trigger 19 to a single state. On the rising edge of the signal from the output of the trigger 19, a reliable decision is written to the decision output group 95, which is accompanied by a single signal at the output 96 of the reliability system at the output of 95.

 The pulse from the output of the And 30 element passes through the And 33, OR 44 elements and starts the one-shot 49 loading a new task. At the same time, a single signal from the output of AND element 59 passes through the OR element 62 and starts the single-vibrator 63 for reloading the task, but since the single-vibrator 49 for loading a new task starts, an external system using this system identifies the signal as a load signal for the new task.

 If the results of the first and second solutions are not comparable, then only the one-shot 63 of reloading the task is started and the computing unit 1.i solves the problem for the third time. At the end of the decision, the decision result remains in the channel B register of adapter 101 and is not written to the registers 23.i and 13.i, since zero signals are supplied to the V-inputs of these registers. The counter 15 is locked and allows the operation of the counter 53.

 The sequential appearance of single signals at the fourth, fifth and sixth outputs of the decoder 54 allows you to consistently compare the third solution with the first and second solutions (stored in the registers 23.i and 13.i. If the comparison occurs, then as a result of the above steps, the one-shot 49 of loading a new task is launched the pulse from the output of which resets the counter 53 to the zero state.

 If the comparison does not occur, then a single signal appears on the seventh output of the decoder 54, which passes through the OR element 68, resetting the counter 15, and through the delay element 64, resetting the counter 53, the AND elements 39. i, OR 35.i and starts the computing unit 1.i for testing.

 If the computing unit 1.i fails during the solution of the problem, then this is fixed as follows. Before loading the task, the microprocessor 100 loads into the timer 99 the maximum time for solving the problem. If the problem is not solved during this time, then the timer 99 generates a pulse at the output 69 of the computing unit 1.i, which passes through the OR element 35.i and starts the computing unit 1.i for testing, thereby a malfunction of the computing unit 1.i will be detected .

 Thus, in this asynchronous system, failure occurs only in the event of failure of all computing units 1.1-1.3, which is fixed by AND 52, the output of which is the output 91 of the system failure.

Claims (1)

 A THREE-CHANNEL ASYNCHRONOUS SYSTEM, comprising in each channel a computing unit connected to the first, second and third signal outputs to the corresponding information inputs of the failure signal generating unit, and the first element AND, the first information outputs of the failure channel generating units of the three channels are connected to the corresponding inputs of the first majority element, pulse generator, characterized in that the first and second registers, the first and second comparison blocks, the first and second elements are introduced into each channel of the system OR, the second and third AND elements, as well as two main switches, three code converters, three registers, a decoder, three counters, six one-shots, four triggers, two majority elements, thirteen AND elements, thirteen OR elements, three delay elements, are introduced into the system the second information outputs of the failure signal generating units of the first, second and third channels are connected to the inputs of the third OR element and to the first inputs of the corresponding first OR elements connected by the second inputs to the control output the corresponding computing unit, the third inputs - with the output of the second majority element, the fourth inputs - with the output of the fourth AND element, the fifth inputs - with the outputs of the corresponding first AND elements, and the outputs - with the first group of inputs of the fourth OR element, with the group of inputs of the fifth OR element and with the first control inputs of the corresponding computing units connected by the second control inputs to the output of the first one-shot, third control inputs to the output of the second one-shot and to the first input an ode of the sixth OR element, the first control outputs to the first group of inputs of the second code converter, the second control outputs to the group of information inputs of the third register, the groups of information inputs and outputs to the corresponding groups of information inputs and outputs of the first main switch, the first groups of information outputs to groups of information inputs of the corresponding first and second registers and to the first groups of information inputs of the corresponding first comparison blocks, the second group the information outputs of the computing unit of the first channel is connected with the first groups of information inputs of the computing units of the second and third channels, while the first and fourth bit outputs of the second group of information outputs of the computing unit of the first channel are connected respectively to the first input of the first code converter, to the first input of the fifth element And, to the second input of the first code converter and to the first input of the seventh OR element, connected by the second input to the output of the fifth AND element, and the output to y set and synchronizing inputs of the fourth register, with the third input of the first code converter and with the signal inputs of the computing units of the first, second and third channels, the second group of information outputs of the computing unit of the second channel is connected to the first group of information inputs of the computing unit of the first channel and to the second group of information inputs of the computing block of the third channel, while the first - fourth bit outputs of the second group of information outputs of the computing unit W The second channel is connected respectively to the fourth input of the first code converter, to the second input of the fifth AND element, to the input of the first code converter and the third input of the seventh OR element, the second group of information outputs of the computing unit of the third channel is connected to the second groups of information inputs of the computing blocks of the first and third channels, with this first - fourth bit outputs of the second group of information outputs of the computing unit of the third channel are connected respectively to the sixth input ne of the first code converter, with the third input of the fifth element AND, with the seventh input of the first code converter and with the fourth input of the seventh element OR, the group of outputs of the first code converter is connected to the group of control inputs of the first main switch connected by the fourth group of information inputs and outputs with a group of information inputs and with a group the outputs of the fourth register, the first output of the pulse generator is connected to the clock input of the third register, to the clock inputs of the first registers to the counting input of the first counter connected to the first input of zeroing with the direct inputs of the first elements of And and with the input of the first delay element, the second input of zeroing - with the input of zeroing of the third register, with the first input of the eighth OR element, with the output of the third one-shot and through the second delay element - with the R-input of the first trigger, the input of the resolution enable - with the lock input and the overflow output of the second counter, and the group of bit outputs - with the group of inputs of the decoder connected with the first output to the resolution input write the second registers of all channels, the second output to the second input of the eighth OR element, to the recording permission inputs of the first registers of all channels and to the first inputs of the second OR elements of all channels, the third output to the first input of the sixth AND element, and the fourth output to the first input the ninth OR element and to the second input of the second OR element of the first channel, the fifth output to the second inputs of the ninth and second OR elements of the second channel, the sixth output to the third input of the ninth and second input of the second OR third channel, the seventh output - to the output of the first delay element, to the second input of the sixth OR element and the first input of the tenth OR element, connected through the second delay element with direct inputs of the second elements AND of all channels, the second input - with the output of the fifth AND element, connected by the first input to the output of the ninth OR element, and the second input to the inverse output of the second trigger and the second input of the sixth AND element, connected by the output to the third input of the tenth OR element and to the third input of the eighth OR element, connected ode to the input of the second one-shot, and the fourth input to the output of the second code converter and to the zero input of the third trigger, connected by a single input to the output of the seventh element And, with the inputs of the first one-shot and fourth fourth vibrator, connected by the output to the first input of the fourth element And, connected by the second input with the direct output of the third trigger and the input of the fifth one-shot connected to the first input of the eleventh element OR, connected by the output to the input of the third one-shot, the second input m - with the output of the eighth element And, and the third input - with the output of the ninth element And connected by a direct input to the J and C inputs of the first trigger, to the output of the tenth element And and the third input of the sixth element OR, and the inverse input to the first inputs of the eleventh and the twelfth AND element and to the first output of the fourth trigger connected by a single input to the first single input of the second trigger, with the output of the twelfth OR element, and the zero input - with the output of the fourth OR element connected by the second group of inputs to the third outputs locks for generating a failure signal of all channels, the first input to the output of the third OR element and to the inverse input of the seventh AND element, and the second input to the output of the thirteenth OR element, to the first zero and second unit inputs of the second trigger connected by the second zero input to the output of the fifth OR element connected by an input to the output of the first majority element connected by inputs to the inputs of the thirteenth elements OR and AND, with the first inverse inputs of the corresponding third AND elements, with the first group of inputs the third about the code converter and with the first inverse inputs of the corresponding second AND elements connected by the second inverse inputs to the equality outputs of the corresponding first comparison blocks, and the outputs to the inverse inputs of the corresponding first AND elements, to the corresponding inputs of the second majority element, to the corresponding inputs of the fourteenth OR element, and to the second group of inputs of the third code converter connected by the group of outputs to the group of control inputs of the second main switch connected first the second, third and third groups of information inputs to the output groups of the corresponding second registers and to the first groups of information inputs of the corresponding second comparison blocks connected by the second groups of information inputs to the output group of the second main switch and the group of information inputs of the fifth register, and the equality outputs to the second the inverse inputs of the corresponding third AND elements, connected by direct inputs to the corresponding outputs of the third register, to the inputs of the fifteenth element of IL and the thirteenth AND element, and the outputs to the fourth inputs of the corresponding failure signal generating units, to the inputs of the fourteenth AND element and to the corresponding inputs of the third majority element, connected to the fourth input of the fourteenth OR element, connected by the output to the first input of the tenth AND element and to the inverse the input of the fifteenth AND element, connected by the first direct input to the output of the fifteenth OR element, and the second direct input - with the second output of the pulse generator, with the fifth inputs corresponding of the fault signal generating blocks, with the second inputs of the eleventh and twelfth elements AND and with the second input of the tenth element AND, and the output with the counting input of the second counter connected to the zeroing input to the output of the sixth OR element, the direct output of the first trigger is connected to the synchronizing input of the fifth register , with the first input of the sixteenth element And and with the third input of the eleventh element And, connected by the fourth input to the output of the thirteenth element And, to the sixth inputs of the respective signal conditioning units and to the third input of the twelfth element And, connected by the output to the input of zeroing the third counter, to the first input of the eighth element And and the second input of the sixteenth element And, connected by the inverse input to the output of the fourteenth element And and the second input of the eighth element And, and the output - the first start input of the sixth one-shot connected to the input of the third one-shot connected to the output of the direct input of the seventh element And the second start input of the sixth one-shot is connected to the overflow output third of the counter connected by the counting input to the output of the eleventh AND element, the output of the eleventh OR element is connected to the input of the third one-shot, the groups of outputs of the first registers are connected to the second groups of information inputs of the corresponding comparison units, the first, second and third inputs of the twelfth element OR are connected to the first signal outputs corresponding computing units, and the fourth input of the twelfth element OR is the first installation input of the operating mode of the system, the third input of the fourth element and OR is the second installation input of the system operation mode, the pulse generator connection input is the system start input, the first outputs of the failure signal generating units are the error outputs of the computing unit of the corresponding channel, the third outputs of the failure signal generating units are the signal outputs of the failure of the recovery channel equipment of the corresponding channel the outputs of the fifth register is the information output of the system, the outputs of the second and third one-shot c are the signal mode outputs of the system, the third group of information inputs of the computing units are the corresponding information inputs of the system.

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