RU2013011C1 - Device for channel selection - Google Patents

Abstract

FIELD: radio engineering. SUBSTANCE: device for channel selection has control unit 1, n processing channels. Each of them includes key n₁, amplifier n₂, AND gate n₃, counter n₄, threshold unit n₅, flip-flop n₆, delay line n₇. Device can be used for determination of number of channel with high noise immunity within confines of preassigned group when pulse signals are processed. EFFECT: enhanced noise immunity. 3 dwg

Description

 The invention relates to radio engineering and can be used in the processing of pulse signals to determine the channel number within a given group.

 A device is known that can be used to determine the channel number (ed. St. N 1264360, class H 04 j 7/00; ed. St. N 1201846, class G 06 F 15/336).

 The device according to ed. St. N 1264360 contains a switch, a first and second memory unit, an oscillator, a counter, a comparison unit, the output of the switch being connected to the inputs of the first memory unit and the comparison unit, the output of which is connected to the input of the second memory unit and the second input of the first memory unit, the output of which is connected to the second input of the comparison unit, the second input of the second memory unit is connected to the input of the switch and the output of the counter, the input of which is connected to the output of the oscillator.

 However, this device has low reliability in determining the channel number during the processing of pulse signals, in which individual impulses may disappear.

 The device according to ed. St. N 1201846 contains the first and second analog-to-digital converters, a clock pulse generator, three frequency dividers, a key, a counter, a trigger, a memory block, a delay block, n multiplication blocks, n keys of the first group, n averaging blocks, m keys of the second group and an element OR.

 However, such a device can be used to determine the channel number by measuring with high accuracy the cross-correlation function only in the presence of reference signals.

Closest to the invention in technical essence is a device containing a series-connected first amplifier, multiplier, integrator and second amplifier, as well as a delay line, the input of which is connected to the output of the first amplifier, and the output is connected to the second input of the multiplier. In this device, when processing pulse signals, the And circuit can be used as a multiplier, and a pulse counter as an integrator. If the device has an adjustable delay line, it can be used to determine the channel number within a given group when processing pulse signals described by the observation model
Y (t) = S (t) + n (t), (1) where S (t) = U _o Σ $\genfrac{}{}{0ex}{}{\text{∞}}{\text{k}}$ _{= -∞} f (tt _k ); t _k = kT _i ; k = 1,2,3,. . . . ;
T _i - pulse repetition period; i = 1, 2, 3,. . . , n; T ₁ = T; T ₂ = 2T; T ₃ = 3T; . . . , T _n = nT; n (t) is the fluctuation noise.

1/

e

, (2) где m - математическое ожидание; σ - среднее квадратическое отклонение. При э

ом в принимаемом колебании может быть только один из сигналов, например сигнал с периодом Ti. Примерами таких сигналов в определенной степени могут служить многие телеграфные сигналы, сигналы передачи данных и т. д.Moreover, in the pulse sequence S (t), one or several in a row may be lost. The probability of occurrence at the corresponding moment in time (i.e., with the beginning of the next period) of zero or one (i.e., an impulse or its absence) is 0.5. In this case, the pulse duty cycle equal to the ratio Ti / Δti is much greater than unity (Δti is the pulse duration). Under the action of n (t) in the signal S (t), the period is a random variable distributed according to the normal law:
f (T) =

1/

e

, (2) where m is the mathematical expectation; σ is the standard deviation. When e

In the received oscillation, there can be only one of the signals, for example, a signal with a period of Ti. To some extent, many telegraph signals, data signals, etc. can serve as examples of such signals.

 To determine the channel number from a group equal to n, n devices connected in parallel containing different delay lines can also be used. However, in any case, these devices will have low noise immunity with respect to mutual interference.

 The aim of the invention is to increase noise immunity.

 To do this, in a device for selecting a channel containing n parallel-connected processing channels, each of which includes a series-connected amplifier, an element And, a counter, a threshold unit and a delay line, the input of which is connected to the first input of the element And, and the output of the delay line is connected with the second input of AND element, a control unit with (n + 1) inputs and (n + 1) outputs is introduced, and a key and a trigger are entered into each of the n processing channels, the first key input being the input of the processing channel, the output of which is the trigger output , at the key path is connected to the input of the amplifier, and the output of the threshold block is connected to the first input of the trigger, the second input of which is connected to the (n + 1) -th output of the control unit, while the combined channel inputs are the input of the device that is connected to (n + 1) -th input of the control unit, the first (n-1) -th inputs of which are connected respectively to the outputs of the first (n-1) -x processing channels, and the outputs of each processing channel are the outputs of the device, while the nth input of the control unit is the input “Start” signal, and the second key input is connected respectively but with the output of the control unit.

 In FIG. 1 shows a structural electrical diagram of the proposed device; in FIG. 2 is a structural electrical diagram of a node 1; in FIG. 3 - time diagrams of the operation of the device.

 A device for selecting a channel contains n signal processing channels (1, 2, 3,..., N), control circuit 1. In this case, the number of channels is determined by the number of pulse signals within a given group.

 Each channel includes a series-connected key (1-1, 2-1, ..., n-1), an amplifier (1-2, 2-2, ..., n-2), 2-3,. . . , n-3), counter (1-4, 2-4, ..., n-4), threshold device (1-5, 2-5,..., n-5), trigger (1-6 , 2-6,..., N-6), as well as a delay line (1-7, 2-7, ..., n-7), the input of which is connected to the output of the amplifier (1-2, 2-2 ,..., n-2), and the output is connected to the second input of the And circuit (1-3, 2-3, ..., n-3; the device input is the first key inputs connected to each other (1-1, 2 -1,..., N-1 and n + 1 inputs of the control circuit 1) the outputs of the device are the outputs of the triggers (1-6, 2-6,..., N-6), and the outputs of the triggers 1-6, 2 -6... (N-1) - 6 are connected respectively to 1, 2 ... n-1 inputs of the control circuit 1).

 The device operates as follows.

 When the Start signal arrives, the device is alerted to receive and process pulse signals. In this case, the channel triggers (1-6, 2-6, ..., n-6) are set to "0". If now impulses described by the observation model (1) begin to arrive at the input of the device, then from the action of the first input pulse at outputs 1, 2,. . . , n control circuits 1 there are potentials that open the channel keys (1-1, 2-1, ..., n-1). At the same time, these keys appear to be open, respectively, during the time intervals NT1NT2,. . . , NTn, where N is an integer significantly larger than unity; T1, T2,. . . , Tn - respectively, the signal periods of the first, second. . . nth processing channel. In this case, the analyzed pulse signal from the outputs of the keys (1-1, 2-1, ..., n-1) through the amplifiers (1-2, 2-2, ..., n-2) starts to arrive simultaneously at the inputs And circuits (1-3, 2-3, ..., n-3) and the inputs of the delay lines (1-7, 2-7, ..., n-7). Moreover, the signal delay time in the first, second n-th channels is determined respectively as T1, T2,. . . , Tn, where T1, T2,. . . , Tn - respectively, the periods of the signals of the first, second. . . n-th processing channels.

 The delayed pulse arrives at the AND circuit (1-3, 2-3, ..., n-3) of each channel, the other input of which receives an uncontrolled pulse train. In this case, pulses will appear at the outputs of AND circuits only when, after the corresponding delay time, the next pulse arrives. In the general case, such a coincidence of pulses can be provided for several channels at once. The number of pulses at the output of each AND circuit is counted by counters (1-4, 2-4, ..., n-4), the outputs of which are connected to threshold devices (1-5, 2-5, ..., n-5) .

The responses at the outputs of the threshold devices will appear if the corresponding counters for a time equal to NT ₁ , NT ₂ ,, respectively. . . , NT _n , count the number of pulses equal to NM _ζ , where M _ζ is the mathematical expectation of the number of missing pulses. The value of M can be defined as
M _ζ = Σ $\genfrac{}{}{0ex}{}{\text{N}}{\text{k}}$ _{= 1} a _k P _k (3)
In the expression (3) a _k is the intensity of the flow (the number of pulses per second); P _k = (at) ^k · e ^-at / K! - the probability of the appearance of k pulses in the time interval (0, t) (N. Sedyakin. Elements of the theory of random pulsed flows. M.: Sov. radio, 1965, p. 59).

 Moreover, if the pulses follow with the ith initial period, the response will appear at the output of the threshold device of the ith channel. In the channels of higher numbers, there will be no responses at the outputs of threshold devices, since the keys are (i + 1) -1, (i + 2) -1,. . . , n-1 will close faster than key i-1 due to the presence of control circuit 1.

 The response at the output of the threshold device i-5 trigger i-6 is set to "1". In this case, the control circuit 1 and its outputs 1, 2,. . . , (i-1) -1 potentials disappear, which leads to the closure of keys 1-1, 2-1,. . . , (i-1) -1. In this regard, the responses at the outputs of the threshold devices 1-6, 2-6,. . . , (i-1) -6 do not have time to appear.

 Setting trigger i-6 to "1" signals that the analyzed pulse sequence belongs to the i-th channel.

 Thus, by introducing into the device for selecting the channel n keys, n triggers and a control circuit, the noise immunity of the device with respect to mutual interference is increased.

 All nodes of the circuit in FIG. 1, in addition to node 1, are standard, well-known devices.

 In FIG. 2 is a structural electrical diagram of node 1. The node contains an OR circuit 1, a ready trigger 2, a trigger 3, a clock 4, an I5 circuit, an I6 circuit, a pulse shaper 7, an OR 8 circuit, a pulse shaper 9, an analysis interval counter 10, OR circuit 11 and key control channels, each of which includes a series-connected OR circuit (1-1, 1-2, ..., 1-n), a pulse shaper (2-1, 2-2, ... , 2-n) and interval trigger (3-1, 3-2, ..., 3-n). At the same time, the trigger input 2 and the first inputs of the OR circuit 1, OR 8 circuit, as well as the second inputs of the OR circuit (1-1, 1-2, ..., 1-n) receive the Start signal. The input R of trigger 2 is connected to the second input of the OR circuit 1 and the output of the OR circuit 11, as well as to the third inputs of the OR circuit (1-1, 1-2, ..., 1-n) of all channels, and the second input of the OR circuit 8 , the output of the OR circuit 1 is connected to the input R of the trigger 3, the input S of the trigger 3 is connected to the output of the I5 circuit, the first input of which is the analyzed pulse sequence of the AIP, and the second input is connected to the output of the trigger 2, the output of the generator 4 of the counting pulses is connected to the second input circuit I6, the first input of which is connected to the output of trigger 3 and through a pulse shaper 7 with input S of all the triggers of the intervals (3-1, 3-2,..., 3-n), the output of circuit I6 is connected to the second input of the counter 10, the first input of which through the pulse former 9 is connected to the output of the circuit OR 8, the first output of the counter 10 is connected to the first input of the OR circuit 1-1, the second output of the counter 10 is connected to the first input of the OR circuit 1-2, the third output of the counter 10 is connected to the first input of the circuit OR 1-3, etc., the nth output of the counter 10 is connected to the first input of the OR circuit 1-n, the outputs of the OR circuit (1-1, 1-2,. . . , 1-n), respectively, through pulse shapers (2-1, 2-2, ..., 2-n), are connected to the inputs of R triggers (3-1, 3-2, ..., 3-n), the outputs triggers 3-1, 3-2,. . . , 3-n are used to control keys 1-1, 2-1, respectively. . . , n-1 in the circuit of FIG. 1, the first input of the OR circuit 11 is connected to the output of the trigger 1-6 of the circuit in FIG. 1, the second input of the OR circuit 11 is connected to the output of the trigger 2-6 of the circuit in FIG. 1, etc., the n-1 input of the OR circuit 11 is connected to the output of the trigger (n = 1) -6 of the circuit in FIG. 1, n, the output of the counter 10 is connected to the input of the OR circuit 11, formers 7, 2-1, 2-2,. . . , 2-n are designed to convert the negative (reverse) edges of the signals arriving at their input into negative short pulses of positive logic for asynchronous control of channel triggers (3-1, 2-2, ..., 3-n), shaper 9 generates short positive impulses of zeroing the counter of the interval on the positive edge of the signal arriving at the input of the former.

 The control circuit operates as follows.

 With the arrival of the Start signal (a short negative pulse of positive logic) into the control circuit, the ready trigger 2 is set to "1", and the start trigger 3 is set to "0", interval triggers (3-1, 3-2, ..., 3-n) to “0”, the analysis interval counter to “0”, channel triggers (1-6, 2-6, ..., n-6) in the circuit of FIG. 1 - to "0".

 With the arrival of the nearest pulse of the analyzed pulse sequence trigger trigger 3 is set to "1". The signal from the output of trigger 3 triggers the passage through element I6 of the pulses of generator 4 to the counter of the analysis intervals, sets triggers 3-1, 3-2, to "1". . . , 3-n intervals of each channel. Triggers 3-1, 3-2, 3-n control the passage through keys 1-1, 2-1,. . . , n-1 of the analyzed pulse sequence to the inputs of amplifiers 1-2, 2-2,. . . , n-2 processing channels in the circuit of FIG. 1. As a result of processing the analyzed pulse sequence, the corresponding i-th trigger of channel i-6 is set to "1", which means that there is an i-channel signal at the device input, the signal from the output of this trigger through the OR element 11, the other inputs of which are connected with trigger outputs 1-6, 2-6,. . . , (n-1) -60 (n + 1) -6,. . . . , (n-1) -6, arrive at the ready trigger 2, the trigger trigger 3, the counter of analysis intervals 8, and resets them. Thus, the next cycle of the device.

 In FIG. 2, the OR circuit 11 has n inputs, of which n-1 inputs are connected respectively to the outputs of triggers 1-6, 2-6,. . . , (n-1) -6 channels of circuit 1, and the nth input of OR circuit 11 is connected to the senior, nth output of interval counter 10.

 In the analysis process, after generating the entire analysis interval and the absence of any channel signal from this group at the device input, the signal from the senior output of the interval 10 counter, passing through the OR circuit 11, will establish the control circuit of the channel selection device to its initial state.

 In FIG. 3 shows the timing diagrams of the operation of the device for channel selection. In this figure is indicated: AIP - analyzed pulse sequence; START - start signal; Tg GOT — the availability trigger in the circuit of FIG. 2; TgZAP - trigger trigger circuit pic. 2; TgINTi is an interval trigger of the ith channel in the circuit of FIG. 2; RgKAN — channel trigger in the circuit of FIG. 1; Output Кli - key of i - channel in the circuit of FIG. 1.

 An autocorrelation receiver was chosen as the base object (see Lange F. Correlation Electronics. Sudpromgiz, 1963).

 The expected economic effect of the use of the proposed device is due to the possibility of achieving greater noise immunity.

Claims (1)

 A CHANNEL SELECTOR device containing n parallel-connected processing channels, each of which includes a series-connected amplifier, an And element, a counter, a threshold block and a delay line, the input of which is connected to the first input of the And element, and the output of the delay line is connected to the second input element And, characterized in that, in order to increase noise immunity, a control unit with n + 1 inputs and n + 1 outputs is inserted into the device, and a key and a trigger are entered into each of n processing channels, the first key input being an input a processing channel, the output of which is the trigger output, the key output being connected to the amplifier input, and the output of the threshold block connected to the first input of the trigger, the second input of which is connected to the (n + 1) -th output of the control unit, and the combined channel inputs are the device input which is connected to the (n + 1) -th input of the control unit, the first (n - 1) -th inputs of which are connected respectively to the outputs of the first (n - 1) -th processing channels, and the outputs of each processing channel are the outputs of the device, this is the nth input of the control unit is the input of the Start signal, and the second key input is connected respectively to the output of the control unit.

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