RU2003119978A - RANDOM SEQUENCE GENERATOR - Google Patents

Claims (3)

1. A random sequence generator containing a random number source, an N-bit selector-multiplexer, random access memory, a multi-input OR element, an I block of elements, whose M-bit output, where M≥2 is the bit capacity of the generated numbers, is an M-bit output "Result" of the generator, bits of the N-bit output "Random address values" of the source of random numbers, where N≥2 is the number of bits sufficient for addressing the elements of a given data set, connected to the corresponding inputs of the second group s information inputs of the N-bit selector-multiplexer, N outputs of which are connected to the corresponding address inputs of random access memory, M information inputs of which are the corresponding bits of the M-bit information input of the device, and M outputs of the random access memory are connected to the corresponding bits of the M-bit the input "Random number" of the block of AND elements, the second enable input of which is connected to the output of the multi-input OR element, the control input of the source random numbers, the input of the selection of the N-bit selector-multiplexer, the control input of the block of elements And are combined and are the control input of the generator, N inputs of the first group of information inputs of the N-bit selector-multiplexer are the N-bit address input of the generator, the inverse enable input N- the bit selector-multiplexer is the first enable input of the generator, and the inverse inputs of the chip selection and read / write of random access memory are respectively the inputs a "and" Read / write "of the generator, characterized in that an interval control unit and a number of generations control unit are additionally introduced, and a multi-input OR element is made with J inputs, where J≥2 is the bit capacity of the number of generations, K M-bit value inputs intervals of the interval monitoring unit, where K≥2 is the number of intervals into which the given data set is divided, are K M-bit inputs of the device interval values, K J-bit inputs "Number of generations" of the number of generations control unit are K J-bit input inputs “Number of generations” of the device, the input “Installation” of the control unit for the number of generations is the input “Setup” of the generator, and M outputs of random access memory are connected to the corresponding bits of the M-bit input “Random number” of the interval monitoring unit, L-bit, output "Interval Number" where

- the number of bits sufficient to encode the interval numbers, the interval control unit is connected to the L-bit input "Interval number" of the number of generations control unit, the bits of the J-bit output "Current value of the number of generations" of which are connected to the corresponding inputs of the J-input OR element, the output of which is connected to the second enable input of the control unit for the number of generations. 2. The device according to claim 1, characterized in that the interval monitoring unit consists of K comparators, K two-input elements OR NOT, priority encoder, L inverters, output l-th, where l = 1,2, ..., L , the inverter is the l-th bit of the L-bit output "Interval number" of the interval monitoring unit, and the input of the l-th inverter is connected to the l-th inverse output of the priority encoder, k-th, where k = 1,2, ... K whose inverse input is connected to the inverse output of the k-th two-input OR-NOT element, the first and second inputs of the k-th two-input OR-NOT element are connected respectively to the outputs "Equality" and "Inequality" of the k-th comparator, m-th, where m = 1,2, ..., M, the inputs of the first groups of information inputs of the comparators are interconnected and are the m-th discharge of the m-bit input The "random number" of the interval control unit, and the m-th input of the second group of information inputs of the k-th comparator is the m-th bit of the k-th M-bit input of the value of the intervals of the block. 3. The device according to claim 1, characterized in that the control unit for the number of generations consists of a low level decoder, an inverter, K two-input elements OR NOT, K reversible counters, J selector-multiplexers, each of which is equipped with L data selection inputs and K information inputs, each of the L inputs of the low-level decoder is connected to the corresponding data selection inputs of J selector-multiplexers and is the corresponding bit of the input "Interval number" of the control unit for the number of generations, the first input of the k-th two-inputs of the OR element is NOT connected to the k-th inverse output of the low level decoder, and the second inputs of the two-input OR-NOT elements are interconnected and connected to the output of the inverter, the input of which is the second enable input of the control unit for the number of generations, the inverse output of the k of the two-input element OR NOT connected to the counting input of the k-th reverse counter, J information inputs of the k-th reverse counter are the corresponding bits of the k-th J-bit input "Number of generations" of the control unit th, inverse gates of preliminary recording of each reverse counter are interconnected and are the “Installation” input of the number of generations control unit, j-th output where j = 1,2, ..., J, k-th reverse counter is connected to k- mu information input of the j-th selector-multiplexer, the outputs of the J selector-multiplexers are the corresponding bits of the J-bit output "Current value of the number of generations" of the block.