RU1807560C - Converter from shaft turn angle to code - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to connect analog information sources with a digital computing device. Purpose is to simplify the converter by eliminating mechanical alignment of samples and increasing accuracy. To a converter comprising a pulse generator 1, a frequency divider 2, a power driver 3, a phase shifter unit 4, a first pulse generator unit 5,

Description

the first block of 7 registers, the second block of 6 pulse shapers, blocks of 8 and 9 registers, blocks of 10-13 adders, block 14 of memory elements, multipliers 15 and 16, code buses 17 and 18, phase shifters of block 4 with multiple electrical reduction coefficients are installed independently of each other on the input shaft without mechanical alignment. Blocks 7 and 8 are recorded. current information on the angular position of the phase shifters. Blocks 9-16 and buses 17, 18 are used to determine the relative position of the phase shifters, match samples, and generate a unique position code for all samples in the 360 ° range. 2 ill.

The invention relates to automation and computer technology and can be used to communicate analogue information sources with a digital computing device.

The aim of the invention is to simplify the converter by eliminating mechanical alignment of readings and increasing accuracy by selecting phase shifters with mismatched harmonic components of errors and their mutual compensation in the pulp and paper mill according to a known method.

In FIG. 1 shows a block diagram of a shaft angle to angle converter; in FIG. 2 is a block diagram of one of the elements of a memory unit.

The converter (Fig. 1) comprises a pulse generator 1, a frequency divider 2, a power driver 3, a phase shifter unit 4, pulse former 5 blocks and 6, 7-9 register blocks, 10-13 adder blocks, a memory element block 14, multipliers 15 and 16, code buses 17 and 18.

The outputs of the converter are connected to the inputs of a digital computer complex (PPM) 19 ..

The element of block 14 (Fig. 2) contains adders 20 and 21, register 22, indicator 23, switch 24, bus 25 zero and bus 26 unit potential.

Block 4 contains a phase shifter 4/1 of a coarse reference (GO) (with an electric reduction coefficient P1), a phase shifter 4/2 of an intermediate reference (PO) with an electric reduction coefficient of P2, and a phase shifter 4/3 of an exact TO reference with an electric coefficient RP reductions, All-phase shifters are installed on the same shaft and are made in the form of single-phase phase shifters with phase-shifting elements. The outputs of the phase shifters of block 4 with a positive phase shift as a function of the angle of rotation of the shaft are connected to the information inputs of the shapers of block 5. The outputs of the shapers of block 5 are connected to the clock inputs of the corresponding registers of block 7, and the outputs of the shapers of block 6 are connected to the clock inputs of the corresponding registers of block 8. The information inputs of all the registers of blocks 7 and 8 are connected to the outputs of the bits of the frequency divider 2, and the outputs of the registers of blocks 7 and 8 are connected in pairs to the summing and subtracting inputs of the adders block 10. The outputs of phase shifters 4 .bloka negative phase shift as a function of and are connected to data input of block 6.

The outputs of the bits of the adders 10/1 (10/2 (without sign) are connected to one group of inputs of the adders 20 of the block 14/1 and 14/2, respectively. The outputs of the lower (K-1) bits of the registers 7/1, 7/2 connected to the summing inputs of adders 21 blocks 14/1, 14/2, subtracting inputs of which are connected to the outputs (K-1) of the senior bits of the respective adders 20. The outputs of the lower matching bits of the multipliers 16, 15 are connected to the group of summing inputs of the adders 21 blocks 14 / 3,14 / 14, the group of subtracting inputs of which are connected to the outputs of equivalent high-order bits, respectively adders 20. One group of inputs of adder 20 of blocks 14/3, 14/4 is connected to the outputs of the higher bits of the adder 10/3 and register 9/2, respectively.These bits are equivalent in price to the lowest matching bits of the multipliers 16 and 15 and the next low order bit. Another group of inputs of the adders 20 is constantly connected to the buses 26 and 25 of the unit and zero potentials, while the input of the high order and the input of the next low after the lowest matching bit are connected to bus 26, and the remaining bits are connected to the bus 25.

The outputs of the bits of the adder module 21 are connected to the information inputs of the register 22, the clock input of which is the clock input of the corresponding element of the block 14. The output of the register 22 is connected to the indicator 23. The information of the switch 24 is set by jumpers with buses

unit 26 and zero 25 potentials depending on the information at the outputs of the indicator 23. The outputs of the registers 7/1. 7/2, multipliers 16, 15 are connected to the summing inputs of the adders of block 11, and the outputs of the elements 14 / 1,14 / 2.14 / 3,14 / 4 are connected to the subtracting inputs of the equivalent bits of the adders of block 11. The output of the sign bit of the adders block 11 is not used. The high-order output of the module of each of the adders 11/1, 11/2 is connected to one input of the corresponding single-bit adder 13/1, 13/2. The outputs of the senior (K-1) bits of the adders 10/1, 10/2 are connected to the summing inputs, and the outputs of the lower (K-1) bits of the adders 11/1, 11/2 are connected to the subtracting inputs of the adders 12/1. 12/2 respectively. The outputs of the sign bits of the adders 12/1, 12/2 are connected to another input of the corresponding single-bit adders 13/1, 13/2. The outputs of adders 13/1, 13 / 2. are connected to the inputs of the higher (K + 1) -th bits of the registers 9/1, 9/2, and the outputs K of the bits of the adders 10/1, 10/2 are connected to the inputs of the lowest bits of registers 9/1, 9/2, respectively. The outputs (K + 1) of bits of the register 9/1 are connected to one input group of the multiplier 15, the other group of inputs of which is connected to the code bus 17. The bus code 17 is equal to the ratio P 2 / P 1 of the electric reduction coefficients of the phase shifters 4/2 and 4 / 1. The outputs of the most significant (significant) bits of the adder module 11/3, 11/4 are connected to the same group of inputs of the adders 13/3, 13/4. The outputs of the lower matching bits of the adders 11/3, 11/4 are connected to the subtracting inputs of the adders 12/3, 12/4, respectively, the summing inputs of which are connected to the outputs of the higher bits of the adder 10/3 and register 9/2. The outputs of the sign bits of the adders 12/3, 12/4 are connected to the low order of the other group of inputs of the corresponding adders 13/3, 13/4. The remaining high-order bits of the other group of inputs of the adders 13/3, 13/4 are connected to a common bus (not shown in the drawing). The outputs of the adders 13/3, 13/4 are connected to the inputs of the high-order bits of the registers 9/3, 9/4, the outputs of the K-bits of the adder 10/3, the register 9/2 are connected to the inputs of the low-order bits of the registers 9/3 and 9/4 respectively. The outputs of all bits of the register 9/4 are connected to one input group of the multiplier 16, the other input group of which is connected to the code bus 18. The bus code 18 is equal to the ratio of RE / P2 of the electric reduction coefficients of the phase shifters 4/3 and 4/2.

The output of the pulse generator 1 is connected to the clock inputs of the pulse shapers of blocks 5 and 6, the clock inputs of the registers 22 of the memory block 14 and the clock 5 inputs of the registers of the block 9.

The outputs of the register 9/3 and the multiplier 16 are connected to the inputs of the pulp and paper mill 19

The converter operates as follows.

0 Generator 1 generates high-frequency pulses of frequency f ™. A ramp code with a frequency fn f ™ / 2K is generated at the outputs of the bits of the frequency divider 2. Shaper 3 produces

5 a sine wave AC signal of frequency fn to power the phase shifters of unit 4. At the outputs of each phase shifter of block 4, two AC signals of frequency fn are generated, shifted in

0 phase angle ± P a, where P is the coefficient of electrical reduction of the corresponding phase shifter. The shapers of block 5 generate pulses when passing through zero the output signals of the phase shifters of block 5 (for example, with a positive gradient), shifted in phase by an angle + Pa. The formers of block 6 generate pulses when passing through zero the output signals of the phase shifters of block 4.

0. phase-shifted angle -Pa. For the leading edges of the output pulses of the formers of block 5, the code of the frequency divider 2 is written into the corresponding registers of block 7, and for the leading edges of the output

5 pulses of the shapers of block 6; the divider 2 code is recorded in the corresponding registers of block 8. To avoid failures when writing the codes of the divider 2 to the registers of blocks 7 and 8 in the shapers of blocks 5 and 6

0, the generated pulses are synchronized by the signals of generator 1. In the adders of block 10, code differences (without taking into account the sign) of the corresponding registers of blocks 7 and 8 are generated.

5, the change of codes in the adders of block 10 is twice the rate of change of codes in the registers of blocks 7 and 8. This is equivalent to doubling the coefficient P of the electric reduction of the phase shifters of block 4. In the process of subtracting the codes in the adders of block 10, the error of offset of the input voltage of block 4 relative to divider code 2.

The converter does not have a start5 for adjusting the zero positions of the unit converters of block 4 with respect to each other, as well as the zero codes of the registers of blocks 7, 8 and the adders of block 10 with respect to each other. In adders 20 of unit 14, the adder 12/3 compares the low matching code of the adder 11/4 with the code of the equivalent high order adders 10/3. The sign of the difference Nioc-Niic from the output of the adder 12/3 is summed in the adder 13/3 with the code of the most significant bits of the adder 11/3. The result is summed from the outputs of the adder 13/3 is written by the front of the output pulse of the generator 1 to the highest bits of the mode 9/3, in the lower K bits of which the output code of the adder 10/3 is recorded. As a result, a complete transmitter output code is generated in register 9/3. The accuracy of the output code in registers 9/3 and 9/4 is determined by the accuracy of the codes in the adders 10/3 and 10/2, respectively. In the pulp and paper mill 19 digitally corrected technological errors by comparing the output codes of the multiplier 16 and register 9, highlighting higher spatial harmonic components and their compensation. The starting code can be any converter code corresponding to the accepted initial angular position. The initial code can be formed in the form of jumpers with buses of unit and zero potential and fed to the subtracting inputs of the adder, which is part of the pulp and paper mill; the output code of register 9/3 (register 9/2) is received at the summing inputs of this adder. The operation of the registers 22 of the block 14 and the registers of the block 9 can be carried out from the same edges of the output pulses of the generator 1 as the operation of the registers of the blocks 7 and 8 (for example, as is done in the shift register). To improve performance, block registers 7.8 can be triggered. 9/4 of register 22 of block 14/4 on one edge of the pulses of generator 1, and the operation of registers 9/1, 9/2, 9/3 and registers of 22 blocks of 14/1, 14/2, 14/3 - on other fronts, which is not essential to the achievement of the object of the invention, and therefore is not reflected in the drawing and in the claims.

During operation, all converter blocks, with the exception of the memory block 14, operate similarly to the described output code generation process. Block 14 only works on the reproduction of codes for subtracting inputs of adders of block 11. Since the outputs of block 14 are made in the form of jumpers with buses of unity and zero potential, the output information of block 14 is not erased with any supply voltage switches. In the adders of block 10, the current values of the K least significant bits of the codes corresponding to the rotation angles of the block growers of the block 4 are generated. In the adders 13/1 and 13/2, one leading bit is generated for the codes of the adders TO / 1 and 10/2. In registers 9/1 and 9/2, the current values (KI) of the bits of the angle codes of the phase shifters 4/1 and 4/2, independent from each other, are generated. Using blocks 15, 14/4. 11/4. 12/4, 13/4, register codes 9/1 and 9/2 are matched. In register 9/4, a consistent code of registers 9/1 and 9/2 is generated with discreteness

Date 2l: / P 1 2 1. Using blocks 16. 14/3, 11/3, 12/3 and 13/3, the codes of register 9/4 and the adder 10/3 are matched. The output code of the converter with discreteness is generated in the register 9/3

D (72 2 / P 3 2 k + 1. The range of the unique transmitter is 2 l / P1.

The advantage of the converter is its high accuracy, which is ensured by the high accuracy of code generation in adders 10/3. 10/2 and the possibility of mutual correction of codes 9/3 and multiplier 16 using CV K according to a known method. The absence of mechanical alignment of phase shifters and readings in each phase shifter simplifies the converter, providing the ability to quickly replace phase shifters and an electronic device during operation, expands the tolerances for instability of the power shaper, and the technological errors of phase shifters 4 / .1 and 4/2.

Claims (1)

SUMMARY OF THE INVENTION A converter of a shaft rotation angle into a code comprising a pulse generator, a frequency divider, a frequency divider, a power driver, the output of which is connected to the input of the phase shifter unit, one output group of the phase shifter unit is connected to the input group of the first pulse former unit, the outputs of which are connected to clock inputs of the first block of registers, characterized in that, in order to increase the accuracy and simplify the converter, the second block of pulse shapers, the second and the third block of registers, from the first to the fourth block of adders, the block of memory elements, the first and second multipliers, the first and second code buses, the other group of outputs of the block of phase shifters is connected to the group of inputs of the second block of pulse shapers, the outputs of which are connected to the clock inputs of the second register block, the information inputs of the first and second register blocks are connected to the outputs of the bits frequency divider, and the output groups of the first and second register blocks are connected in pairs to the input groups of the first adder block, the first, second and third output groups of the first adder block are connected to the first, second and third input groups of the memory element block, third adder block, respectively and the third block of registers, the first and second groups of outputs of the third block of registers are connected to the first groups of inputs, respectively, of the first and second multipliers, the second groups of inputs of which are connected respectively to the first and second code buses, the third group of outputs of the third block of registers is connected to the fourth groups of inputs of the block of memory elements, the third block of adders and the third block of registers, the first and second groups of outputs of the first block of registers, the groups of outputs of the second and first multipliers are connected respectively to the fifth , the sixth, seventh and eighth groups of inputs of the block of memory elements, to the first, second, third and fourth groups of inputs of the second block of adders, the group of inputs from the fifth to 2C Jl U m j fee /. 75 ttu.fttf v-t Z3 InE. gu AT i-xiij the eighth of which is connected respectively to the output groups from the first to the fourth block of memory elements, the output groups from the first to the fourth of the second adder block are connected to the input groups from the fifth to the eighth of the third adder block, the first to fourth outputs of which are connected to the first to fourth inputs the fourth of the fourth block of adders, the first and second outputs, the fifth and sixth groups of outputs of the second block of adders are connected respectively to the fifth and sixth inputs, the first and second groups of inputs of the fourth block of sums tori, the first and second outputs, the first and second groups of outputs of which are connected respectively to the first and second information inputs, to the fifth and sixth groups of inputs of the third block of registers, the fourth group of outputs of the third block of registers and the group of outputs of the second multiplier are the first and second groups the outputs of the converter, the output of the pulse generator is connected to the synchronizing inputs of the first and second blocks of the pulse shapers. W L ha .Tact j n g I I Xtj