RU1805461C - Unit for homogeneous structure - Google Patents

Abstract

The invention relates to computer technology and is intended to build homogeneous computing structures that perform parallel logical and arithmetic processing of data. An object of the invention is to expand the functionality of a cell by enabling the arithmetic division operation to be performed. The device comprises a one-bit adder, four AND elements, four OR elements, three BAN elements, four multiplexers with three control inputs, eight inputs and five outputs. The functionality of the cell allows the implementation of homogeneous structures for performing operations of calculating a logical function from to variables, counting the number of units in a binary vector, arithmetic addition, multiplication and division in a binary number system, binary vector vectors, commutation of information channels. Decisive gender based on the proposed cell can be implemented in the form of LSI and used in the construction of processors for mass processing of elements of vector data streams. 2 ill. Yo

Description

The invention relates to computer technology and is intended to build homogeneous computing structures that perform parallel logical and arithmetic processing of data.

The purpose of the invention is to expand the functionality by providing the arithmetic division operation.

In FIG. 1 shows a functional diagram of the proposed device; in FIG. 2 - an example of the operation of division in a homogeneous structure of the proposed cells (the table shows the reaction outputs

cells depending on the values of the input and control variables).

A cell of a homogeneous structure contains information inputs 1-5 (t, x, S, p, y), tuning inputs 6-8 (ki, Zi, Z2) information outputs 9-13 (S1, у. х, р1, t), adder 14, multiplexers 15-18, elements AND 19-22, elements OR 23-26, elements FORBIDDEN 27-29.

Inside the cell, the inputs 6, 7, 8 are connected respectively to the first, second and third control inputs of the elements 15-18, the outputs of which are respectively connected to the outputs 11,13,12 and 9 of the cell, the input 5 of which is connected to the output of 10 whose00

about eating

4 Os

ki, the second inputs of the elements And 20 and 21, the inverse input of the element 28 and 27, the output of the element 29, the direct input of which is connected to the input 7 of the cell, and the three inverse inputs are respectively connected to the input of 6 cells, the input of 8 cells and the output of the sum of the adder 14 which is also connected to the first input of the element 20, the output of which is connected to the input of the element 24, the second input of which is connected to the output of the element 27, the direct input of which is connected to the input 3 of the cell, the input of the first term of the adder 14, the first input of the element 22 and the second input element 26, first input which is connected to the second input of the element 22, the direct input of the element 28, the transfer input of the adder 14 and the input 4 of the cell, the input 2 of which is connected to the input of the first term of the adder 14, the second information input of the element 15, the third information input of the element 16, the first inputs of the elements 19 and 23, the outputs of which are respectively connected to the seventh and sixth information inputs of element 16, the fifth information input of which is connected to the zero bus line of the cell, respectively, with the second, fifth and third information inputs of elements 1 7, 18 and 15, the first information input of which is connected to the fourth information input of element 18, the input 1 of the cell, the second inputs of elements 19 and 23, the fourth information input of element 16, the second information input of which is connected to the output of the first term adder 14, and the first information output - with the output of element 24 and the second information input of element 18, the third and first information inputs of which are respectively connected to the input 3 of the cell and the output of element 22, the transfer output of the adder 14 is connected to the first electronic input ment 21 and the first data input element 17, the third and fourth information inputs of which are respectively connected to the output member 26 and output member 25, whose inputs are respectively connected to the outputs of elements 28 and 21.

Structural and circuit solutions of the elements used in the proposed technical solution are known and described in detail in the educational and scientific and technical literature.

The device operates as follows.

The operations implemented by the device are shown in the table. Depending on the values of the control signals K, Zi, Z2, respectively, received at the inputs of 6-8 cells,

organized in a homogeneous structure, as in the prototype device, the following data processing operations are implemented in a homogeneous structure. Upon receipt of the signal K-1 cell provides the implementation of functions

P, Pv.-s

x ZijZa x v Z21)

t1 Z- | Z2 x t v ZiZ2 (x v t) v ZiZ2t У У

T.O. functionally, the cell works identically to the prototype cell and provides the operations of calculating a logical function of n variables and counting the number of units in a binary vector is completely similar to performing these operations in the prototype.

Upon receipt of signals KZiZ2 000 cell ensures the formation of the following functions on the information outputs:

S1 Sy v Ay

p By v py x t

U u

As a result, in a homogeneous structure, similarly to the prototype device, the operations of arithmetic multiplication and addition of binary numbers, the operation of concatenation of two binary channel switching vectors are realized.

Unlike the prototype device, the proposed device further provides an implementation of the operation of arithmetic division of binary numbers, which is performed as follows. Arithmetic division of two binary numbers.

The problem that the device solves in this case is to form on the group of outputs y1 the quotient of dividing two positive integers, which respectively enter a homogeneous structure at the inputs x and S.

In this mode, the device operates as follows.

The dividend is supplied to m + 1 inputs S of a homogeneous structure, and the lowest bit of the dividend is fed to the input Si, .... to the input Sm is the highest bit of the dividend, and to the input Srn-H is the sign bit of the dividend. The divider is fed to the (q + 1) inputs x of a homogeneous structure in an additional code, with the sign bit of the divider (q + 1 bit) being sent to the input xt + 1 of the structure, the senior qth bit, .., xm-q input is the least significant bit of the divider. Accordingly, m + q

- the number of significant bits of the dividend and divider.

The adjustment of the structure to perform the division operation is performed as follows.

At the input to the structure, signal K0 is applied. At the tuning inputs Zi and Zz of the cells of the first m rows (m-q + 1), the signals are sent to the columns of the structure: Zi 1, Tz. 0. As a result of this, the first m cells implement the following functions:

 S1 t

I x x

{t Ay v Sy

p in

U y

To the tuning inputs of the cells (t + 1)

the rows and (m + q - 1-m) columns are fed with signals Zi 1, Z2 - 0, where n is the number of columns. As a result, the functions are implemented in the listed cells:

S1 S1

x x

Mr. GA

p is 0.

A

Any signals Zi and Z2, except for signals Zi 1, 7.2 0, are supplied to the tuned inputs of the remaining cells.

As a result of such a setting, the sign values of the divisible and divisor are constantly generated at the outputs of the x cells of the (m + 1) -th row. At the outputs x of lines 1 through m, the original values of the divider bits are generated. At the outputs of the cells of the (m + 1) th line, an inverse value of the result of adding the divisor and dividend digits to mod 2 to the mod 2 is formed taking into account the transfer values from the previous line. The outputs of S cells 1 through m of the row of n (m-q + 1) columns are switched by the signals from the inputs of t cells, the output signal p generates a transfer signal based on the addition of mod 2 variables at the inputs S and x, the output signal c is switched of the input at the output t, the sum value is generated over mod 2 of the variables at the inputs x and S at y 1 or the variable is switched from the input S. At the outputs S of the cells in the columns, the signals are generated at the inputs S. At the outputs y1 of the remaining cells of the structure are formed the values of the signals at their y inputs.

Upon receipt of the dividend and divider respectively at the inputs S and inputs x of the first column at the S-inputs, a concatenation of the first remainder of the division and the remaining bits of the dividend with a shift by one position

when forming at the output of the (1, t + 1) -th cell, the values of 1, otherwise, at the outputs S1 of the indicated cells, values of the dividend are formed with a shift of one

position down. At the output of the (1, m + 1) -th cell, the value of 1 is formed only if the value of the sum over mod 2 of the sign bits of the divisible and divisor, taking into account the received transfer

0, the sum of the leading bits of the divisible and the divisor by mod 2 is equal to 0. As a result, the signal controlling the output of S1 cells of the first column m

5 lines. Similar processes occur in the (m-q + lHi) column of the (t + 1) -th row. Upon completion of transients, the outputs of the cells of the (t + 1) -th row (m-q + 1) columns will form a quotient which through the cells (m + 2), (m + 3), ... - rows will go to the outputs of a homogeneous structure, with the leading bit of the quotient being formed at the output of the first column. At the outputs of 3 cells of the n - column (mq), (m-q + 1), ..., (m) lines, the remainder of the division is formed, the high-order bit of which is formed at the output of the m-line. Thus, in the proposed device, all operations are implemented, implemented in the prior art device, and

0, the operation of dividing binary numbers is additionally performed, which allows to expand the scope of the device. In addition, the expansion of the functionality of the device is achieved without

Claims (1)

5 increasing the number of external leads. SUMMARY OF THE INVENTION A homogeneous cell containing an adder, two multiplexers, four AND elements, four OR elements, and three 0 of the element is PROHIBITED, and the first information input of the cell is connected to the first information input of the first multiplexer, the first information input of the second multiplexer, the first 5 inputs of the first elements AND and OR, the outputs of which are respectively connected to the second and third information inputs of the first multiplexer, the fourth information input of which is connected to 0 zero bus of the cell, the first and second tuning inputs of which are connected respectively with the first and second control inputs of the first multiplexer, the second tuning input of the cell 5 is connected to the first control input of the second multiplexer, the second information input of which is connected to the second information input of the cell, the second inputs of the first elements AND and OR, the input of the first term of the adder, the input of the second term of which is connected to the third information input of the cell, the first input of the second element And and the direct input of the first element BAN, the inverse input of which is connected to the fourth information input of the cell, the inverse input of the second element BAN, the first information output , the first input of the second element OR is connected to the output of the first element FORBID, the direct input of the second element FORBID is connected to the second input of the second element AND, the fifth information input of the cell and the transfer input of the adder, the third tuning input of the cell is connected to the first inverse input of the third element FORBID, characterized in that, in order to expand the functionality of the cell by providing the arithmetic division operation, the third and fourth multiplexers are introduced into it, the first one being tuned the first input of the cell is connected to the first control inputs of the third and fourth multiplexers, the second control inputs of which are connected to the second control input of the second multiplexer and the second tuning input of the cell, the third tuning input of which is connected to the third control inputs of the first to fourth multiplexers, the first information the cell output is connected via a wiring OR with the output of the third element BAN, the second inverse input and the direct input of which are connected respectively to the first and second training cell input, a third inverting input of the third element is connected to the inverted fifth informational input of the first multiplexer, the adder sum output and the first input of the third AND gate, a second input coupled to a fourth information input of the cell, the second information input of which is connected to the sixth information input of the first multiplexer, the output of which is connected to the second information output of the cell, the seventh information input of the first multiplexer is connected to the output of the second OR element and the first information input of the fourth multiplexer, the second information input of which is connected to the zero bus line of the cell, the first information input of the third and third information input of the second multiplexers, the third, fourth and fifth the information inputs of the fourth multiplexer are connected respectively to the third and first information inputs of the cell and the output of the second element And, and the output of the fourth multiplexer is connected to the third information output of the cell, the adder transfer output - with the first input of the fourth AND element and the second information input of the third multiplexer, the output of which is connected to the fourth information output of the cell, the third information input of the third multiplexer is connected to the output of the third OR element, the fourth information input of the third multiplexer is connected to the output of the fourth OR element, the first and second inputs of which are respectively connected to the third and fifth information inputs of the cell, the output of the second element is FORBID connected to the first input of the third OR element, the second input of which is connected to the output of the fourth element AND, the second input of which is connected to the fourth information the input of the cell, the output of the third element AND is connected to the second input of the second OR element, the output of the second multiplexer - with the fifth information output of the cell. 45 7 V (2,) 8 10 (y) FIG.