RU1803881C - Digital spectrum analyzer - Google Patents

Abstract

The invention relates to an information measurement technique for determining the spectral power density of an input electrical signal. This goal is achieved by introducing into the device a numerical input unit 12, two decoders 13, 14, blocks 15, 16, 22, 23, 26, 32, 33, multiplying memory blocks 17, 18, dividing block 20, inverter blocks 19, 34 , adders 24, 25, 35, switches 27, 29, storage registers 21.28, 30 and shift and storage register 31. The device also consists of ADC 1, multiplication units, an adder, a memory unit, an accumulation unit, a control unit, a cosine generator, and a spectral component calculation unit. 2 ill.

Description

The invention relates to specialized means of information measurement technology and is intended to study the frequency properties of random processes.

The purpose of the invention is to increase the accuracy of the analyzer.

In FIG. 1 shows a block diagram of a digital spectrum analyzer; in FIG. 2 is a block diagram of a weighting block.

A digital spectrum analyzer contains (see Fig. 1) an analog-to-digital converter 1, a multiplication unit 2, a weighting unit 3, an adder 4, a memory unit 5, a multiplication unit 6, a cosine generator 7, a multiplication unit 8, an accumulation unit 9 , a spectral component calculating unit 10, a control unit 11, a numerical value input unit 12.

Block 3 weights contains (see Fig. 2) decoders 13, 14, blocks 15, 16 multiplication, blocks 17, 18 memory, block 19 inverters, block 20 division, register 21

storage, multiplication blocks 22.23, adders 24, 25, multiplication block 26, switch 27, channels, storage register 28, channel switch 29, storage register 30, shift and storage register 31, multiplication blocks 32, 33, inverter unit 34 and adder 35.

Digital spectrum analyzer operates as follows. Before the start of the analyzer operation, the counter of the address of memory unit 5 and the registers of accumulation unit 9 are reset. From the keyboard of the numerical input unit 12, a numerical coefficient / is set. defining the width of the correlation window.

The start and sampling of l (n 1, N) is synchronized by the control unit 11, which sets the cycle time of the formation of the digital word Xn by the analog-to-digital converter 1. The multiplication block 2 multiplies the output signal Xn of the analog-to-digital converter 1 and

signal Wn 2 hm-1 I -Ya2 hm-2 block 3 weighting factors, generating a signal Qn

ate

WITH

| 00

about gj

00

00

 XnWn, which in adder 4 together with the samples (pn from memory block 5 serves to generate the output signal Jnk - 9 - UL - 2. The value of each sample (p from memory block 5 is determined by the signal Ck

 cos -r- k cosine generator 7, corresponding to the Kth spectral component and the recurrence relation pn Ck pn - 1 - kn - 2 + Q. Multiplication block 8

generates a signal i / Ј JnkQn, which enters the accumulation unit 9, which sums the value t / ft 3a N operation cycles and

m

17 k- t-rn Sv

generates an input signal Zn

n 1

 Zm-ik + $ n Z0k 0; m TTN} for spectral component block 10,

the output signal Sk of which is an estimate of the power spectral density for the Kth component of the spectrum of the signal under study.

The output signal Wn of the weighting unit 3 is obtained at the output of the adder 35 as a difference signal hm

 2 hm-iA - Я2 hm-2. For this, the control unit 11 sets a digital code that determines the sampling interval At, which, together with the code that determines the width of the correlation window / and is set from the keyboard in the block 12 for inputting numerical values, enters the inputs of the decoders 13, 14 and generates them at the outputs addresses of cells of memory blocks 17, 18 that contain a digital code of values A0 and

- / HWP I am irrespective. Switches

27.29 are initially set to receive data from the first channel. At the end of the work cycle, the switches 27 and 29 are switched. At the same time, information signals from the control unit 11 and the numerical input unit 12 are fixed by the buffer registers of the first and second inputs of the multiplication unit 16, which multiplies and outputs the result Ui6 / J At, when a resolution signal is received operation (control signals are not shown in Fig. 2). The byte of the value of AO thus selected from the memory block 17 is supplied to the inputs of four blocks at once: to the second input 15 of the multiplication block, to the second input of the division block 20, to the first input of the multiplication block 22 and to the input of the storage register 21. At I, the input of block 15 of the multiplication comes from the output of the analog-digital pre0

educator 1 discretized input signal X (t). The output of the multiplication unit 15 through the inverter unit 19 is connected to the first input of the adder 24, the second input of which is connected to the output of the division unit 20. The byte of the value I, read from the memory block 18, is supplied to both inputs of the multiplication block 23, the output of which byte 1) 23 Я2 is sent to the second input of the multiplication block 22 and to the second input of the multiplication block 32, where it is fixed by the input buffer registers of each of blocks. If the output of the adder 24 resulting

At / 3 l - r-1- - A0x, incoming 5 signals 1) 24 Ar

 W

first through the channel switch 27 to the buffer register of the first input of the multiplying unit 32 and simultaneously entering the first input of the adder 25, permission signals are transmitted to transmit data from the storage register 21 to the second input of the adder 25 and outputting the multiplication result from the multiplying unit 22 to the third input of the same adder. The output signal of the adder 25 1) 25 AI + AO (1 + Я2) arrives at the first input of the multiplication block 26, in the buffer register of the second input of which the previously selected Uie Я from the memory block 18 was recorded, also recorded in the shift and storage register 31 . From the output of the multiplication unit 26, the signal U26 hi + A0 (1 + II) passes through the channel switch 29 and enters the storage register 30, which, without fixing, transfers it to the first input of the multiplication unit 33 and the intermediate storage register 28. The appearance of the signal U26 at the outputs of the register 30 results in the simultaneous issuance of an operation enable signal for the multiplier 32 and for the shift and storage register 31. The output signal of the latter, containing the value Uai 2 I, obtained by shifting the input byte one bit to the left, comes to the second input of the multiplication block 33, the output of which the signal Uzz 2 I hi goes to the second input of the adder 35, the first input of which passes through block 34 inverters the output signal of block 32 of the multiplication U32 AI ZA2. The appearance of the signal Uss Wn 2 hi Я-Я2 h0 at the output of the adder 35 means the end of the first cycle of operation. Channel switches 27 and 29 switch to the state of selecting data from the second channel and remain so until a new signal of initialization and initialization of the spectrum analyzer is received. Thus, the output signal 1) s5 of the adder 35 passed through the second channel 29 of the channel switch is stored in the intermediate storage register 30 and

0

5

0

5

0

5

0

5

appears on its output only after the data hi in the register 28, having passed through the second channel of the switch 27, is stored in the buffer register of the first input of the multiplying unit 32. In the buffer register of the second input of the multiplication unit 32, a byte is stored corresponding to the new sample I from the memory unit 18 for the second cycle and passed through the multiplication unit 23. The same sample for the second cycle from the memory unit 18 is stored in the shift and storage register 3. The output of register 30 from ha, as in the first cycle, permits operation for the multiplier 32 and the shift and storage register 31.

Claims (1)

SUMMARY OF THE INVENTION A digital spectrum analyzer comprising three multiplication units, an adder, the first input of which is connected to the output of the first multiplication unit, the first output is connected to the first input of the second multiplication unit, the output of which is connected to the information input of the storage unit, connected to the input of the spectral component calculation unit the output of which is connected to the output of the analyzer, the cosine generator, which is connected to the first input of the third multiplication unit, connected by the second input to the first output of the memory unit, and the output is its multiplication unit is connected to the first input of the memory unit, the second input of which is connected to the second output of the adder, and the second output of the memory unit is connected to the second input of the adder, an analog-to-digital converter, the input of which is connected to the input of the analyzer, and the output is connected to the first input the first block of multiplication, the output of the latter is also connected to the second input of the second block of multiplication, the control unit, the first output connected to the control input of the analog-to-digital converter, the second output to the synchronization input block ka accumulation, third an output to the third input of the memory unit, characterized in that, in order to increase the accuracy of the analysis, series-connected input unit of numerical values, the fourth multiplication unit, the division unit, the second adder, the first channel switch, the fifth multiplication unit, the first unit are introduced into it inverters and a third adder connected in series the fifth multiplication unit, and the second inverter unit, connected in series with the first decoder, the second memory unit, the first storage register, the fourth adder, the sixth multiplication unit, the second channel switcher, the second storage register and the seventh multiplication unit, connected in series with the second decoder, the third unit memory, the eighth block of multiplication, and the ninth block of multiplication, as well as the third the storage register and the shift and storage register, the output of which is connected to the second input of the seventh multiplication unit, and the input to the second inputs of the sixth and eighth multiplication units, the output of the latter is connected to the second input of the fifth multiplication unit, the second input of the third adder to the output of the seventh unit multiplication, and the output of the third adder to the second input of the second channel switch, the first inputs decoders are connected to the output of the numerical input unit, and the second inputs to the output of the control unit and the second input of the fourth multiplication unit, the first input of the fifth multiplication unit is connected to the output of the analog-to-digital converter, the second input to the second inputs of the division unit and the ninth multiplication unit the output of which is connected to the second input of the fourth adder, the third input connected to the output of the second adder, the second input of which is connected to the output of the second block of inverters, and the output of the second storage register through t ety storage register connected to the second input of the first switch. Figs Editor G. Melnikova Compiled by L. Ustinova Tehred M. Morgenthal Corrector N. Revska