RU1788575C - Device for pulse synchronization - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for forming and processing information. The device contains 2 triggers, 2 keys with memory of the control signal, 1 control bus. 1 clock bus, 3 output buses. 9 ill.

Description

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The invention relates to a pulse technique and can be used in devices for forming and processing information.

A device for synchronizing pulses is known, comprising a first trigger whose S input is connected to an input bus, an inverse output is connected to an R input of a second trigger, whose direct output is connected to an output bus, a clock bus.

A pulse synchronization device is known, comprising a first trigger, the S-input of which is connected to the input bus, a second trigger, a clock bus, and an output bus.

A common disadvantage of the known devices is the design complexity, which is due to the significant amount of hardware required for their implementation. This drawback provides known devices with low reliability indicators in terms of the number of possible failures.

The closest in technical essence to the proposed one is a device for synchronizing pulses, comprising a first trigger, the R-input of which is connected to the first output bus, a clock pulse bus that is connected to the information inputs of the first and second keys with the memory of the control signal, the first control inputs of which connected, control bus.

The disadvantage of this device is the narrow functionality, since it does not provide the formation of a series of pulses with a duration proportional to the duration of the control pulse. .

The aim of the invention is to expand the functionality by generating both single and a series of pulses of duration proportional to the duration of the control pulse.

This goal is achieved in that in a device for synchronizing pulses containing a first trigger, the R-input of which is connected to the first output bus, a clock pulse bus that is connected to the information inputs of the first and second keys with storing the control signal, the first control inputs of which are connected, control bus, the second and third output buses are introduced, the second trigger, whose direct output is connected to the first output bus, the R-input - with the inverse output of the first trigger, and the output of the first key is memorized Niemi signal

control is connected to the second output bus and to the first S-inputs of the first and second triggers, the second S-inputs of which are connected to the third output bus and

the output of the second key with the memory of the control signal, the first control input of which is connected to the direct output of the first trigger, the third S-input of which is connected to the control bus and to the second

0 control inputs of the first and second keys with memory control signal.

In FIG. 1 is an electrical functional diagram of an apparatus for synchronizing pulses; on the

5 of FIG. 2-5-time diagrams explaining the operation of the device for different durations of the control pulse and various temporary positions of the control pulse relative to

0 clock pulses; in FIG. 6 is an electrical functional diagram of a key with storing a control signal having a direct information input C and two control inputs V; in FIG. 7 - temporary

5 diagrams explaining the general rule of functioning of this key at the level of its interface; in FIG. 8 is an electrical functional diagram of a key with storing a control signal having an inverse information input C and two control inputs V; in FIG. 9 are timing diagrams explaining the general rule of functioning of this key at the level of its interface.

5 The device for synchronizing pulses contains the first trigger 1, the first and second keys 2 and 3 with memory control signal, the second trigger 4, the control bus 5, bus 6 clock pulses, the first

0 7. second 8 and third 9 output buses.

The first S-input of trigger 1 is connected to the output of the key 2, with bus 8 and the first S-input of trigger 4, the second S-input of which is connected to the second S-input of trigger 1,

5 with bus 9 and with the output of key 3, the information input of which is connected to bus 6 and with the information input of key 2, the first control input of which is connected to the direct output of trigger 1 and with the first input

0 control key 3, the second control input of which is connected to the second control input of key 2, with bus 5 and with the third S-input of trigger 1, whose inverse output is connected to the R-input of trigger 4, direct 5 of which is connected to the R-input trigger 1 and with bus 7.

A device for synchronizing pulses operates as follows.

In the initial state, triggers 1 and 4 are in a state on buses 5 (diagram a), 7-9 (diagrams railways, e) the levels are acting on bus 6 (diagram 6), a highly stable clock signal. Due to the well-known, requirement 6 of the necessity of forced installation of sequential elements in one of the stable states after applying the supply voltage to them, the initial installation bus and additional R-inputs of triggers 1 and 4, by which the initial state is set the device of FIG. 1 are not shown.

The control pulse arrives at bus 5 and switches to state 1 trigger 1 at its third S-input. In this case, at the direct (diagram c) and inverse (diagram d) outputs of trigger 1, levels 1 and O are set, respectively.

If the front of the control pulse arrives on bus 5 during an inter-pulse pause (level O) in the clock signal on bus 6, then in accordance with the rule of operation of key 2 (Fig. 7), the closest clock pulse is then transmitted to the output of key 2 and is allocated on the bus 8, and at the output of the key 3 at the moment of changing the state of the trigger 1, the pulse is not generated (Fig. 9). The pulse from the output of key 2 causes switching to state 1 of trigger 4 at its first S-input, which ensures the formation of the front of the output pulse on bus 7. Under the action of level 1, received at the R-input of trigger 1, at the direct output of this trigger and level O is set at the first control inputs of keys 2 and 3. However, level O continues to be stored at its inverse output, due to the action of level 1 at its first S-input.

If the front of the control pulse arrives on bus 5 during the action of the pulse (level 1) in the clock signal on bus b, then in accordance with the rule of key 3 operation (Fig. 9), the nearest inter-pulse pause of the clock signal is inverted key 3, is transmitted in the form of a pulse to its output and is allocated on the bus 9, and the output of the key 2 at the time of changing the state of trigger 1, the pulse is not generated (Fig. 7). The pulse from the output of the key causes switching to state 1 of trigger 4 at its second S-input, which ensures the formation of the front of the output pulse on bus 7. Under the action of level 1, which is received at the R-input of trigger 1, at the direct output of this trigger and at the first control inputs of keys 2 and 3, level O is set. However, at its inverse output,

level O, due to the action of level 1 at its second S-input.

In this case, if the slice of the control pulse on the bus 5 is formed earlier, 5 than the slice of the first output pulse of the key 2 (key 3), then the trigger 1 by the slice of the pulse at the first (second) S-input is set to O, since its R-input is active at this time level 1, level

0 G from the inverted output of trigger 1 goes to the R-input of trigger 4 and switches it to state 0. At the same time, a cut of the output pulse is formed on bus 7 and the device returns to its original state.

5 If, however, a slice of a control pulse on bus 5 is formed later than a slice of the first output pulse of key 2 (key 3), then keys 2 and 3 select at their outputs a series of pulses with the number of pulses proportional to the duration of the control pulse. In this case, the pulses allocated on the bus 8 are generated from the pulses of the clock signal, and the pulses allocated on the bus 9 are formed from the pauses

5 clock signal. By cutting the control pulse at the third S-trigger 1 and at the second inputs of the control keys 2 and 3, level O is set, since at this moment in time the first inputs of the control keys 2 and 3 also have level O, both keys stop the process converting the duration of the control pulse into a series of pulses at their outputs. As a result of this, by cutting the last pulse generated at the outputs of the keys 2 or 3, trigger 1 switches to state O, since level 1 is active at its R input at this time. Level 1 from the inverse output of trigger 1 enters

0 to the R-input of trigger 4 and sets it to state O. In this case, a cut of the output pulse is formed on bus 7 and the device returns to its original state. Thus, the supply of a control pulse to bus 5 leads to the fact that a single pulse is emitted on bus 7, the duration of which is determined by the duration of the control pulse, and the front and slice are always synchronized by the clock signal of bus 6. In addition, on the buses 8 and 9, series of pulses are generated with a series duration proportional to the duration of the control pulse.

Claims (1)

5 Claims The pulse synchronization device containing the first trigger, the R-input of which. connected to the first output bus, a clock bus, which is connected to the information inputs of the first and second keys with storing a control signal, the first control inputs of which are connected, a control bus, characterized in that, in order to expand the functionality by forming as single pulses , and series of pulses with a duration proportional to the duration of the control pulse, depending on the duration of the control signal, the second and third output buses are introduced into it, the second three heger, whose direct output is connected to the first output bus. R-input - with the inverse output of the first trigger, and the output of the first key with storing the control signal is connected to the second output bus and to the first S-inputs of the first and second flip-flops, the second S-inputs of which are connected to the third output bus and to the output of the second key with storing the control signal, the first control input of which is connected to the direct output of the first a trigger, the third S-input of which is connected to the control bus and to the second control inputs of the first and second keys with the memory of the control signal. Fce.b Figure 5 FIG. 6 W W FIG. 8