RU1784978C - Pseudostohastic sequence generator-analyzer - Google Patents

Abstract

The invention relates to tf computing and measurement technology. Its use in devices for measuring fidelity of information transmission in Digital Communication Channels (CCS) allows to increase noise immunity. This is achieved by generating a complex pseudorandom sequence (PSP) composed of two PSPs with periods of different sizes (the minimum possible and required), as well as by providing the possibility of analyzing this complex test PSP for errors during the passage of the CCS. 2 ill.

Description

The invention relates to computing and radio engineering and can be used in devices for measuring fidelity of information transmission in digital communication channels (CCS).

The pseudo-random sequence generator-analyzer (GAPSP) solves the following problems: generating and issuing a pseudo-random sequence (PSP) for use as a test sequence and applying it to the test CSC when checking the quality of the CKS or other control object: receiving the CPS that passed the CKS; formation of internal memory bandwidth in the error analyzer; synchronizing the internal memory bandwidth with the input external memory bandwidth; isolating errors from the input SRP by comparing the input external and internal SRP in an error analyzer; counting the number of errors by the error counter.

As a test PSP, the maximum length PSP (PSMPD) is most often used.

A well-known pulse code sequence analyzer comprising an error selector, an error counter, a control unit, an OR element, an RS trigger, two D triggers. The disadvantage of this analyzer is the need for a separate SRP generator.

The closest analogue is the SRP generator analyzer. comprising a control unit, the first output of which is connected to the input of the clock generator, the output of which is connected to the clock input of the first & shift register and is the clock output of the analyzer-generator, the second output of the control unit is connected to the installation input of the first shift register, the first outputs

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a great deal

of which are connected to the first information inputs of the first switch, the outputs of which are connected to the inputs of the first adder modulo two, the output of which is connected to the information input of the first shift register, the second outputs of which are connected to the information inputs of the first decoder, the first output of which is the geyser synchronization analyzer, first. a trigger whose D-exdS is the information input of the analyzer generator, the direct output of the first trigger is connected to the first inputs of the comparator and the second adder modulo two, the C-input of the first trigger is combined with the clock input of the second shift register and the counting input of the first counter and is the clock input of the analyzer generator, the first outputs of the second shift register are connected to the first information inputs of the second switch, the outputs of which are connected to the inputs of the third adder modulo two, the output of which is connected inen with the first input of the fourth adder modulo RHEED and the second input of the comparator, the output of which is connected to the D-input of the second trigger, the direct output of which is connected to the second input of the second adder modulo two, the output of which is connected to the second input of the fourth adder modulo two, the third outputs of the control unit are connected to the second information inputs of the first and second switches, the fourth output of the control unit and the output of the fourth adder are modulo two connected to the R-input of the third trigger, the direct output of which о is connected to the R-input of the fourth and S-input of the fifth trigger and the zero input of the first counter, the overflow output of which is connected to the C-input of the fourth trigger, the direct and inverse outputs of the fifth trigger are connected respectively to the first input of the first element OR and S-input of the third trigger. The disadvantage of the prototype is the low noise immunity due to the inability to synchronize the error detector

prototype when receiving input external

Y PSMD with error coefficient Kosh -k-,

where n is the number of bits (length) of the shift register, i.e. when on average at least one error occurs for every 2p clock intervals of the input memory bandwidth. Moreover, in order for synchronization of the prototype error detector to occur, it is necessary to have 2n error-free clock intervals of the input memory bandwidth received from the DSS (n clock intervals are spent on the second synchronization stage, and another 5 clock intervals on the third). Since at К0ш-о гГ the presence of 2n

Since the error intervals of the input SRP are very rare, the prototype error detector may be in a state of desynchronization for an indefinite period of time.

The purpose of the invention is to increase the noise-immunity of GAPSP by providing the generation of a test SRP of a complex form, composed of two SRPs with periods of different sizes, the first - with the minimum possible period Lmin 2Prn1 - 1 and the second - with the required period of SRP, issuing this test SRP in CCS and by providing the ability to analyze this complex test memory bandwidth, passed 11

 detector

5

0

5

0

5

0

5

0

5

Shay CCS, - Kosh „

GAPSP analyzer errors.

Figure 1 shows a functional diagram of a generator-analyzer SRP. Figure 2 presents the timing diagrams of his work,

The analyzer generator contains a control unit 1, a clock generator 2, a first shift register 3, a first switch 4, a first adder 5 modulo two, a first decoder b, a first trigger 7, a comparator 8, a second trigger 9, and a second adder 10 modulo two, the second shift register 11, the second switch 12, the third 13 and the fourth 14 adders modulo two, the third trigger 15, the first counter 16, the fourth 17 and the fifth 18 triggers, the second counter 19, the fifth adder 20 modulo two, the third counter 21, sixth 22 and seventh 23 triggers, first element OR 24, element And 25 , the sixth adder 26 modulo two, the second decoder 27, the second element OR 28, the fourth counter 29, the eighth 30 and the ninth 31 triggers, the third switch 32, the fifth counter 33, the fourth switch 34, the sixth counter 35, the fifth switch 36 , PSP 37 generator, PSP 38 analyzer.

The first counter of 16 clocks has a counting module n + 1, the third counter of small periods has a counting module K, the fourth and fifth counters 29.33 have counting modules I, 0 I is a whole and (1+ a), 0: Ј a is a whole accordingly, the sixth clock counter has a count module t, 0 t is an integer. The control unit 1 is made similar to the control unit of the prototype.

The work of GAPSP is as follows.

After turning on the GAPSP using control unit 1 (built-in keyboard

microcomputers, control buttons, setup registers), the selected operating modes are established - generation of the PSMPD of the required period, structure and error analysis. In this case, from the control unit 1 to the switches 4 and 12, which switch the connection points of the adders 5 and 13 modulo two to the shift registers 3 and 11, respectively, at the same time the same parallel feedback enable code is issued, which include the elements EXCLUSIVE OR adders 5 and 13, modulo two, for forming the 3.11 PSMD shift registers with the same required structure and period and the same PSMD of the same minimum (small) period. At the same time, which PSMSD (small or required period) will be generated by shift register 3, at a given time depends on the state of trigger 23 at that moment and shift register 11 on the state of trigger 31, which are set to the initial zero state by setting pulses the PSP 37 generator and the RSP 38 analyzer from the outputs of the control unit 1, respectively, simultaneously when the START button of the control unit 1 is pressed and the generation of a small period PSPMD is started.

A parallel control code for setting the selected value of the frequency of the clock pulses is issued to the clock generator 2 from the control unit. From the output of the control unit 1 to the counter 21, an allelic code pair of the selected number of small periods K PDMD is issued. From the outputs of the control unit 1 to the switch 34, the switch 36, the counter 29, the switch 32 are issued parallel codes of control signals by installing the counting modules m, (n + 1),, (1+ a) counters 35, 16, 29, 33, respectively, which can be set different for PSMD of small and required periods and are selected by the operator based on the expected interference situation in the CCS.

The installation pulses of the generator and analyzer also arrive at the shift registers 3 and 11, respectively, setting them to the initial state 0 ..01 and allowing them to work. Clock pulses from the output of the generator 2 clock pulses. PSMPD from the output of the adder 5 modulo two through the adder 20 modulo two and the SYNC pulses from the decoder 6 are issued to the outputs of the GAPSP. Moreover, during the duration of issuing (K-1) small periods of the PSMPD, the adder 20 modulo two operates as an OR element, skipping the PSMPD to the output without inversion, since

one of its inputs receives the voltage log. O from the direct output of the sixth flip-flop 22, which is set to its initial state by a setting pulse. The number of past 5 periods is counted by the counter 21, counting the pulses generated by the decoder 6 at the moments when the shift register 3 is set to the initial state.

After (K-1) small periods

0 of the issued PSMD at the output of the counter 21 there is a pulse that sets the sixth trigger 22 to the state of log.1, which from its direct output is fed to the input of the adder 20 modulo two, causing

5 inversion of the issued PSMPD. After the end of the inverse small period of the PSMPD, the next pulse from the decoder 6 is set by the leading edge of the trigger 23, the input D of which at this time is supplied

0 log. 1, to the state log. 1, which causes, using the switch 4, the adder 5 modulo two is connected to the necessary points (bit outputs) of the shift register 3 in order to generate the PDMSD of the required peri5 and from the initial state 0 ... 01, and, in addition, through the OR element 24, sets the trigger 22 to the state of log.O, prohibiting the inverse of the output PSMPD.

PSMPD as a test is served

0 to the test CSC, clock pulses are fed to the clock input of the error analyzer in the loopback error analysis mode.

The operation of the GAPSP analyzer can be divided into three cycles: synchronization of the internal PSPMD of a small period of the analyzer error detector with the input external PSPMD of the same period with the stages of initial setup, phase shift of internal0. early PSMPD with allocated error pulses, checking for the absence of false synchronization; waiting for a packet of errors in the last small period of the PSPMD caused by the inversion of the output PSPMD of the generator; analysis of the input PSPMD required (large) period and structure.

The analyzer setup pulse sets triggers 15, 17, 18, counters

0 16, 33, 35 to the initial state, in which at the output of counters 16, 35, at the direct output of trigger 17, the log level is set. О, and at the direct output of trigger 18 the level is log, 1, triggers 30, 31 are also set 5 to the initial zero state. At the same time, at the output of trigger 15 and counter 33, a log level O is set, which allows counter 16 to count clock cycles. The counter module of counter 35, equal to the number m (0 m is an integer), and the counter module of counter 33, equal to

the number (1+ a), where 0 a is an integer, are set by the control signals from the switches 34 and 32, respectively, which are switched at that moment to their outputs control signals corresponding to the numbers selected for a small period of the PSMD. Similarly, the counter module of counter 16 is set to (rtmin + 1).

Comparator 8 begins comparing the input external PSPMD with a small period and the internal PSPMD formed at the output of the adder 13 modulo two of the same period and structure, but phase shifted by a number of clock cycles. In this case, the error pulses from the output of the comparator 8 are passed to the error counter 33 and to the I 25 element. The I 25 element is opened by log levels 1 from the inverse output of the trigger 17 and the direct output of the trigger 18. Therefore, the error pulses will affect the register shift 11 through the adder 26 modulo two until the counter 16 does not count the number of clock pulses to (nmin + 1). If, in this case, error-free information is recorded in the shift register 11, i.e. the shift register of the error detector enters into synchronism with the shift register 3 at the transmitting end, then at the next stage of checking for the absence of false synchronization, when the inverse output of the trigger 17 is set to logical 0 and the clock count will be allowed to the counter 35 and the error count to the counter 33, and the AND element 25 will be closed, counter 33 for the number of clock periods mmin (for a small period of the PSMP), if mmm and (1 + “min) are correctly selected, will not count its own account module (1 + sp) (with the expected distribution of errors in the input PSP) . At the output of counter 35, a pulse is detected that sets the log. О at the direct output of trigger 18, which closes the And 25 element and allows the passage of pulses from decoder 27 to counter 29 to set it to zero, while in between with these pulses, the counter 29 is allowed to count errors from the output of comparator 8. i.e. the third synchronization step will end.

If at the second synchronization step at least one error is recorded in the shift register 11 that is received in the input memory bandwidth, then at the third synchronization step, the counter 33 for the number of clock periods nrimin will have time to calculate up to its counting module (1 + ctmin) and a positive pulse on the output will set the analyzer error detector circuit to its initial state. Such a process is repeated until the shift register 11 of the analyzer enters

synchronism with the shift register 3 of the generator at the transmitting end of the CSC. After that, the GAPSP analyzer enters the waiting cycle of the error packet.

In this operation cycle, with the correctly selected counting module I (0 I - integer), the counter 29 during the time between pulses from the decoder 27 does not have time to calculate the number of errors from the comparator 8 to its counting module, and the triggers 30, 31 are in their initial zero state nii. When an error packet arrives from comparator 8 caused by the inversion of one last small period of the PSPMD generator, then the counter 29, before the next pulse from the decoder 27, has time to calculate the errors to its account module I, and at its output there is a pulse that sets trigger 30 to Log 1, which is fed to the D-input of trigger 31. The pulse that comes after this from the decoder 27 to the C-input of trigger 31 sets it to the state log, 1, and from its inverse output, the resolving potential goes to counter 19, letting him account osh and on the switches 12, 32, 34, 36, allowing the necessary bits of the shift register 11 to be connected to the adder 13 modulo two, which allows the shift register 11 to generate the PSMD of the selected structure and large period, and allowing the switches to install the corresponding selected account modules counters 33, 35.16 for PSMPD large period,

At this point, the waiting cycle ended and the analysis cycle of the input PSPMD from the CCS of a large period began,

During normal operation of the error detector, the information at both inputs of the adder 14 modulo two coincides, since errors in the input SRP are corrected by a comparator 8, trigger 9, and adder 10 modulo two. therefore, a log is generated at the output of adder 14 modulo two. If during the normal functioning of the error detector a malfunction occurs in the shift register 11, at the output of the adder 14 modulo two pulses are generated that affect the logic zero input of the trigger 15 and set the log. On its output, the counter 16 will start working, and analyzer error detector will again proceed to the second stage of operation during synchronization - recording information, then to the third stage, etc. until the error detector resynchronizes automatically.

Such a structure of GAPSP allows to synchronize the internal memory bandwidth t:

M POSSIBLE PERIOD Lmln,

generated by the analyzer error detector during the duration of several small periods of this SRP, the number of which is set in advance before measuring the dependence on the expected interference situation so that synchronization occurs with a probability of close to 1 over this number. The synchronization is ensured by controlling the phase shift of the internal memory bandwidth by the allocated error pulses during the time of entering the synchronism in one attempt, defined by the expression

TCmin (nmln + 1 + GPnn) Tm,

where Tm is the pulse repetition period;

nmin is the number of bits (length) of the PC generator and the error detector involved in the formation of the SRP with the minimum possible (small) period,

rrimin - the module of the account of the sixth analyzer clock counter (the number of ticks of the check phase for the absence of false synchronization).

In this case, for the input to the analyzer SRP with Lmin, passing the CKS, will be performed:

TO,

1

oshch

Pt1p

After the synchronization of the internal SRP of the error detector and the SRP of the generator that passed the CKS with a small period and after the end of receiving the error packet caused by the inversion of one small period of the SRP in the GAPSP generator at the transmitting end, the error detector of the GAPSP analyzer automatically goes over analysis of the input SRP of the required large period and the structure formed by the GAPSP generator at the transmitting end after the end of the inverse small period of the SRP

The proposed GAPSP according to (2) has a higher noise immunity, since in many cases it is possible to choose

Fri1p "Ptreb.

Greater noise immunity allows using the proposed GAPSP for functional monitoring of objects (CCS) in those cases when the use of a prototype and similar error detectors is no longer possible, and other methods for analyzing the test SRP are required, for example, measuring the signal delay time in an object control Then analysis of the test memory bandwidth can be carried out by starting the shift register in pen 5 10

fifteen

20 25

thirty

35 40 45

50 55 sensor (generator) of the SRP arriving at the control object and the same register in the error analyzer with the same initial conditions, but with a time difference equal to the signal delay time in the control object. Obviously, such a method for determining the delay and, therefore, a different principle of operation even without error coefficient analysis equipment requires a large hardware cost, since it requires the inclusion of, for example, a frequency meter in the measuring equipment, and the more accurate, the higher the clock frequency is used to transmit the SRP .

Claims (1)

The claims A pseudo-random sequence generator-analyzer comprising a control unit, the first output of which is connected to the input of the clock generator, the output of which is connected to the clock input of the first shift register and is the clock output of the analyzer-generator, the second output of the control unit is connected to the installation input of the first shift register, the first outputs of which are connected to the first information inputs of the first switch, the outputs of which are connected to the inputs of the first adder modulo two, the output of which connected to the information input of the first shift register, the second outputs of which are connected to the information inputs of the first decoder, the first output of which is the synchronization output of the analyzer-generator, the first trigger, the D-input of which is the information input of the generator-analyzer, the direct output of the first trigger is connected to the first inputs of the comparator and the second adder modulo two, the C-input of the first trigger is combined with the clock input of the second shift register and the counting input of the first counter and is a clock the generator-analyzer, the first outputs of the second shift register are connected to the first information inputs of the second switch, the outputs of which are connected to the inputs of the third adder modulo two, the output of which is connected to the first input of the fourth adder modulo two and the second input of the comparator, the output of which is connected to D - the input of the second trigger, the direct output of which is connected to the second input of the second adder modulo two, the output of which is connected to the second input of the fourth adder modulo two, the third outputs are block the controls are connected to the second information inputs of the first and second switches, the fourth output of the control unit and the output of the fourth adder are modulo two connected to the R-input of the third trigger, the direct output of which is connected to the R-input of the fourth and S-input of the fifth trigger and the zero input the first counter, the overflow output of which is connected to the C-input of the fourth trigger, the direct and inverse outputs of the fifth trigger are connected respectively to the first input of the first OR element and the S-input of the third trigger and the second counter k, characterized in that, in order to increase the noise immunity, the fifth and sixth adders modulo two, third to sixth counters, a second decoder, sixth to ninth triggers, third to fifth switches, element And and the second OR element, the first input of which is combined with the R-input of the seventh trigger and connected to the second output of the control unit, the fifth outputs of which are connected to the installation inputs of the third counter, the overflow output of which and the output of the second OR element are connected respectively to the S- and R-inputsthe sixth trigger, the direct output of which is connected to the D-input of the seventh trigger and the first input of the fifth adder modulo two, the second input of which is connected to the output of the first adder modulo two, the second output of the first decoder is connected to the input of zeroing the third counter and C-input the seventh trigger, the inverse output of which is connected to the enable input of the first decoder, the direct output of the seventh trigger is connected to the second input of the second OR element and the enable input of the first switch, the sixth output of the control unit is connected n to the control input of the fourth switch whose output is coupled to the input of the installation of the sixth counter, the count input of which is connected to the clock input generatoraanalizatora inverse output of the fourth latch coupled to the first input of the AND gate and the reset input of the fifth and sixth counters, the outputs of which overflow connected respectively to the S- and C-inputs of the fifth trigger, the second input of the And element is connected to the direct output of the fifth trigger, the third input of the And element is combined with the counting inputs of the second, fourth and fifth counters and connected to the output of the comparator, R-input the second trigger is connected to a common bus, the seventh-ninth outputs of the control unit are connected respectively to the information inputs of the fifth switch, the setting inputs of the fourth counter and the information inputs of the third switch, the outputs of the third and fifth switches connected to the installation inputs respectively of the first and the first counters, the output of the And element is connected to the first input of the sixth adder modulo two, the second input and output of which are connected respectively to the output of the third adder modulo two and the information input of the second shift register, the second outputs of which are connected to the inputs of the second decoder, the output of which is connected to the C-input of the ninth trigger and the second input of the first element OR, the output of which is connected to the zero input of the fourth counter, the overflow output of which is connected to the C-input of the eighth trigger, the R-input of which is combined with the R-input of the ninth trigger and the installation input of the second shift register and connected to the fourth output of the control unit, the direct output of the eighth trigger is connected to the D-input of the ninth trigger, whose inverse output is connected to the control inputs of the third to fifth switch, the enable input of the second switch and the enable input of the count of the second counter, the output of the fifth adder modulo two is the output of the analyzer generator. I f Editor N. Kol yes Tehred M. Morgenthal Order 4365 Mintage VNIIIPI of the State Committee for Inventions and Discovers under the State Committee for Science and Technology of the USSR 6113035, Moscow, Zh-35, Rauska nab., 4/5 Proofreader O. Kravtsova