RU1774464C - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to electronic equipment, intended for the synthesis of signals with linear frequency modulation and can be used in radar, broadband communication systems and sounding the ionosphere. The device contains: two read-only memory blocks (1,4), a drive (2), a code multiplier (3), a counter (5) with preset, a code converter (6), a memory register (7), a digital-to-analog converter (8 ), a low-pass filter (9), a clock generator (10), a delay unit (11). All of the listed blocks are connected as follows: 1-2-3-6-7-8-9. 11-2,, 11-3.11-7.10-11. The purpose of the invention is to improve performance by achieving the multiplier by entering codes 3, code converter 6, memory register 7, read-only memory 4, and counter 5 with a preset. 3 ill.

Description

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The invention relates to electronic equipment, intended for the synthesis of signals with linear frequency modulation and can be used in radar, broadband communication systems and sounding the ionosphere.

The closest technical solution to the proposed one is a digital frequency synthesizer comprising a frequency setting unit, a drive, a clock, a delay unit, a first code converter, an angular correction calculation unit, a read-only memory, a code multiplier, a first memory register, a code allocator , a second code converter, an adder, a second memory register, a digital-to-analog converter, and a low-pass filter.

However, such a synthesizer but provides a sufficiently high speed. The aim of the invention is to increase speed. This goal is achieved in that in a digital frequency synthesizer containing a series-connected clock generator and a delay unit, a series-connected memory register, a digital-to-analog converter and a low-pass filter, a first read-only memory unit, a code multiplier, a code converter, a drive, a clock input which is connected to the first tap of the delay unit, the second tap of which is connected to the clock input of the memory register, additionally connected in series to the second a permanent memory lock and a preset counter, whose main input is connected to the first tap of the delay unit, the third tap of which is connected to the input of the write signal of the multiplier code multiplier, the input of the multiplier recording signal is connected to the fourth tap of the delay unit, fifth the output of the delay unit is connected to the input of the signal for recording the result of the multiplication of the code multiplier, the input of the multiplier of which is connected to the output of the drive, the information input of which is connected to the output of the first block of the constant ominani, and the counter output with preset is connected to the input of the code multiplier, the output of the high-order signal of which is connected to the input of the high-order signal of the code converter, the code input of the signal of low-order bits of which is connected to the code output of the signals of low-order bits code multiplier, the output of the code converter is connected to the information input of the memory register.

In the developed technical solution, the phase of the synthesized FM signal is directly calculated. This makes it possible to exclude the operations of calculating the sine and cosine of the signal and provide a positive effect - increased performance.

In FIG. 1 is a structural diagram of the developed digital frequency synthesizer; in FIG. 2a, b, c, d, e, e are shown, respectively, diagrams at the output of the clock generator and at the first, second, third, fourth and fifth taps of the delay unit; in FIG. For given time

5 is a diagram of a changing code P at the output of a code multiplier. In FIG. 36 is a timing chart of a varying phase p code at the output of a memory register.

The device of FIG. 1 comprises a block 1

0 read-only memory, drive 2, multiplier 3 codes, block 4 read-only memory, counter 5 with preset, code converter 6, memory register 7, digital-to-analog converter 5 phone 8, low-pass filter 9, clock generator 10 and block 11 delays. Digital frequency synthesizer operates as follows.

The addresses of the sample Ci, Dk, which determine the initial frequency and the rate of change of the frequency of the synthesized frequency-modulated signal, are received at the address inputs of the blocks 1.4 of constant memory. The clock generator 10 generates a sinusoidal signal of the reference frequency f (see Fig. 2 a). The delay unit 11 converts this signal into meander clocks. Due to the fact that the sequence of clock

0 pulses from the outputs of block 11 of the delay are separated by a time of 3 ed, a significant reduction is achieved in switching noise of the accumulator 2, the code multiplier 3, and the counter 5 under undefined conditions

5 at their exits.

At the output of accumulator 2, the resulting numbers are updated with a synchronization frequency f. The code of the number X at the outputs of drive 2 is changed as follows:

X Ci x T.

where T is the number of the clock pulse (T -0.1,2 ...).

The code of the number Y at the outputs of the counter 5 s

5 by preset changes as follows: Y Dk + T.

Multiplier 3 multiplies the codes X, the multiplier MY factor.

The product code P with each clock pulse is changed as follows:

X X x Y Ci x T x (Dk + T). In this case, the product code varies from 0 to (2N-1), where N is the number of bits of the digital-to-analog converter 8. The highest bit of the product PIsGN is signed and is input to the code converter. The remaining N high-order bits (N is the number of bits of the digital-to-analog converter 8) through the code converter b and memory register 7 are supplied to the corresponding inputs of the digital-to-analog converter 8. If the high-order bit of the product is logical zero, then to the digital-to-analog converter 8 direct binary product code П arrives (see Fig. 3a). If risGN is 1, then the inverse product product поступ is supplied to the digital-to-analog converter 8 (see Fig. 36). The digital-to-analog converter 8 generates a triangular step signal whose phase (f changes as follows: p P Ci x T x (Ok + T) Ci x Dk x T + Ci x T2.

The low-pass filter 9 passes only the first harmonic of the generated signal to the output of the digital frequency synthesizer. As a result, a frequency-modulated signal is generated at the output of the frequency synthesizer, the amplitude of which varies according to the law

U (t) Um (Ci x Dk x T + d x T2), where Urn is the maximum value of the signal amplitude at the output of the digital-to-analog converter 8.

The phase of the synthesized signal changes according to the law:

# C xDkxT + CixT2, ecnnCixDk ftb; About 0.5c5, -T At, where ftb is the initial cyclic frequency;

ct is the rate of change of the cyclic frequency, then

r Sho g + 0.5 SU t2.

Thus, the developed device synthesizes a signal of the form

U (t) UmSln (uA, t + 0.5c & t2), which is used in radar and 5 communication systems.

Claims (1)

SUMMARY OF THE INVENTION A digital frequency synthesizer comprising a series-connected clock generator and a delay unit, 10 series-connected memory registers, a digital-to-analog converter and a low-pass filter, a first read-only memory unit, a code multiplier, a code converter, a power supply, whose fifth input is connected to the first tap of the delay unit, the second tap of which is connected to the clock input of the memory register, characterized in that, in order to improve performance, 0 are connected in series to the second read-only memory unit and a preset counter, the clock input of which is connected to the first tap of the delay unit, the third tap of which is connected 5 with the input of the write signal of the largest code multiplier, the input of the signal of the multiplier of which is connected to the fourth tap of the delay unit, the fifth output of the delay unit is connected to the input of the signal of recording the multiplication result of the code multiplier, the input of which is multiplied with the output of the drive, the information input of which is connected to the output of the first block of constant storage, and the output 5 counters with a preset are connected to the input of the code multiplier factor, the output of the high-order signal of which is connected to the input of the high-order signal of the code converter, the code low-level signal input of which is connected to the code output of the low-order signals of the code multiplier, the output of the code converter connected to the information input of the memory region. 6) CLK2 g; CLI & t .J tS. 14 e) CLK5 % pr my back