RU126162U1 - COMMUNICATION INTERFACE DEVICE FOR NETWORK Space Wire - Google Patents

Abstract

1. A communication interface device for the Space Wire network, comprising a data output unit, a data reception unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which is connected to the input of the data output unit of the same name, the output of which is ready to issue a flow control symbol of connected to the input of the data flow control unit of the same name, inputs of acknowledgment of receipt of the flow control symbol and acknowledgment of receipt of the information symbol of which are connected respectively to one the outputs of the data receiving unit and the inputs of the same name of the control unit, the character encoding error output of which is the symbol encoding error output of the system interface of the device, the reset input of the device system interface is the reset input of the control unit, the first and second reset outputs of which are connected to the reset inputs of the data output unit, respectively and a data receiving unit, the “received NULL” output of which is connected to the control unit input of the same name, the data reading input of the device’s system interface is are the input of the data receiving unit of the same name, the data outputs for receiving and the readiness of the data for receiving are the corresponding outputs of the device system interface, the credit error of the device system interface is the output of the data flow control unit of the same name and connected to the same input of the control unit, the third reset output of which is connected with the reset input of the data flow control unit, inputs for confirming the issuance of an information symbol and permitting the reception of data of which are connected to

Description

This utility model is a communication interface device (system) and relates to digital computing, namely, to high-speed communication systems for high-performance multiprocessor computing systems with distributed information processing and local area networks based on SpaceWire technology [ECSS Standard ECSS-E -50-12A, "SpaceWire, Links, Nodes, Routers and Networks", Issue 1, European Cooperation for Space Data Standardization, February 2003.]. This device is intended, in particular, for use in building multiprocessor computing systems with a distributed architecture, used in embedded applications, including on-board computer systems, as well as on-board local area networks.

As an analogue from the prior art, a communication interface is known as described in the FiberChannel standard [Fiber Channel - Physical Interfaces - 2 (FC-PI-2), ISO 1.25.13.], Which uses the 8b / 10b for representing eight-bit characters as 10-bit codes. In devices that communicate via this communication interface, every eight bits of the original sequence are replaced with 10 bits in accordance with certain rules. As a result, for 256 possible combinations of eight input bits, 1024 possible combinations for 10 output bits are obtained. But of these 1024 combinations, only 256 are allowed, and the rest are forbidden. As a rule, such redundancy is used in order to increase coding noise immunity (if a forbidden sequence is detected during reception, a transmission error is recognized). In addition, such redundancy improves the self-synchronizing properties of the code, since it eliminates the possibility of long sequences of zeros and ones appearing in the transmitted bit chain, which ultimately helps to increase the reliability of the device. When data is received, 8b / 10b decoding is performed, that is, eight bits are mapped to each group of 10 bits.

The disadvantage of this approach is the inability to transmit special control codes along with data symbols. Special control codes are needed to support system functions and real-time control, which significantly limits the scope.

A conversion device 8b / 10b is known, [US Patent 06977599 B2. 8B / 10B encoding and decoding for high speed applications, Apr 30, 2002]. used in the FibreChannel standard. The device contains an 8b / 10b encoding unit, an output 10-bit shift register that converts parallel 10-bit codes to a serial bit stream output to the communication interface, an input 10-bit shift register that provides reverse conversion of a serial bit stream to parallel 10-bit codes and decoding unit 8b / 10b. The device operates at a local frequency 10 times lower than the bit rate in the communication interface. The use of the code 8b / 10b allows the use of a single data transmission line in the communication channel, since when encoding 8b / 10b it is possible to transmit, along with data symbols, a special built-in clock symbol for synchronizing interacting devices.

As a drawback, it should be noted that the device does not provide real-time transmission of various special control codes (system interrupts, system time markers and other control signals necessary for control at the system level), since it is not possible to insert a control code into the sequence of transmitted eight-bit characters data of one frame. The need to wait for the end of the transmission of the next data frame leads to significant time delays in performing system functions. In addition, the inability to implement system mechanisms in real time significantly narrows the scope.

Known serial communication interface that implements the method of DS-coding (Data-Strobe coding) in accordance with the standard Space Wire [ECSS Standard ECSS-E-50-12A, "Space Wire, Links, Nodes, Routers and Networks", Issue 1, European Cooperation for Space Data Standardization, February 2003.] and is widely used for transmitting bit streams between processing nodes in on-board distributed computing complexes. The use of data lines and strobe (D- and S-signals) in each direction in the communication interface allows for high-speed transmission of data bits in a wide speed range from 2 Mbit / s to 400 Mbit / s. A simple implementation of the procedure for generating data packets based on the use of service (control) characters of the end of the EOP packet (End Of Packet) allows transmitting information symbols in the form of packets of arbitrary length. This feature simplifies the structure of switching nodes (switches and hubs) used to transmit and switch bit streams from airborne sensors to processing nodes in distributed computing complexes.

The disadvantage of the SpaceWire interface is the presence of jitter (variation of the delay time) between the parallel transmitted D- and S-signals in the physical channel. Due to the need to use two lines for transmitting data bits and gating signals, DS coding places rather stringent requirements on the bevel (phase shift) and jitter of D and S signals, which makes it difficult to use it at distances of more than 10 meters. Also, the presence of two lines for each direction of transmission makes it difficult to use galvanic isolation due to various delays at the isolation itself, which significantly limits the scope of SpaceWire devices in on-board distributed computing complexes.

A device for a communication interface [PATENT GB No. 91304711.4. Communication interface for serial transmission of variable length data tokens / Priority 05/25/90, No. 9011700. Data of filing 05/24/91. Data of publication 11/27/91. Bulletin 91/48 of European Patent Office. Publication number 0458648A2] for use in a communication system connecting at least two computers, the communication interface device comprising a control unit, a data flow control unit, a data output unit and a data receiving unit, the data and gating inputs of which are respectively data and gating inputs of the interface devices with a channel for receiving information, data outputs and gating interface of a device with a channel for issuing information are respectively data outputs and gating block and data output. Using the FCT (Flow Control Token) special control characters for flow control, the device’s flow control unit implements a lending mechanism that allows the use of buffers of a limited size for receiving and transmitting packets of unlimited length.

The disadvantage of this device of the communication interface is the limitation of the distance between the interacting parties and the absence of galvanic isolation, which can cause failures and malfunctions due to short circuits.

The closest analogue to the claimed is a communication interface device [RF Patent for utility model No. 103013. Communication interface device. Publ. 03/20/2011, declared. 05/26/2010, H04L 1/00 (2006.01)], which provides data transmission from the host system to the serial channel in accordance with the SpaceWire standard and contains a data output unit, a data reception unit, a control unit and a data flow control unit, an output of a request for issuance the flow control symbol of which is connected to the input of the data output unit of the same name, the readiness output of the flow control symbol of which is connected to the input of the data flow control unit of the same name, acknowledgment inputs of the flow control symbol and acknowledgment of receipt the information symbol of which is connected respectively to the outputs of the data receiving unit and the inputs of the control unit of the same name, the output of the character encoding error is the output of the character encoding error of the system interface of the device, the reset input of the device system interface is the reset input of the control unit, the first and second reset outputs of which are connected to reset inputs, respectively, of the data issuing unit and the data receiving unit, the output of “received NULL” of which is connected to the same input of the unit board, the input for reading data from the device’s system interface is the input of the data receiving unit of the same name, the data outputs for receiving and the readiness of the data for receiving are the corresponding outputs of the device’s system interface, the credit error output of the device’s system interface is the output of the data flow control unit of the same name and connected to the input of the same name control unit, the third reset output of which is connected to the reset input of the data flow control unit, inputs for confirming the issuance of information symbol and data reception permissions which are connected to the outputs of the same name respectively of the data output unit and the data reception unit, the output readiness output of the system interface of the device is the same output as the data output unit, the recording and data inputs for issuing the system interface of the device are the corresponding inputs of the data output unit, which contains a block of arbitration of the issuance of characters, a buffer for issuing data, the output of readiness for issuing data of which is the same output as the issuing unit for data, the recording and data inputs for the output of which are the corresponding inputs of the data output buffer, the outputs for confirming the issuance of the information symbol and the readiness for issuing the flow control symbol of the data output unit are the outputs of the arbitration unit for issuing symbols, the input of the request for issuing the flow control symbol of which is the same input a data output unit, the reset input of which is a reset input of a character issuing arbitration unit and is connected to a reset input of a data output buffer, the data readiness output of which is connected to the input of the symbol issuing arbitration unit of the same name, the synchronization input of which is connected to the synchronization input of the data output buffer and is the synchronization input of the data issuing unit, the outputs of which the flow control symbol is allowed and transmitting are the same inputs of the symbol issuing arbitration unit, the output data reader which is connected to the input of the data output buffer of the same name, the output of the packet end flag of which is connected to the input of the arbiter block of the same name Ms issuing characters; the data receiving unit contains a data receiving buffer and a decoded code decoder, the output of the flow control symbol receiving confirmation and the “received NULL” output of which are the outputs of the data receiving unit of the same name, the received data output of which is the output of the data receiving buffer of the same name, data reception permission outputs and readiness received the data of which are respectively the outputs of the same name of the data receiving unit, the data reading input of which is the reading input of the data receiving buffer, the recording permission input b the data receiving scam is connected to the output of the acknowledgment of the decoder information symbol of the converted code and is the same output of the data receiving unit, the reset input of which is the reset input of the data receiving buffer.

This device supports operation at frequencies up to 400 MHz, with a local frequency 2 times less than the frequency of transmission and reception of bits. That is, it allows you to transmit a stream of data bits and gates in the communication interface at a frequency twice the local frequency at which all other blocks of the device work. However, various non-multiple coding of SpaceWire characters having different lengths does not allow to effectively increase the bit rate relative to the local synchronization frequency.

The disadvantage of this technical solution is the limited functionality. On the one hand, this limitation is associated with the inability to transmit control signals in real time over the stream of transmitted packet data. On the other hand, there is a limitation of the bit rate and the distance between the interacting devices of the communication interface, as well as a decrease in reliability due to the inability to use galvanic isolation of the devices from each other, which does not prevent failures and malfunctions due to short circuits.

The basis of this utility model is the task of developing a communication interface device that provides enhanced functionality by realizing the possibility of real-time transmission of system control signals along with the transmission of packet data bits; increase the speed of transmission and reception of data bits; overcoming the limitations of the interaction of devices over long distances and the possibility of using galvanic isolation of interacting devices.

The technical result of the proposed technical solution is to expand the scope of the communication interface device by providing system level control signals and using a coding scheme that ensures alignment of the length of the transmitted characters and allows data bits to be transmitted over a cable containing only one data line in each direction, and increase the cable length of the communication interface while achieving higher performance and by reliability in comparison with known analogues.

The technical result is achieved by the fact that in the proposed communication interface device for the SpaceWire network, comprising a data output unit, a data reception unit, a control unit and a data flow control unit, a request for issuing a flow control symbol is connected to the input of the data output unit of the same name, the readiness output issuing a flow control symbol which is connected to the input of the data flow control unit of the same name, inputs for acknowledging the receipt of a flow control symbol and acknowledging information which symbol is connected respectively to the outputs of the data receiving unit and the inputs of the control unit of the same name, the output of the character encoding error is the output of the character encoding error of the system interface of the device, the reset input of the device system interface is the reset input of the control unit, the first and second reset outputs of which are connected to reset inputs, respectively, of the data issuing unit and the data receiving unit, the output of which is “received NULL” is connected to the input of the control unit of the same name, The data reading system interface of the device is the input of the data receiving unit of the same name, the data outputs for receiving and data readiness for reception of which are the corresponding outputs of the device system interface, the credit error output of the device system interface is the output of the data flow control unit of the same name and is connected to the input of the control unit of the same name , the third output of the reset of which is connected to the reset input of the data flow control unit, inputs confirm the issuance of information from the symbol and permissions for receiving data of which are connected to the outputs of the same data output unit and the data receiving unit, the output readiness output of the system interface of the device is the same output as the data output unit, the recording and data inputs for issuing the system interface of the device are the corresponding inputs of the data output unit, which contains a block of arbitration for issuing symbols, a buffer for issuing data, the output of readiness for issuing data of which is the same output as the block for issuing data, inputs records and data for the issuance of which are the corresponding inputs of the data output buffer, the outputs for confirming the issuance of the information symbol and the readiness for issuing the flow control symbol of the data issuing unit are the corresponding outputs of the symbol arbitration unit, the input of the request for issuing the flow control symbol of which is the input of the data issuing unit of the same name , the reset input of which is the reset input of the arbitration unit for issuing symbols and is connected to the reset input of the data output buffer, the output is ready whose data is connected to the input of the symbol issuing arbitration unit of the same name, the synchronization input of which is connected to the synchronization input of the data issuing buffer and is the synchronization input of the data issuing unit, the outputs of the issuing permission and transmitting permission symbols of the flow control symbol of which are the same inputs of the symbol issuing arbitration unit, the read output the data of which is connected to the input of the data output buffer of the same name, the output of the end of packet sign of which is connected to the input of the arbitration block of the sim oxen; the data reception unit contains a data reception buffer and a decoded code decoder, the acknowledgment of the receipt of the flow control symbol and the “received NULL” output of which are the inputs of the same name of the control unit, the received data output of which is the output of the data reception buffer of the same name, the outputs of the data reception permission and readiness of received data which are respectively the outputs of the same name of the data receiving unit, the data reading input of which is the reading input of the data receiving buffer, the buffer write permission input and the data reception is connected to the output confirmation message of the decoded code decoder information symbol and is the output of the data receiving unit of the same name, the reset input of which is the input of the data reception buffer reset, the transmitted character converter, the 8b / 10b encoding unit, the bit transmission unit, the bit receiving unit are additionally introduced , decoding unit 8b / 10b, character buffer 8b, received character converter, connection check unit, the disconnect error output of which is connected to the input of the control unit of the same name Phenomenon, the first output of the reset is connected to the inputs of the transmitter of transmitted symbols and the coding unit 8b / 10b of the same name, the information input of which is connected to the data output of the symbol 8b of the converter of transmitted symbols, the output of which the character is ready is connected to the readiness input of the data output unit, information output and type the symbol of which is connected respectively to the data inputs and the symbol type of the converter of transmitted symbols, the output of the special symbol attribute of which is connected to the input of the symbol type symbol ol of the coding block 8b / 10b, the output of the encoded data of which is connected to the same input of the bit transmission unit, the output of the bit signals of which is the same output as the communication interface of the device, the local synchronization output of the transmission of bits is connected to the same inputs of the coding block 8b / 10b, the converter of transmitted characters, character buffer 8b, a converter of received characters, a control unit, a data receiving unit and a data output unit, the input of the control code recording of which is of the same name the input to the system interface of the device, the readiness output of the control code of which is the output of the data output unit of the same name, the input of the control code for which is the input of the device system interface of the same name, the output of the received control code of which is the output of the data reception unit of the same name, the readiness of the received control code of which is is the output of the same system interface of the device, the input of reading the control code of which is the input of the same name data reception, the information input and the input of the symbol type of which are connected respectively to the inputs of the converter of the received symbols with the same information, the information input and the input of the sign of the special symbol of which are connected respectively with the outputs of the character buffer 8b, the recording permission input is connected to the same output of the decoding unit 8b / 10b, the symbol output 8b which is connected to the information inputs of the character buffer 8b and the connection check unit, the input of the special character flag of which is connected to the input of the same buffer s mvolv 8b and with the same output of the decoding unit 8b / 10b, the output of the coding error of which is connected to the input of the control unit of the same name, the connection establishment input of which is connected to the same output of the connection verification unit, the input of the connection attribute of which is connected to the input of the received symbol converter of the same name and the output of the same name a bit receiving unit, the data receiving synchronization output of which is connected to the reception symbol synchronization input of the symbol buffer 8b, to the synchronization input of the connection check unit and to the synchronization code of the decoding unit 8b / 10b, the information input of which is connected to the output of the received encoded data of the bit receiving unit, the input of the bit signals of which is the input of the device’s communication interface, the control code issuing register is entered into the data issuing unit, the output of which is ready to issue the control code is the output of the data output unit of the same name, the input of the record of which is the input of the record of the register for issuing the control code, the input of the control code for the output of which is explicit it is the input of the data output unit of the same name, the reset and synchronization inputs of which are connected respectively to the reset and synchronization inputs of the control code issuing register, the control code readiness output of which is connected to the input of the character issuing arbitration unit of the same name, the control code reading output of which is connected to the input of the control output register codes, the output of the control code of which is connected to the second information input of the data multiplexer; a control code receiving register is entered into the data receiving unit, the information input of which is the input of the data receiving unit of the same name, the reset and local synchronization inputs of which are connected respectively to the reset and local synchronization inputs of the control code receiving register, the readiness outputs of the received control code and the received control code of which, are respectively the same outputs of the data receiving unit, the input of the control code reading of which is the same name as the input of the control reception register code, the recording and synchronization enable inputs of which are connected respectively to the synchronization input of the data receiving unit and to the output of the selection of the control code of the decoded code decoder.

Preferably, the transmitted symbol converter comprises an output data register, a first symbol type register, a control code selector, a control code trigger, a first ROM constant, an output multiplexer, a first counter, a first AND element, a second AND element, a third AND element, whose symbol output is ready to be output is the output of the transmitter of the transmitted characters of the same name, the data input of which is the data input of the output data register, the output of which is connected to the first information input of the output mult a plexor whose symbol data output 8b is the same output as the transmitted symbol converter, the local synchronization input of which is connected to the synchronization inputs of the first symbol type register, the first trigger of the control code, with the counting input of the first counter and with the synchronization input of the input data register, the converter reset input is connected to reset inputs of the output data register, the first symbol type register, the first trigger of the control code and the first counter, the transfer output of which is connected to With the first input of the first ROM constants, with the second inverse input of the second element And, with the second input of the first element And, the inhibit output of which is connected to the inverse input of the reset of the first counter, the input of the symbol type of the transmitter of transmitted characters is the data input of the first register of the symbol type, the output of the first register of the type the symbol is connected to the first input of the first ROM of constants and to the input of the selector of the control code, the output of the selection of the control code of which is connected to the first input of the third element And, the output of setting the flag connected to the data input of the control code trigger, the direct output of which is connected to the first input of the first AND element, with the first inverse input of the second AND element, with the third input of the first ROM constants, the output of the special character code of which is connected to the second information input of the output multiplexer, The output of the special character sign the first constant ROM is the output of the transmitter of the transmitted symbols of the same name and is connected to the control input of the output multiplexer, the inverse trigger output is connected to the second input of the third about element I.

Preferably, the received symbol converter comprises a second ROM of constants, a second symbol type register, a second control code trigger, an input multiplexer, an input symbol type register, an input data register, the output of which type of received symbol is the output of the received symbol converter of the same name, the information input of which is connected to the input data of the input data register and with the first input of the second ROM of constants, the second input of the second ROM of constants is the input of the sign of the special symbol of the converter of recognizable characters, the enable input of the ROM is the input of the sign of the converter of the received characters, the output of the symbol type of the second ROM constants is connected to the data input of the second register of the character type and the first information input of the input multiplexer, the output of the selection of the control code of the second ROM constants is connected to the data input of the second trigger of the control code and with the input of the reset register of the input symbol type, the data input of which is connected to the output of the input multiplexer, the second information input of which is Inonii with the output of the second character type symbol delayed type register, the clock input of which is the input local synchronization symbols received converter and is connected to the clock input of the second flip-flop control code type input character register and the register input data, the output data output transducer is received symbols.

In this communication interface device, the technical result is achieved through the use of additional conversion of SpaceWire technology symbols into 8b format symbols, followed by 8b / 10b encoding before their transmission as a sequence of bit signals to a remote device via a dedicated communication channel having one transmission line in each direction. In addition to the packet data symbols of the SpaceWire network, this device additionally provides the transmission of real-time control signals to support system mechanisms (system time stamps, interrupts, etc.). As a result of this technical solution, conditions appeared for transferring data between devices in the SpaceWire network at distances significantly exceeding the values determined for cables in the SpaceWire standard, while removing restrictions on increasing the data transfer rate in the communication channel. Using only one line for data transmission significantly reduces the influence of the signal jitter on the limitation of the transmission speed, since the signal jitter will depend on only one transmitter. The use of 10b / 8b coding allows increasing the transmission speed of bit signals in the communication channel relative to the local synchronization frequency by ten times and simplifying the implementation of the device at the local synchronization frequency due to the same 8b / 10b symbol multiplicity, in contrast to the standard SpaceWire different encoding of characters. In addition, the provided possibility of using galvanic isolation at the input and output of the communication interface can improve the reliability of the device.

The essence of this technical solution is explained in detail with a description with reference to the figures of the drawings, in which Fig. 1 shows a block diagram of a device, Fig. 2 is a functional diagram of a data output unit, and Fig. 3 is a functional diagram of a data reception unit. Figure 4 and figure 5 presents possible options for the implementation of functional circuits of the data flow control unit and the control unit. Figure 6 shows the functional diagram of the Converter transmitted characters. 7 shows an embodiment of a possible implementation of a functional block diagram of a bit transmission unit. Fig. 8 shows an embodiment of a possible implementation of a functional circuit of a bit receiving unit. Figure 9 shows the functional diagram of the Converter received characters. Figure 10 shows the functional diagram of the connection verification unit. 11 shows a state machine of the physical signal exchange layer (PHY). 12 is a timing chart illustrating a character alignment procedure 10b. On Fig depicts an automatic level adaptation SpaceWire. 14 is a timing chart illustrating the transmission of a special communication support character among other symbols. On Fig presents a graph of the state machine that describes the modes of operation of the device at the level of exchange SpaceWire. In Fig.16 shows the timing diagrams of the transmission of bytes of packet data, Fig.17 - timing diagrams of receiving data symbols, control characters and control codes, Fig.18 - timing diagrams of the transmission of the control code, Fig.19 - timing diagrams of the transmission of the control code and special character support communications.

As shown in FIG. 1, the proposed device comprises a data output unit 1, a data reception unit 2, a data flow control unit 3, a control unit 4, transmit symbols 5, an encoding unit 6 8b / 10b, a bit transmitting unit 7, a receiving unit 8 bits, decoding unit 9 8b / 10b, buffer 10 characters 8b, converter 11 received characters, unit 12 for checking the connection, input 13 for synchronizing the system interface, input 14 for resetting the system interface, output 15 for readiness for issuing system interface data, input 16 for recording system interface data ISA, input 17 of data for issuing a system interface, output 18 of readiness of received data of a system interface, output 19 of received data of a system interface, input 20 of reading system interface data, output 21 of readiness for issuing a system interface control code, input 22 of a system interface control code entry, input 23 control code for issuing a system interface, output 24 of the readiness of the received control code of the system interface, output 25 of the received control code of the system interface, input 26 of the control system interface ode, system interface connection output 27, system interface disconnect error output 28, system interface symbol encoding error output 29, system interface symbol encoding error output 30, system interface credit error output 30, flow control symbol acknowledgment output 31, information symbol acknowledgment output 32, output 33 a request for issuing a flow control symbol, a first reset output 34, a second reset output 35, a third reset output 36, a ready flow control output 37 output, output 38 times flow control symbol transmission decisions, information symbol output confirmation output 39, data reception permission output 40, data output permission output 41, symbol output 42 output, symbol type output 43, symbol output readiness output 44, special character sign output 45, symbol data output 46 symbol 8b , output 47 of encoded data, output 48 of local synchronization, output 49 of the signal signals of the communication interface, input 50 bit of the signals of the communication interface, output 51 of the received encoded data, output 52 of the receive synchronization data, output 53 of the sign of the connection, output 54 of the character 8b, output 55 of the sign of the special character, output 56 of the recording permission, output 57 of the coding error, information output 58, output 59 of the sign of the special character, output 60 of the disconnect error, output 61 of the connection, information output 62, output 63 of the type of the received symbol, output 127 "Received NULL".

The data issuing unit 1 (see FIG. 2) contains a character issuing arbitration unit 64, a data issuing buffer 65, a control code issuing register 66, a data multiplexer 67, a reset input 68, an output enable input 69, an output synchronization input 70, a request input 71 for issuing a flow control symbol, input 72 for transmitting a flow control symbol, input 73 ready, output 74 data ready, output 75 read data, output 76 sign of the end of the packet, output 77 data, output 78 read control code, output 79 information selection, output 80 ready control code , control code output 81, synchronization input 13, data output ready 15 output, record 16 input, data input 17 for output, control code output ready 21, control code entry 22, input 23 control code for output, output 37 ready flow control symbol, information symbol output confirmation output 39, information output 42, symbol type output 43.

The data receiving unit 2 (see FIG. 3) contains a converted code decoder 82, a data receiving buffer 83, a control code receiving register 84, an information input 85, a symbol type input 86, a reset input 87, a local synchronization input 88, a control selection output 89 code, output 127 “Received NULL”, input 13 of the system interface synchronization, output 18 of the received data ready, output 19 of the received data, input 20 to read the system interface data, output 24 of the received control code ready, output 25 of the received control code, input 26 of the control read to yes system interface, output 31 acknowledgment of receipt of the symbol of the flow control, output 32 of the acknowledgment of receipt of the information symbol, output 40 of permission to receive data.

The data flow control unit 3 contains (see FIG. 4) a credit request generator 90, a received symbol counter 91, a transmitted symbol counter 92, a credit error detector 93, a data reception permission input 94, a reset input 95, a flow control symbol readiness input 96 , input 97 acknowledgment of receipt of the information symbol, input 98 acknowledgment of receipt of the symbol of the flow control, input 99 confirmation of the issuance of the information symbol, output 100 of the counter status, output 101 errors of credit reception, output 102 errors of credit issuance, input 13 synchronization, credit error output 26, output 33 of a request for issuing a flow control symbol, output 41 of permission to issue data.

The control unit 4 contains (see FIG. 5) a state register 103, a new state generating unit 104, a control signal generator 105, a delay unit 106, a connection establishment input 107, a credit error input 108, a disconnect error input 109, a character encoding error input 110 , input 111 acknowledgment of receipt of the symbol of the flow control, the input 112 of the acknowledgment of receipt of the information symbol, the input 113 local synchronization, the output 114 status, the output 115 state control, the control output 116, the input 178 "Received NULL", the input 13 synchronization system interface, system interface reset input 14, system interface connection output 27, system interface disconnect error output 28, system interface character encoding error output 29, first reset output 34, second reset output 35, third reset output 36, symbol transfer enable output 38 flow control.

Transmitter 5 of transmitted symbols (see FIG. 6) contains an output data register 117, a first symbol type register 118, a control code selector 119, a control code trigger 120, a first ROM 121 constants, an output multiplexer 122, a first counter 123, a first AND element 124 , second element 125 I, third element 126 I, input 128 data, input 129 symbol type, input 130 local synchronization, input 131 reset, output 132 type symbol, output 133 selection of data symbol, output 134 selection control code, inverse output 135 flag control code, output 136 setting flag a, direct control code output 137, account prohibition output 138, transfer output 139, special character code output 140, character output ready output 44, special character sign output 45, character data output 46 character 8b.

The bit transmission unit 7 (see FIG. 7) comprises a bit transmission clock 141, a first frequency divider 142, an output shift register 143, an output signal conditioner 144, an input 145 of encoded data, an output 48 of local synchronization, an output of 49 bit signals.

The block 8 receiving bits (see Fig) contains a generator 146 clock signals receiving bits, a second divider 147 frequency, input shift register 148, block 149 alignment, output signal amplifier 150, input 50 bit signals, output 51 of the received encoded data, output 52 synchronization of data reception, output 53 of the sign of the connection.

The converter 11 of the received symbols (see Fig. 9) contains a second ROM 151 of constants, a second symbol type register 152, a second control code trigger 153, an input multiplexer 154, an input symbol type register 155, an input data register 156, a local synchronization input 157, information input 158, input 159 sign of a special character, input 160 of a sign of connection, output 161 type of character, output 162 of selection of the control code, output 163 of the flag of the control code, output 164 of the delayed type of character, information output 62, output 63 of the type of the received character.

The connection verification unit 12 (see FIG. 10) contains a communication support symbol decoder 165, a communication setup trigger 166, a second counter 167, a first OR element 168, a second OR element 169, a fourth AND element 170, an information input 171, a special symbol input 172 , connection flag input 173, synchronization input 174, communication support symbol selection output 175, transfer output 176, disconnect flag output 177, disconnect error output 60, connection establishment output 61.

On the time diagrams (see Fig. 12) for the process of aligning the symbols in the device, it is shown: a - values of bit signals, b - sign of connection at the output 53 of the block 8 for receiving bits, c - clock signals at the output 52 for synchronizing data reception of the block 8 for receiving bits , d - aligned characters 10b at the output 51 of the block 8 of the reception of bits.

The time diagrams (see Fig. 14) for the transmission process of the special communication support symbol show: a - clock signals, b - data at the output of 133 output data registers 117, c - symbol type code at output 132 of the first symbol type register 118, d - the transfer signal at the output 139 of the first counter 123, e is the data at the output 46 of the output multiplexer 122, f is the sign of the special character at the output 45 of the first ROM 121 constants, g is the readiness signal for writing to the registers 117 and 118 at the output 44 of the transmitter 5 of transmitted symbols.

In the time diagrams (see Fig. 16) for the process of transferring bytes of packet data to the converter 5 of transmitted symbols: a - clock signals, b - data at the output 133 of the register 117 of the output data, c - code of the type of the symbol at the output 132 of the first register 118 of the type symbol, d - data at the output 46 of the output multiplexer 122, e - sign of a special character at the output 45 of the first ROM 121 constants, f - signal of readiness for writing to the registers 117 and 118 at the output 44 of the transmitter 5 transmitted characters.

On the time diagrams (see Fig. 17) for the process of receiving symbols 8b it is shown: a - clock signals, b - data at the information input 158 of the converter 11 of the received symbols, c - sign of a special symbol at the input 159 of the second ROM 151 constants, d - type code the symbol at the output 161 of the symbol type of the second ROM 151, e is the data at the information output 62 of the input data register 156, f is the symbol type code at the output 164 of the delayed symbol type of the second symbol type register 152, g is the sign of the control code at the output 162 of the selection of the control code second ROM 151, h - I control the flag its code at the output 163 of the second flip-flop 153 the control code, i - type character code at the output 63 of the input character type register 155.

On the time diagrams (see Fig. 18) for the control code transmission process it is shown: a - clock signals, b - data at the output 133 of the output data register 117, c - symbol type code at the output 132 of the first symbol type register 118, d - data at the output 46 of the output multiplexer 122, e is a sign of a special character at the output 45 of the first ROM 121 constants, f is the ready signal at the output 44 of the converter 5 of transmitted characters.

The time diagrams (see Fig. 19) for the process of transmitting a control code and a special symbol for communication support show: a - clock signals, b - data at the output of 133 registers 117 of the output data, c - code of the character type at the output 132 of the first register 118 character type , d is the transfer signal at the output 139 of the first counter 123, e is the data at the output 46 of the output multiplexer 122, f is the sign of the special character at the output 45 of the first ROM 121 constants, g is the ready signal at the output 44 of the converter 5 of transmitted symbols.

The data output unit 1 is designed to generate SpaceWire data symbols from the packet data received through the data input for output connected to the input 17 of the device system interface of the same name, as well as control characters on demand from the output 33 of the request for the issuance of a flow control symbol of the control unit 3 the data stream to the input of the same name of the block 1. The input 16 of the data recording of the system interface of the device is the same input of the block 1 of data output, output 15 of the readiness of the data output of which is the same ennym output device interface system. Output 15 and input 16 of the system interface are designed to implement the standard mechanism for buffering packet data from the host system (computer, switch, or other SpaceWire network node) in the data output unit 1. The input 22 of the record of the control code of the system interface of the device is the same input of the data output unit 1, the output 21 of the readiness for issuing the control code of which is the same output of the system interface. The input 23 of the control code for issuing the system interface of the device is connected to the input of the unit of the same name 1. Recording bytes of packet data and control codes in block 1 is clocked from its synchronization input connected to the synchronization input 13 of the device’s system interface. The outputs 37 of the readiness for issuing a flow control symbol and 39 for confirming the issuance of an information symbol of block 1 are connected to the inputs of the data flow control block 3 of the same name and are designed to implement the lending mechanism necessary to organize the transmission and reception of data through a communication interface without overflowing the receive buffers of interacting devices. The information output 42 of block 1 is connected to the data input of the transmitter 5 transmitted characters and provide the transmission of bytes of packet data and control codes. The output 43 of the symbol type of block 1 is connected to the input of the transmitter of the transmitted symbols 5 of the same name and is intended to determine the type of transmitted symbol of SpaceWire.

The data receiving unit 2 provides receiving SpaceWire characters and control codes from a remote device, buffering bytes of packet data and control codes. The output 19 of the received data of block 2 is the same output of the system interface of the device and provides the issuance of bytes of buffered packet data to the host system. The output 18 of the readiness of the received data of block 2 is the same output of the system interface of the device, the input 20 of the data reading of which is the same input of the block 2 of the data reception. The output 40 of the permission to receive data of block 2, connected to the same input of the block 3 of the data flow control, is designed to notify the presence of sufficient free space in the buffer 83 for receiving data. The output 25 of the received control code of block 2 is the same output of the system interface of the device and provides the issuance of the control code to the host system. The output 24 of the readiness of the received control code of block 2 is the same output of the system interface of the device, the input 26 of reading the control code of which is the same input of the block 2 of the data reception. The data receiving unit 2 provides a notification to the data flow control unit 3 and the control unit 4 through the output 31 of the flow control symbol reception connected to the inputs of the same blocks 3 and 4, about the reception of the control symbol of the flow control and through the information acknowledgment output 32 connected to the same name the inputs of blocks 3 and 4, about receiving an information symbol from a remote device. The output 127 "Received NULL" of block 2 is connected to the input of the same block 4 control.

The data flow control unit 3 is designed to implement the lending mechanism required when exchanging packet data in duplex mode between two devices through a communication interface, taking into account the limited amount of buffer memory for receiving data available for each device in the data receiving unit 2. The output 33 of the request for the issuance of a flow control symbol of block 3 connected to the same input of the data output block 1 is intended to initialize the issuance by the block 1 of a flow control control symbol confirming the presence of free buffer space in the data receiving block 2 necessary to receive a certain number of data symbols. In the described device, the amount of credit provided when issuing one symbol of flow control, in accordance with the SpaceWire standard, is assumed to be eight. The output 26 of the credit error of the data flow control unit 3 is connected to the input of the control unit 4 of the same name and is the output of the device system interface of the same name. The data flow control unit 3 is clocked from the synchronization input connected to the synchronization input 13 of the device system interface.

The control unit 4 is designed to monitor the status of the device when signals from SpaceWire are extracted from the received converted code from the received unit 2 and generate control signals under the influence of the state machine and the initial setup signal from the reset input connected to the reset input 14 of the device system interface. The output 38 of the permission to transmit the flow control symbol of the control unit 4 is connected to the input of the data output unit 1 of the same name and is intended to inform that the state machine of the unit 4 has switched to a mode allowing the output of flow control symbols. The first 34 reset output of the control unit 4 is connected to the reset inputs of the data output unit 1, the transmitted symbol converter 5 and the coding unit 6 8b / 10b. The second 35 and third 36 reset outputs of the control unit 4 are connected to the reset inputs of the data receiving unit 2 and the data flow control unit 3, respectively, and are intended to be set to their initial state. The output 27 of the connection establishment of block 4 is the same output of the system interface of the device and is intended to inform the host system about this event. The output 28 of the disconnect error of block 4 is the same output of the system interface of the device and is intended to inform the host system about this event. The output 29 of the credit error of block 4 is the same output of the system interface of the device and is intended to inform the host system about this event. The clock when generating the status signals of the control unit 4 is carried out from the synchronization input connected to the synchronization input 13 of the system interface of the device.

Transmitter 5 for transmitting characters is intended to transcode SpaceWire characters and control codes into 8b characters. The data output 46 of the symbol 8b of the converter 5 is connected to the information input of the coding unit 6 of 8b / 10b and is intended to transmit an eight-bit code of the symbol 8b, which corresponds to either a data byte or the code of a special control symbol. The output 45 of the special character of the converter 5 is connected to the input of the character type of the character of the coding unit 6 of coding 8b / 10b and identifies what type of character 8b is output from the output 46 of the converter 5 in the current clock cycle (data byte or special control symbol). The output 44 of the readiness for issuing the symbol of the converter 5 is connected to the readiness input of the data output unit 1 and provides an indication of the state of readiness of the converter 5 for the arrival of the next SpaceWire symbol or control code from the data output unit 1. If the ready signal is “0”, then the converter 5 in the current cycle does not read information from block 1, since it is busy generating an additional symbol 8b in accordance with its functioning algorithm.

Block 8 encoding 8b / 10b is designed to convert eight-bit characters into 10-bit characters of the standard 8b / 10b. The output 47 of encoded data of block 6 is connected to the input of the same block 7 bit transmission and provides the issuance of a 10-bit code in each clock local synchronization.

The bit transmitting unit 7 is designed to serialize the bit signals of the generated 10-bit symbols 10b and provides the generation of the necessary clock signals for this purpose, which determine the transmission speed of the signals in the communication channel, as well as the clock signals of local synchronization. The local synchronization output 48 of block 7 is connected to the inputs of the same block as the data output unit 2, the data receiving unit 2, the control unit 4, the transmitted symbol converter 5, the encoding block 6 8b / 10b, the elastic buffer 10, and the received symbol converter 11. The output of 49 bit signals of block 7 is the same output of the communication interface of the device.

Block 8 receiving bits is designed to receive the input stream of bit signals from the input 50 bit signals of the communication interface, and the formation of a parallel character code format 10b at the output 51 of the received encoded data connected to the information input of block 9 decoding 8b / 10b. The output data synchronization output 52 of block 8 is connected to the synchronization input of decoding unit 9 of 8b / 10b, to the synchronization input of receiving buffer 10 of characters 8b and to the synchronization input of connection checking unit 12. The output 53 of the connection sign of block 8 is designed to generate a single signal when highlighting one of the special control symbols, the communication check symbol, in the stream of received bit signals and is connected to the inputs of the received symbol converter 11 and the connection checking block 12 with the same input.

The decoding unit 9 8b / 10b is designed to convert the character 10b into a parallel character code of the 8b format at the output 54 of the character 8b connected to the information inputs of the buffer 10 of the characters 8b and the connection checking unit 12. The output 55 of the special symbol attribute of block 9 is connected to the inputs of the same buffer 10 of characters 8b and block 12 of the connection check and determines what type of character 8b (data byte or special control character) is issued from output 54 in the current clock cycle. The write enable output 56 of block 9 is connected to the same input of the buffer 10 of characters 8b and indicates, at a single value, that block 9 has exhibited valid data at its outputs 54 and 55. The output 57 of the coding error of block 9 is connected to the same input of the control block 4 and notifies the detection of errors when decoding symbols 10b.

A buffer of 10 symbols 8b is intended for buffering received symbols in the 8b format at a frequency of reception and making a transition to another time domain with local synchronization. The information output 58 of the buffer 10 is connected to the input of the received symbol converter 11 of the same name and provides the output of an eight-bit symbol code in 8b format. The output 59 of the special symbol sign of the buffer 10 is connected to the input of the received symbol converter 11 of the same name and determines which symbol is read from the output 58 of the buffer 10.

The received symbol converter 11 encodes 8b format symbols into SpaceWire standard symbols. The information output 62 of the converter 11 is connected to the input of the data receiving unit 2 of the same name and ensures the transmission of SpaceWire symbols and control codes received from the remote device into it. The output 63 of the symbol type of the converter 11 is connected to the same input of the data receiving unit 2 and is intended to identify the type of SpaceWire symbol or control code set at the information output 62 in the current clock cycle.

The connection verification unit 12 monitors the status of the connection between the remote devices during their interaction by monitoring the intervals between the receipt of a special control symbol - the communication verification symbol. The output 60 of the error of disconnection of the block 12 is connected to the same input of the control unit 4 and provides a single signal about the connection failure upon expiration of the connection verification symbol. The output 61 of the connection block 12 is connected to the same input of the control unit 4 and provides the formation of a signal of readiness for receiving aligned characters 10b / 8b.

In the data output unit 1, the data output buffer 65 (see FIG. 2) is intended for intermediate storage of packet data arriving at the data input for the output of the buffer 65 connected to the same input 17 of the data output unit 1. The output 15 of the readiness for data output of the buffer 65 is the output of the data output unit 1 of the same name and is intended to notify the host system via the system interface of the possibility of buffering the next byte of data, which is performed when the write signal is sent to the input of the recording buffer 65, which is the input 16 of the record of output unit 1 data. Data buffering is provided when clocking from the synchronization input of the buffer 65 connected to the synchronization input 13 of the data output unit 1. The reset input 68 of the data output unit 1 is connected to the reset input of the data output buffer 65 and is intended for its initialization. The presentation of information in the data packet coming from the system interface of the device to the buffer 65 data output is shown in table 1.

Table 1. Encoding packet data in the system interface of the device for block 1 data output Control flag Data bits (st. ... ml.) Description 0 X ₇ X ₆ X ₅ X ₄ X ₃ X ₂ X ₁ X ₀ 8 data bits one (irrelevant) Packet End Sign

The reading of buffered packet data is provided from the data output 77 of the data output buffer 65 connected to the first information input of the data multiplexer 67. The output 74 of the data readiness of the buffer 65 is connected to the input of the symbol issuing arbitration unit 64 of the same name and is intended to notify of the presence of a data byte ready for issuing. The output 76 of the sign of the end of the packet buffer 65 is connected to the same input of the block 64 arbitration character issuance and is intended to indicate that the previous byte was the last in the packet.

The register 66 of the issuance of the control code is designed for intermediate storage of the control code received at the input of the control code for issuing, connected to the same input 23 of the block 1 of the data output. The output 21 of the readiness for issuing the control code of the register 66 is the output of the data output unit 1 of the same name and is intended to notify the host system via the system interface of the possibility of issuing the next control code, which is performed by applying a write signal to the input of the register register 66 connected to the input 16 of the block record 1 data output. The memorization of the control code is provided when clocking from the synchronization input of the register 66 connected to the synchronization input 13 of the data output unit 1. The control code entering the device from the host system contains two fields: a control code type field and a control code value field. The control code type field indicates for which specific system control signal the given control code is used, for example, a system time stamp or a system interrupt signal. The control code value field contains a specific parameter characterizing the meaning of the transmitted system control signal, for example, the value of the current system time or the vector of a specific interrupt. The reset input 68 of the data output unit 1 is connected to the reset input of the data output register 66 and is intended for its initialization. Reading the recorded control code is provided from the output 81 of the control code of the register 66 connected to the second information input of the data multiplexer 67. The output 80 of the readiness of the control code of the register 66 is connected to the same input of the block 64 of the arbitration of the issuance of characters and is designed to notify the presence of a control code, ready for issuance.

The block 64 of the arbitration of the issuance of characters is designed to regulate the formation and order of issuance of data symbols and control characters defined by the SpaceWire standard, according to the requirements of block 3 control the flow of data and control codes as they arrive and depending on the given priority. The SpaceWire symbols transmitted by the device through the communication interface are divided into channel and information symbols. Information symbols include the data symbol (Nchar), the end of packet symbol (EOP), and the erroneous packet end symbol (EEP). Channel symbols are designed to control the state of the communication channel and, unlike information symbols, are not transmitted to the system interface. Channel symbols include the flow control symbol (FCT) and the null symbol (NULL code). The FCT symbol is used to implement a lending mechanism when transferring packet data between devices interacting via a communication channel. NULL code is designed to maintain the activity of the communication channel and should be constantly transmitted if the channel is not busy transmitting other characters. From the input 71 of the request for the issuance of a flow control symbol of the data output unit 1 connected to the input of the same name of the block 64, a request is issued to issue a flow control control symbol. The output 75 of reading data block 64 arbitration character issuance, connected to the input of the same name of the buffer 65 of the data output, is designed to control the rate of receipt of data from the buffer 65 to generate an internal code of data symbols in block 64. The output 78 of reading the control code of the block 64, connected to the same input register 66 control codes, designed to control the rate of issuance of control codes from the output 81 of register 66. The internal coding of the characters generated in the block 64 is shown in Table 2.

Table 2. Internal encoding of the SpaceWire character type and control codes Symbol Name Designation SpaceWire Symbol Type Code Data byte Zero character (NULL code) Null 000 - Data symbol Nchar 001 X ₀ ... X ₇ Packet End Symbol EOR 010 - Buggy End Symbol EEP 011 - Flow control symbol FCT one hundred - Control code UK 101 X ₀ ... X ₇

An input 72 for permitting the transmission of a flow control symbol of the data issuing unit 1, which is the same input of the symbol issuing arbitration unit 64, is intended for the initial authorization of issuing FCT symbols after establishing a connection with a remote device. The readiness output 37 for issuing a flow control symbol of block 64, which is the same output of the data output unit 1, is intended to notify the flow control unit 3 of the possibility of issuing another FCT symbol. The output 39 of the confirmation of the issuance of the information symbol, which is the same output of the data output unit 1, is intended to notify the flow control unit 3 of the issuance of the next Nchar symbol in order to manage the credit counter of 92 transmitted symbols. The output 43 of the symbol type of the block 64 of the arbitration of the issuance of characters, which is the same output of the block 1 of the data output, is intended to identify, in accordance with the encoding shown in Table 2, the character or control code transmitted through the data multiplexer 67. The information selection output 79 of the unit 64, connected to the control input of the data multiplexer 67, provides a choice of the information source for transmission through the multiplexer 67. When the selection signal is zero, the data byte from the data output buffer 65 is supplied to the information output 42 of the multiplexer 67 from the first information input; at a single value of the selection signal, a control code is supplied from the second information input to the information output 42 of the multiplexer 67 from the buffer 66 for issuing control codes. Thus, as shown in Table 2, the type of data symbol or control code at the output 43 is accompanied by the data byte itself at the output 42 of the symbol output unit 1. The clocking of the block 64 arbitration of the issuance of characters is carried out from the synchronization input connected to the synchronization input 13 of the data output unit 1, the reset input 68 of which is connected to the reset input of the block 64 and is intended for its initialization. The information output 42 of the data multiplexer 67 is the same output of the data output unit 1.

In the data receiving unit 2, the transformed code decoder 82 (see Fig. 3) of the code is used to recognize the characters and control codes of the SpaceWire network in accordance with the coding shown in Table 3, and generate control signals necessary for buffering the received packet data and control codes, as well as state changes of the data flow control units 3 and 4 control units. The information input of the decoder 82 is an input 86 of the symbol type of the data receiving unit 2. The output 32 of the acknowledgment of the information symbol of the decoder 82, which is the same output of the data receiving unit 2 and connected to the write enable input of the data reception buffer 83, is designed to generate a single signal in one of the following two options: either when receiving a Nchar data symbol or when receiving a symbol end of package (EOP). The output 89 of the selection of the control code of the decoder 82, connected to the write enable input of the buffer 84 receiving control codes, generates a single signal confirming the receipt of the control code. The output 31 of the acknowledgment of receipt of the symbol of the flow control, which is the same output of the unit 2 for receiving data, is intended to provide a sign of confirmation of the receipt of the FCT symbol, which is necessary for the credit mechanism to control the flow of data from this device to the remote. The output 127 "Received NULL" of the decoder 82, which is the same output of the data receiving unit 2, generates a single signal confirming the receipt of the NULL code.

The data reception buffer 83 is designed for intermediate storage of received data packets arriving at its information input from the same input 85 of the data receiving unit 2, in the presence of a single signal at the recording permission input. At the output 19 of the received data of the buffer 83, which is the output of the data receiving unit 2 of the same name, a byte output of data packets separated by signs of the end of the packet is provided. The data output from the data reception buffer 83 is ensured according to the “first received, first read” (FIFO) principle, accompanied by a data ready signal at the received data readiness output 18, which is the output of the data receiving unit 2 of the same name, and if there is a single signal at the buffer data read input 83, which is a data reading input 20 of a data receiving unit 2. The output 40 of the permission to receive data of the buffer 83, which is the same output of the data receiving unit 2, indicates the presence of a certain number of free cells in it (in the described embodiment, at least eight) and is intended to control the lending mechanism. When writing data to the data reception buffer 83, it is clocked on the rising edge of the clock signal from the first synchronization input connected to the local synchronization input 88 of the data receiving unit 2. When reading data, the buffer 83 is clocked from the second synchronization input connected to the synchronization input 13 of the data receiving unit 2 and is initialized by the signal from the reset input connected to the reset input 87 of the data receiving unit 2.

The control code reception register 84 is intended for intermediate storing of the received control code received at its information input from the information input 85 of the data receiving unit 2, if there is a corresponding single signal at the recording permission input. At the output 25 of the received control code of the register 84, which is the same output of the data receiving unit 2, the control code is provided. Reading the control code from the register 84 is accompanied by a single ready signal at the ready output 24 of the received control code, which is the output of the data receiving unit 2 of the same name, and if there is a single signal at the read input of the control code of the register 84, which is the same input 26 of the data receiving unit 2. When writing the control code, the control code reception register 84 is clocked on the rising edge of the clock signal from the first synchronization input of the register 84 connected to the local synchronization input 88 of the data receiving unit 2. When reading the control code, the register 84 is clocked from the second synchronization input connected to the synchronization input 13 of the data receiving unit 2 and is transferred to the initial state by a signal from the reset input connected to the reset input 87 of the data receiving unit 2.

In the data flow control unit 3 (see FIG. 4), the credit request generator 90 is designed to generate an FCT symbol request signal at the output 33 of the request for issuing the flow control symbol of block 3 in the presence of enable signals at the readiness inputs 96 for the flow control symbol and 94 permission to receive data of block 3 and depending on the status of the counter 91 received characters. An input 94 for receiving data from block 3 is the first input of the shaper 90. The input 96 of the readiness for issuing the flow control symbol of block 3 is the second input of the shaper 90. The state output 100 of the counter of the received symbols 91 is connected to the third input of the shaper 90. The synchronization input 13 of the block 3 connected to the synchronization inputs of the generator 90 credit requests, the counter 91 received characters, the counter 92 transmitted characters and the detector 93 credit errors, provides synchronization of their work at the frequency of the system interface. The reset input 95 of block 3 is designed to set the initial state and is connected to the reset inputs of the credit request generator 90, the received symbol counter 91, the transmitted symbol counter 92 and the credit error detector 93. The counter 91 of the received symbols provides the formation of a binary code that determines the number of information symbols that are allowed to be received in this device. The first control input of the counter 91, connected to the output of the credit request generator 90, is intended to increase the state of the counter 91 by eight when a request signal for issuing a flow control symbol is issued. The second control input of the counter 91, which is the input 97 of the acknowledgment of the information symbol of block 3, is intended to reduce by one the contents of the counter 91 when each information symbol is received. The state of the counter 91 of the received symbols under the influence of control signals is changed along the front of the clock signals from the synchronization input 13 of block 3 to the synchronization input of the counter 91. The credit error of the reception of the counter 91 is connected to the first information input of the credit error detector 93 and is designed to generate an error signal when attempt to reduce the counter state below the maximum permissible value. The counter 92 transmitted characters provides the formation of a binary code that determines the number of information characters that are allowed to transmit from this device. The first control input of the counter 92, which is the input 98 of the acknowledgment of the receipt of the symbol of the flow control unit 3, is intended to increase the state of the counter 92 by eight upon receipt of each symbol FCT. The second control input of the counter 92, which is the input 99 of the confirmation of the issuance of the information symbol of block 3, is intended to reduce by one the contents of the counter 92 of the transmitted characters. The change in the state of the counter 92 transmitted symbols when applying control signals is carried out along the front of the clock signals from the synchronization input 13 of block 3 to the synchronization input of the counter 92. The credit error output of the counter 92 is connected to the second information input of the credit error detector 93 and is designed to generate an error signal when an attempt to increase the state of the counter 92 above the maximum permissible value. The credit error detector 93 provides the formation of a combined clock error signal of the credit error at its output, which is the output 26 of the credit error of the block. The synchronization input of the detector 93 is connected to the synchronization input 13 of the data flow control unit 3.

In the control unit 4 (see Fig. 5) that implements the state machine, the state register 103 is designed for online storage and monitoring of the state of the phases of the device. In fact, the state register 103 is the memory of the state machine, which is implemented by the control unit 4. Register 103 can be read as well as writable by the host system (not shown in FIG. 5). Filling the register is performed bitwise by signals from the block 2 of the data reception or processor of the host system. The state output 114 of the register 103 is connected to the first control input of the new state generating unit 104 and to the control input of the control signal generator 105. The connection establishment output 27 of the status register 103 is the same output of the control unit 4. A single signal value at this output indicates a connection at the SpaceWire standard exchange level. The output 28 of the error of disconnection of the state register 103 is the same output of the control unit 4. A single signal value at this output indicates a connection error when exchanging data between remote devices. The output 28 of the credit error of the state register 103 is the same output of the control unit 4. A single signal value at this output indicates a credit error when exchanging data between remote devices. The reset input 14 of the control unit 4 is designed to set the initial state and is connected to the reset inputs of the state register 103, the shaper 105 of the control signals and the block 106 delay. The recording of status bits in the register 103 is provided on the rising edge of the clock signal at its synchronization input, which is the synchronization input 13 of the control unit 4.

Block 104 of the formation of a new state is designed to implement the logic of the state machine, which performs the function of an automaton that goes under the influence of input signals into various states. The control signal generator 105 provides the generation of control signals by which the state machine transfers the data output unit 1, the data reception unit 2, and the data flow control unit 3 to the initial states, thus allowing the correct operation of the device as a whole. The delay unit 106 is designed to generate timeouts necessary for the state machine to function properly when establishing and maintaining a connection with the remote side through the communication interface. From the exemplary implementation of the state machine graph shown in FIG. 16, the need for the implementation of two timeouts T1 and T2 is visible. In the implemented device layout, timeout values are selected in accordance with the requirements of the SpaceWire standard: T1 = 6.4 μs, T2 = 12.8 μs. The local synchronization input 113 of the control unit 4 is connected to the synchronization inputs of the control signal generator 105 and the delay unit 106. The connection establishment input 107 of the control unit 4 is the first input of the new state generating unit 104. Block 108 credit error input 108 is the second input of block 104. Block 4 disconnect error input 109 is the third input of block 104. Block 4 character encoding error input 110 is the fourth input of block 104. Block 4 flow control acknowledgment input 111 is the fifth block input 104. Input 112 for acknowledging the information symbol of block 4 is the sixth input of block 104. Input 178 “Received NULL” is the seventh input of block 104 for generating a new state, the output 115 of which is connected to the input of the recording of status bits histra 103 state. The control output 116 of the control signal generator 105 is connected to a control input of the delay unit 106, the output of which is connected to the second control input of the new state generating unit 104. The output 38 of the resolution of the transmission of the symbol of the flow control of the driver 105 of the control signals is the same output of the control unit 4. The first output 34 of the reset of the driver 105 is the same output of the control unit 4. The second output 35 of the reset of the driver 82 is the same output of the control unit 4. The third output 36 of the reset shaper 82 is the same output of the control unit 4.

In the transmitted symbol converter 5 (see FIG. 6), the output data register 117 is intended to fix a packet data byte or control code during a clock cycle to convert it to a symbol code of format 8b. The data input of the register 117 is the input 128 of the data of the transmitter 5 transmitted characters. The data are written into the register 117 on the rising edge of the clock signal at its synchronization input, which is connected to the synchronization inputs of the first symbol type register 118, the first trigger code 120 of the control code, with the counting input of the first counter 123 and is the input 130 of the local synchronization of the transmitter 5 of the transmitted symbols. The reset input 131 of the converter 5 is connected to the reset inputs of the output data register 117, the first symbol type register 118, the first control code trigger 120 and the first counter 123 and provides a single signal to bring them to the zero state. The output 133 of the register 117 is connected to the first information input of the output multiplexer 122. The first symbol type register 118 is intended to fix a SpaceWire symbol type code in the current clock cycle. The data input of the first symbol type register 118 is a symbol type input 129 of the transmitted symbol converter 5. The output 132 of the first symbol type register 118 is connected to the input of the selector 119 of the control code and to the first input of the first ROM 121 constants.

The selector 119 of the control code provides selection of the control code from the type of SpaceWire symbol entering its input, forming a single signal at the output 134. The output 134 of the selection of the control code of the selector 119 is connected to the first input of the third AND element 126, the output of which setting the flag 136 is connected to the trigger data input 120 of the control code and provides the translation of the trigger 120 from the zero state to a unit on the rising edge of the clock of the local synchronization signal.

The trigger code 120 of the control code is designed to generate a bit of the flag of the control code (CC) by fixing for one clock cycle the sign of the control code. This is necessary because converting the control code into 8b format characters takes two clock cycles. The direct output 137 of the trigger code 120 of the control code is connected to the third input of the first ROM 121 constants, with the first input of the first element 124 AND, as well as the first inverse input of the second element 125 I. The inverse output 135 of the trigger 120 is connected to the second input of the third element 126 I. Zero the value at the inverse output of the trigger 120 and, accordingly, the output 136 of the third element 127 And, returns the trigger 120 to its initial zero state along the rising edge of the next clock signal.

The first ROM 121 constants provides storage of codes for special control characters defined by the encoding of characters 8b. The output 140 of the special symbol code of the ROM 121 is connected to the second information input of the output multiplexer 122 and provides eight-bit constants that define special control characters when encoding characters 8b, which are used in this technical solution for encoding SpaceWire control characters and control codes of various types. Such control characters will include the characters EOP, EEP, FCT and NULL used to control the data stream and format them; when generating a special character in the converter, 5 bytes of data are not transmitted through register 117. The output 45 of the special character flag of the first ROM 121 constants is connected to the control input of the output multiplexer 122 and is the same output of the transmitter 5 transmitted characters. A single value at the output 45 of the first ROM 121 constants indicates that one of the special control characters (special characters) read from the output 140 of the ROM 121 should be output from the output 46 of the multiplexer 122. The rules for generating special characters at the outputs of the first ROM 121 constants are shown in table 3.

The output multiplexer 122 is designed to select the type of symbol 8b transmitted to its output, which is the output 46 of the symbol data 8b of the transmitted symbol converter 5, depending on the value of the sign of the special symbol on the control input. When the value of the sign of the special symbol is zero, output byte of multiplexer 122 is issued a data byte from the first information input of multiplexer 122 from the register 117 of the output data. With a single value of the sign of the special symbol, output 46 of the multiplexer 122 is issued from the second information input, the code of the special symbol 8b from the first ROM 121 constants.

The first counter 123 is designed to determine the time interval T3, through which a special control symbol — a communication support symbol — must be generated by the transducer 5 of transmitted symbols to maintain the state of the connection between devices (according to Table 4, K28.5 are used for the implementation of 12 of the special characters 8b encoded for) . The width of the first counter 123 is chosen equal to five, so the interval T3 is equal to 32 clock cycles of local synchronization. The transfer output 139 of the first counter 123 is connected to the second input of the first ROM 121 constants, with the second inverse input of the second element 125 AND, with the second input of the first element 124 AND and provides the formation of a single signal every 32 periods of the clock signal at zero state of its bits. The first element And provides the formation of a single signal at its output 138 of the prohibition of counting in case of coincidence of the transfer signal and the flag of the control code in one cycle. The counter ban output 138 of the first element 124 AND is connected to the inverse reset input of the first counter 123. When the counter ban signal is a single value, the counter 123 is reset to zero for a second additional clock cycle. The second element 125 And provides the formation of a single value of the signal of readiness for issuing a symbol only in the absence of a transfer signal and a control code flag. The output 44 of the readiness of the issuance of the symbol of the second element 125 And is the same output of the Converter 5 transmitted characters.

Table 3. The formation of special characters on the outputs of the ROM 121 ROM Inputs ROM outputs Comments First entry Second entrance Third entrance Exit 47 Exit 23 Character type code Carry signal UK flag Special character 8b Sign of special character 8b 000 0 0 K28.0 (00011100) one Null code 001 0 0 XXX 0 Data Byte (Nchar) 010 0 0 K28.3 (01111100) one EOR 011 0 about K28.4 (10011100) one EEP one hundred 0 0 K28.2 (01011100) one FCT 101 0 0 K28.6 11011100 one Control code XXX one 0 K28.5 (10111100) one Communication Support Symbol XXX X one XXX 0 UK data byte

In block 7 of the transmission of bits (see Fig.7), the generator 141 of the clock transmission of bits ensures the formation of the base synchronization sequence with a frequency selected equal to 1 GHz. The output of the generator 141 is connected to the input of the first frequency divider 142 and to the synchronization input of the output shift register 143. The first frequency divider 142 is used to generate local synchronization clock signals and is connected to the write input of the output shift register 143 and is the local synchronization output 48 of the bit transmission unit 7. The frequency of the clock signals of local synchronization is chosen equal to 100 MHz. The output shift register 143 is designed to convert a parallel code of a ten-digit character into a serial one. The serial output of the output shift register 143 is connected to the output driver 144 of the bit signal, providing the generation of the bit signal in the required form for transmission to the communication channel.

In the block 8 for receiving bits (see Fig. 8), the generator 146 of the clock signals for receiving bits provides the formation of the base clock sequence with a frequency selected equal to 1 GHz. The output of the generator 146 is connected to the input of the second frequency divider 147 and to the synchronization input of the input shift register 148. The second frequency divider 147 is used to generate synchronization clock signals and is connected to the synchronization input of the alignment unit 149 and is the output synchronization output 52 of the data of the bit receiving unit 8. The frequency of the clock signals synchronization of data reception is selected equal to 100 MHz. An input 50 of the bit signals of the bit receiving unit 8 is connected to the input of the input signal amplifier 150 and to the phase adjustment input of the bit receiving clock 146. The input signal amplifier 150 provides amplification of the signals received from the communication channel and the formation of a stream of bit signals at the output connected to the serial input of the equalization unit 149. Input shift register 148 is designed to convert serial code to parallel. The serial output of the input shift register 148 is connected to the input of the alignment unit 149. Block 149 alignment provides the formation of reliable 10-bit characters that are output 51 of the received encoded data, which is the same output block 8 receiving bits. At the output 53 of the sign of the connection of the alignment block 149, which is the same output of the bit receiving unit 8, the generation of a single level with reliable formatting of 10-bit characters is provided.

The decoding unit 9 8b / 10b is designed to convert 10-bit characters eight-bit characters of the standard 8b / 10b. The output 54 of the symbol 8b of the decoding unit 9 of the 8b / 10b is connected to the information inputs of the buffer 10 of the symbols 8b and the connection verification unit 12 and is intended to transmit the generated eight-bit symbol 8b. The output 55 of the special character flag of block 9 is connected to the inputs of the same symbol buffer 10 of characters 8b and connection check block 12 and determines which characters 8b at output 54 are not data bytes. The output 56 of the write permission block 9 is connected to the same input of the buffer 10 characters 8b. A single value of the signal at this output means that the next symbol 8b is generated at the output 54 of block 9. The output 57 of the coding error of block 9, connected to the same input of the control block 4, ensures the formation of a single signal in case of detection of an error in decoding symbols. The format of the symbols 8b, which are generated in block 9 decoding 8b / 10b, are given in table.3.

A buffer 10 of symbols 8b is intended for intermediate storage of received symbols 8b and provides a transition from a temporary domain with a clock synchronization frequency to a temporary local synchronization domain of this device. The writing of characters 8b to the buffer 10 is carried out by the clock signals of the data reception unit 8 of the data reception, reading from the buffer 10 is performed by the clock signals from the output 48 of the local synchronization of the block 7 data transmission. Information output 58 and output 59 of the sign of the special symbol of the buffer 10 are connected to the inputs of the converter of the received symbols of the same name.

In the received symbol converter 11, a second constant ROM 151 converts the character codes of the 8b format into the SpaceWire character representation codes. The first input of the second constant ROM 151 is an information input 158 of the received symbol converter 11 and is connected to the data input of the input data register 157 to provide the symbol code 8b. The second input of the ROM 151 is the input 159 of the special character of the converter 11, a single signal value at this input indicates that the current symbol 8b is a special control symbol. The enable input of the ROM 151 is the input 160 of the sign of the connection of the Converter 11, a single signal value at this input translates the outputs of the second ROM 151 constants in the active state. The symbol type output 161 of the second ROM 151 of the constants is connected to the data input of the second symbol type register 153 and the first information input of the input multiplexer 155. The output 162 of the control code selection of the second ROM 151 of the constants is connected to the data input of the second control code trigger 153 and to the type 155 register reset input input character. The rules for generating SpaceWire symbol codes at the outputs of the second ROM 151 constants are shown in Table 4.

The second register type 152 symbol type is designed for intermediate storage of the internal code type symbol SpaceWire for one clock cycle. The synchronization input of the second register 152 is the input 157 of the local synchronization of the received symbol converter 11 and is connected to the synchronization inputs of the second trigger 153 of the control code, the input symbol register 155 and the input data register 156. The output 164 of the delayed symbol type of the second register 152 of the symbol type is connected to the second information input of the input multiplexer 154. The second trigger 153 of the control code ensures the formation of the flag upon receipt of the control code, a single value of which at the output 163 is stored for a clock cycle. The output 163 of the control code flag of the trigger 153 is connected to the control input of the input multiplexer 154. The input multiplexer 154 selects the internal code of the SpaceWire symbol type either directly from the second ROM 151 when the UK flag is zero on its control input, or from the second symbol type register 152 at single state of the flag of the Criminal Code. The output 160 of the input multiplexer 154 is connected to the data input of the input symbol type register 155. The input symbol type register 155 is intended for transmitting an internal code of the SpaceWire symbol type to its output 63 of the received symbol type, which is the output of the converter of the received symbols of the same name. The input data register 156 is designed to transmit a byte of Nchar SpaceWire symbol data or a control code parameter to its output, which is the information output 62 of the received symbol converter 11.

Table 4. The formation of internal codes such as SpaceWire characters at the outputs of the second ROM 151 constants ROM Inputs ROM outputs Comments Enable entry First entry Second entrance Exit 161 Exit 162 Sign of connection Special character 8b Sign
special character Character type code Sign of control code 0 X X Z Z Outputs in the third state one K28.0 (00011100) one 000 0 Null code one X 0 001 0 Data Byte (Nchar) one K28.3 (01111100) one 010 0 EOR one K28.4 (10011100) one 011 0 EEP one K28.2 (01011100) one one hundred 0 FCT one K28.6 11011100 one 101 one Control code one K28.5 (10111100) one 000 0 Instead of a special communication support symbol, a NULL code is issued one Rest X 000 0 Null code

In the connection verification block 12 (see FIG. 10), the communication support symbol decoder 165 selects the communication support symbol by generating a single signal at its output 175. The output 175 of the communication support symbol selection of the decoder 165 is connected to the reset input of the second counter 167 and to the first input the first element 168 OR, the output of which is connected to the data input of the trigger 166 communication. The enable input of the decoder 165 is connected to the input 173 of the connection attribute of the connection verification unit 12, with the inverse reset input of the communication setup trigger 166 and with the first inverse input of the second OR element 169. A zero level signal at this input provides a ban on the operation of the decoder 165, in which the output of the decoder is in a passive zero state. A single signal level of the connection indicator activates the operation of the decoder 165. The first input of the decoder 165 is the information input 171 of the connection verification unit 12 and ensures that the 8-bit binary code of the character 8b is transmitted to the decoder. The second input of the decoder 165 is the input 172 of the special character of the connection verification unit 12 and provides a single-bit control signal, the unit value of which sets the decoder 165 to decode the incoming binary code to its first input as a special control symbol. When the value of the sign of the special symbol is zero, the decoder 165 ignores the binary code at the first input, since this binary code is a data symbol that must be written to the input data register 156.

The trigger 166 connection is designed to fix the establishment of a connection in which it becomes possible to exchange data between interconnected devices, that is, each device receives permission to transmit data to a remote device. The trigger synchronization input 166 is the synchronization input 174 of the connection verification unit 12 and is connected to the counting input of the second counter 167. At a single value at the input of data on the increasing clock input, the communication setup trigger 166 is in a single state, which indicates the establishment of the connection. The connection establishment output 61 of the communication setup trigger 166 is connected to the second input of the first OR element 168, to the first input of the fourth AND element 170, and is the connection establishment output of the connection verification unit 12.

The second counter 167 is designed to monitor the time interval during which a special control symbol, a communication support symbol, must be received from a remote device to maintain a connection. If the specified special control symbol does not arrive within a certain time interval (for example, 64 cycles), then the second counter 167 provides the formation of a transfer signal notifying of the disconnection error. The transfer output 176 of the second counter 167 is connected to the second input of the second OR element 169, which provides the formation of a single value of the disconnect sign in the absence of a special symbol for checking communications or in case of loss of synchronization. The output 177 of the sign of disconnection of the second element 169 OR is connected to the second input of the fourth element 170 AND, which ensures the formation of a single value of the error of disconnection only if there is an established connection. The output of the fourth element 170 AND is the output 60 of the disconnect error of the connection verification unit 12.

The device operates as follows. The objective of the device is to provide data exchange between a local host system (a computer or processor node having a local data memory) and a remote host system through a similar remote communication interface device. The local device and its local host system are hereinafter referred to as “Side A”, the remote communication interface device and its host system - “Side B”. To accomplish this task, this device organizes the connection in a communication channel connecting parties A and B, and provides data flow control. A communication channel supporting duplex serial data transmission mode is formed (see Fig. 1) by output 49 and input 50 by simplex bit-signal transmission lines.

The device has three levels of connection and information exchange control: SpaceWire exchange level, adaptation level and bit synchronization level. The state machine of each control level is represented by a state diagram. States are represented as ellipses, state names are indicated inside. Transitions from state to state are indicated by arrows. The event that caused the transition from state to state is indicated next to the transition arrow.

Before establishing a connection at the SpaceWire exchange level, it is necessary to establish a physical connection at the adaptation and bit synchronization levels. The state machine of the level of bit synchronization, which determines the exchange of signals at the physical level (PHY), is shown in Fig.11. After the SpaceWire exchange layer has allowed the PHY layer to begin operation, the transmitter of the 8b / 10b encoding unit starts sending special characters to establish bit synchronization with the receiver in the bit receiving unit 8 of the remote device. To this end, interconnected devices send each other primary synchronization symbols of format 10b, defined as symbols D10.2. After coding at the output 47 of block 6, it has the form "1010101010". After switching on, blocks 6 in each of the devices send synchronization symbols D10.2 to the channel during a certain time interval. In this state of Bit Sync, D10.2 sending continues and the codec waits for receive synchronization. After the reception synchronization is established, the machine switches to the Alignment state. For this, the transmitter generates a special K28.5 communication support symbol in the 8b format, after encoding in the 10b format it has the form “1100000101”. When this symbol appears in the receiver, the data is considered aligned and parallel 10-bit sequences appear, as reflected in Fig. 12, transmitted to the overlying level. Block 8 receiving bits at the output 53 sets the unit signal level of the sign of the connection. Upon receipt of this symbol, the PHY level goes into a ready state (see Fig. 11).

To organize the interaction of the physical level and the SpaceWire exchange level, the SpaceWire adaptation level is introduced, the tasks of which are:

1) encoding and decoding of SpaceWire characters into 8b characters (character sequence);

2) determination of disconnection errors;

3) coordination of the frequencies of the receiver and transmitter.

The adaptation layer is responsible for encoding SpaceWire characters into 8b characters. The adaptation level machine shown in FIG. 13 starts its operation after turning on the device and waits for synchronization of the PHY level. After synchronization is established, the transition to the Waiting state is performed. After 2 μs, the adaptation level automaton transitions to the Start state. In this state, periodic sending of special characters for K28.5 communication support begins. After receiving the communication support symbol and sending at least one symbol after this, the device switches to the Ready state. In this state, the conversion of 8b-characters to SpaceWire characters and vice versa is allowed, and in this way conditions are prepared for receiving the first NULL code, which is an important event for the state machine of the SpaceWire exchange level. If within a certain time a special symbol for communication support has not been received or an encoding error of 8b / 10b has been detected, a transition to the Error state occurs. For the SpaceWire exchange level, a coding error signal is generated at the output 57 of decoding unit 9 8b / 10b, which will reset the SpaceWire status machine (at the exchange level). After that, if the underlying PHY level has not lost synchronization, it will switch to the Standby state. If PHY level synchronization is lost, it switches to the Reset state.

The determination of the disconnect error that the SpaceWire exchange layer processes is the responsibility of the adaptation layer. To detect a disconnect, the transmitter from the transmitter 5 of transmitted symbols sends a special communication support symbol every 32 symbols (see timing diagrams in Fig. 14), inserting it into the general symbol stream. If an error occurs on one of the parties, this side goes into the Error state, and then into the Waiting state. In these states, the K28.5 special character is not sent. The opposite side, having not received a special communication support symbol for a long time (within 640 ns - 960 ns at a transmission frequency of 1 GHz), detects a disconnect error and also switches to the Error state.

The exchange level of the SpaceWire standard and higher operate in accordance with the documentation of the SpaceWire standard, without changes.

Changing the states of the data output unit 1, the data receiving unit 2, the data flow control unit 3, and the control unit 4 is carried out in accordance with the state machine diagram (see Fig. 15) of the SpaceWire exchange control level: from device initialization by the initial setup signal starting from resetting one of the parties connected by a communication channel to a state of normal operation, in which packet data and control codes are transmitted in both directions. From the Reset state, in which the data receiving unit 2 does nothing, it goes into the Run state. In this state, block 2 is running and is waiting for the first bit to be received. When the data receiving unit 2 receives the first NULL code, it enters the Connection mode, and the disconnection detection mechanism is turned on and only NULL codes are allowed to be received. After receiving the FCT symbol from the remote device of the communication interface, the data receiving unit 2 enters the Run state and can receive NULL codes, FCT symbols, information symbols, including Nchar data symbols and EOR / EEP packet end symbols, and control codes (UK), which transmitted over the SpaceWire network. In this state, the device includes a mechanism for detecting disconnect and coding errors.

After a reset or an error in the channel, the data output unit 1 is placed in the Reset state and, when the connection is initialized at the Exchange level, SpaceWire can be in one of four states:

1. Reset. The data output unit 1 does nothing.

2. Launch. The data output unit 1 sends only NULL codes. It is not ready to transmit information symbols and does not transmit FCT symbols.

3. Connection. Transmission of FCT characters / NULL codes. The data output unit 1 sends FCT symbols or NULL codes and is not ready to transmit information symbols.

4. Operating mode - the normal operating mode of the data output unit 1 (FCT / Nchar / NULL / UK transmission). It sends FCT characters, NULL codes, information characters (Nchar / EOP) and control codes.

The control unit 4 performs the function of a control machine in the device, which is a state machine, the graph of which is presented in Fig. 15. It controls the operation of the data output unit 1, the device data reception unit 2 and the flow control unit 3, receiving status signals from them and sending them control signals. Two types of signals serve as events or conditions that cause transitions from state to state: external (for example, reset) and internal control signals. Internal control signals causing transitions between states are:

- T μs passed - the signals from the timers in block 83 of the delay cause the transitions “6.4 ms passed” or “12.8 μs passed” and show the occurrence of an event - timeout (time delay), after which the transition from one state to another. Delay times are selected as nominal values in accordance with the requirements of the SpaceWire standard.

- Received a NULL code - the signal is set at the output 127 of the data receiving unit 2 (see Fig. 3) when the first NULL code is received.

- Received FCT symbol - the signal is installed at the output 31 of the acknowledgment of the reception of the flow control symbol of the data receiving unit 2 and means the fact that the FCT symbol is received. Reception of the FCT symbol is correct only in the states Connection or Operating mode. Reception of the FCT symbol in other states is perceived as an error.

- Received Nchar - the signal is installed at the output 32 of the acknowledgment of the information symbol of the data receiving unit 2 and means the fact of the adoption of the information symbol. Reception of an information symbol in any state other than the Run state is perceived as an error.

- Disconnect error - the signal at the output 60 of the disconnection error of the connection verification unit 12 means out of sync in the communication channel. The mechanism for determining the disconnect error in block 12 starts when, after establishing a connection, and exiting the Reset state.

- Encoding error - the signal at the output 57 of the encoding error of decoding unit 9 of decoding 8b / 10b means determining an error in the received symbol or an error due to incorrect encoding. The determination of the encoding error is allowed only when the data reception unit 2 is started and after the first NULL code is received.

- Credit error - a signal at the output 26 of a credit error of the data flow control unit 3 means that information symbols are received that are not expected (receiving an information symbol at the moment when all information symbols are already received in response to the sent FCT symbols). Also, a credit error occurs when receiving an FCT symbol at a time when the credit increase exceeds the maximum value, which according to the SpaceWire standard should be at least 56 bytes).

In addition to the internal control signals generated in the device blocks, the state machine generates the following internal conditions for transitions:

- Receive error - this condition indicates the occurrence of a disconnect error or an encoding error signal.

- Symbol sequence error - this condition is generated by the state machine differently depending on the current state:

a. Any characters received before the first NULL code are ignored. In the Standby and Ready states, this leads to an error, which causes the transition to the Reset state. In the state diagram (see FIG. 11), the events “Received FCT” and “Received Nchar” are indicated.

b. After receiving the first NULL code, receiving the FCT character before sending the first NULL code (that is, in the Run state) is perceived as an error.

c. An information symbol can be accepted only after a NULL code and FCT symbol are received, otherwise the situation is erroneous. Therefore, in the Connection state, the Nchar Received event causes the device to reset. Thus, information symbols can only be received in operating mode.

The device transmits data to the communication channel in the operating mode sequentially (see timing diagrams in Fig. 16), reading packet data bytes from the data output buffer 66 of the data output unit 1 as they arrive from the host system. If there is a readiness to output data in the form of a unit level at the output 44 of the second element 125 AND in the converter 5 (see Fig. 16, f), the next data byte is read from the input 128 of the data of the converter 5 and written to the input data register 117 (see. 16b) and then through the first information input of the multiplexer 122, the data 46 of the symbol 8b of the converter 5 is output 46 (see Fig. 16, d). At the same time, an internal symbol type code equal to “001” was recorded in the symbol type register 118 (see Table 3). The data byte goes to the output 46 of the symbol 8b, since the output 45 of the first ROM 121 sends a zero level to the control input of the multiplexer 122 (see Fig. 16, e). The zero sign signal of the special symbol at the output 45 of the converter 5 confirms that in the coding block 6 8b / 10b, the symbol 8b arriving in the current clock cycle should be interpreted as a data symbol. If the next byte of data transferred was the last in the packet, then the symbol of the end of the packet is transmitted in the next clock cycle. The EOR symbol type code is “010”, in accordance with it the ROM 121 at the output 140 forms the special symbol K28.3, and the sign of the special symbol will take a single value (see Fig. 16, diagrams d, e). From the second information input of the output multiplexer 122, the eight-bit code of this special character 8b is transmitted to its output 46, since a single value is present at the control input.

When the data output buffer 65 in block 1 is empty and the transmission of data bytes through the device to the other side of the connection is suspended, a NULL code is transmitted (a symbol type zero code is written to register 118) so as not to lose synchronization of the device connection. ROM 121 in this situation forms another special character - K28.0 (see Fig. 16, diagrams b, c, d), which means the transmission of a NULL code (see Table 4). Timing diagrams illustrating the process of transmitting a control code in a packet data stream are shown in FIG. First, the special symbol K28.6 will be sent to the channel as the header of the criminal code, and the data symbol next to it is a parameter of the control code (see Fig. 18, diagrams b, c, d). To do this, the multiplexer 122 will first give the byte code of the constant from the ROM 121 together with a single sign of the special character at the output 45 (see Fig. 18, f), and at the next clock cycle - the byte of the control code parameter from register 117. If the control code and the special character transmit coincide communication support, the control symbol will be transmitted first, then the communication support symbol (see Fig. 19, diagrams b, c, d, e, f).

Received symbols of format 8b are buffered in buffer 10, from which they are converted into SpaceWire symbols into a converter 11 of received symbols (see Fig. 9). The received symbols 8b (see FIG. 4) come from the input 158 of the converter 11 to the first input of the second ROM 151, which decodes the symbols 8b into an internal code of the SpaceWire symbol type (see Table 4, FIG. 17, d). The data byte is directly recorded in the input data register 156 (see Fig. 17, f) and then from the output 62 are written to the output data buffer 83 of the block 2. At the same time, a code of the type of data symbol from the output 161 of the ROM 151 through the input multiplexer 154 is written to input symbol type register 155 (see FIG. 17, i). The decoded code decoder 82 recognizes the Nchar symbol, generating a single signal at the output 32. If a control code is received, a single sign of the code at the output 162 of the ROM 151 is generated (see Fig. 17, g). This feature is fixed as a flag in the second trigger 153 of the control code (see Fig.17, h). The control type code is delayed in the second register 152 (see FIG. 17, f). At the next cycle, a single signal at the output 163 switches the output multiplexer 154 to the second information input and the type of symbol in register 155 is written from register 152 (see Fig. 17, i). In this case, the byte of the control code parameter will fall into the register 1566, which will go to the control register block receiving register 84.

The proposed technical solution will remove a significant part of the problems of SpaceWire technology that were solved when developing this communication interface device for the SpaceWire network: increasing the bit rate and transmission distance in the channel. During physical implementation of pairing with a communication channel (at the PHY level), various signal levels can be used in the device, which is reflected in a significant expansion of the scope of SpaceWire modules. The device can use LVDS according to the standards of Serial RapidIO (which are fully implemented at speeds of 1 Gbit / s), physical channels on copper cables and fiber-optic channels. There are conditions for the use in the technical implementations of this device of proven technical solutions, for example, for galvanic isolation. From the electronic component base available on the market for PHY, signals with PECL / LV-PECL FibreChannel levels can be used, cable products and Infmiband connectors, and other well-known technical solutions can be applied. Thus, this technical solution contributes to the achievement of higher indicators of reliability and speed, has significant functional advantages compared to well-known analogues, and is implemented using the current level of technology.

Claims (3)

1. A communication interface device for the Space Wire network, comprising a data output unit, a data reception unit, a control unit and a data flow control unit, the output of a request for issuing a flow control symbol of which is connected to the input of the data output unit of the same name, the output of which is ready to issue a flow control symbol of connected to the input of the data flow control unit of the same name, inputs of acknowledgment of receipt of the flow control symbol and acknowledgment of receipt of the information symbol of which are connected respectively to one the outputs of the data receiving unit and the inputs of the same name of the control unit, the character encoding error output of which is the symbol encoding error output of the system interface of the device, the reset input of the device system interface is the reset input of the control unit, the first and second reset outputs of which are connected to the reset inputs of the data output unit, respectively and a data receiving unit, the “received NULL” output of which is connected to the control unit input of the same name, the data reading input of the device’s system interface is are the input of the data receiving unit of the same name, the data outputs for receiving and the readiness of the data for receiving are the corresponding outputs of the device system interface, the credit error of the device system interface is the output of the data flow control unit of the same name and connected to the same input of the control unit, the third reset output of which is connected with the reset input of the data flow control unit, inputs for confirming the issuance of an information symbol and permitting the reception of data of which are connected to the output of the data issuing unit and the data receiving unit respectively, the output readiness output of the system interface of the device is the same output as the data issuing unit, the recording and data inputs for issuing the system interface of the device are the corresponding inputs of the data issuing unit that contains the character issuing arbitration unit, the issuing buffer data, the output of readiness for the issuance of data of which is the same output of the data output unit, the entries of the record and data for the output of which correspond inputs of the data output buffer, outputs confirming the issuance of the information symbol and the readiness for issuing the flow control symbol of the data issuing block are respectively the outputs of the arbitration block of character issuing with the same name, the input of the request for issuing the flow control symbol of which is the same input as the data issuing block, the reset input of which is the reset input the block of arbitration of the issuance of characters and is connected to the reset input of the data output buffer, the data readiness output of which is connected to the input of the same name block character issuance arbitration, the synchronization input of which is connected to the synchronization input of the data output buffer and is the synchronization input of the data output unit, the inputs of the issuance of permission and transmission permission of the flow control symbol of which are the inputs of the symbol arbitration unit of the same name, the data reading output of which is connected to the input of the output buffer data, the output of the sign of the end of the packet of which is connected to the input of the same block arbitration character issuance; the data reception unit contains a data reception buffer and a decoded code decoder, the acknowledgment of the receipt of the flow control symbol and the “received NULL” output of which are the inputs of the same name of the control unit, the received data output of which is the output of the data reception buffer of the same name, the outputs of the data reception permission and readiness of received data which are respectively the outputs of the same name of the data receiving unit, the data reading input of which is the reading input of the data receiving buffer, the buffer write permission input and the data reception is connected to the output confirmation message of the decoded code decoder information symbol and is the output of the data reception unit of the same name, the reset input of which is the reset input of the data reception buffer, characterized in that the transmitted symbol converter, the coding block 8b / 10b, the transmission unit bits, a block for receiving bits, a decoding block 8b / 10b, a symbol buffer 8b, a converter of received symbols, a connection checking block, the disconnect error output of which is connected to the input of the same name control unit house, the first reset output is connected to the inputs of the transmitter of the transmitted symbols and the coding unit 8b / 10b of the same name, the information input of which is connected to the data output of the symbol 8b of the converter of transmitted symbols, the output of which the symbol is ready is connected to the readiness input of the data output unit, the information output and the output of the symbol type of which is connected respectively to the data inputs and the symbol type of the converter of the transmitted symbols, the output of the special symbol sign of which is connected to the input character type symbol of the coding block 8b / 10b, the output of the encoded data of which is connected to the same input of the bit transfer unit, the output of the bit signals of which is the same output as the communication interface of the device, the local synchronization output of the bit transmission unit is connected to the same inputs of the coding block 8b / 10b, the converter symbols, symbol buffer 8b, a converter of received symbols, a control unit, a data receiving unit and a data output unit, the input of the control code recording of which is explicit is the input of the device system interface of the same name, the output of which is ready to issue a control code of the same name as the output of the data output unit, the input of the control code for which is the input of the same name as the system interface of the device, the output of the received control code of which is the output of the data reception unit of the same name, the readiness output of the received control code which is the output of the same system interface of the device, the input for reading the control code of which is the same name the input input of the data receiving unit, the information input and the symbol type input of which are connected respectively to the inputs of the received symbol converter respectively, the information input and the input of the special character flag of which are connected respectively to the outputs of the character buffer 8b, the recording permission input is connected to the output of the decoding unit 8b / 10b of the same name , the output of the symbol 8b of which is connected to the information inputs of the buffer of symbols 8b and the connection check block, the input of the special character attribute of which is connected with the same name the character buffer 8b and with the same output of the decoding unit 8b / 10b, the coding error output of which is connected to the input of the control unit of the same name, the connection establishment input of which is connected to the same output of the connection check unit, the connection sign of which is connected to the input of the received symbol converter and the output of the same block receiving bits, the synchronization output of the data reception of which is connected to the synchronization input of the reception of the character buffer 8b, with the synchronization input of the check unit with connected to the synchronization input of the decoding unit 8b / 10b, the information input of which is connected to the output of the received encoded data of the bit receiving unit, the input of the bit signals of which is the input of the communication interface of the device of the same name, and a control code issuing register is entered into the data issuing unit, control output is ready the code of which is the output of the data output unit of the same name, the input of the record of which is the input of the register of the output of the control code, the input of the control code for If it is the input of the data output unit of the same name, the reset and synchronization inputs of which are connected respectively to the reset and synchronization inputs of the control code issuing register, the control code readiness output of which is connected to the input of the character issuing arbitration unit of the same name, the control code reading output of which is connected to the register input of the same name issuing control codes, the output of the control code of which is connected to the second information input of the data multiplexer; a control code receiving register is entered into the data receiving unit, the information input of which is the input of the data receiving unit of the same name, the reset and local synchronization inputs of which are connected respectively to the reset and local synchronization inputs of the control code receiving register, the readiness outputs of the received control code and the received control code of which are respectively, by the outputs of the same name of the data receiving unit, the input of reading the control code of which is the input of the same name of the reception register of the control present code, and inputs the write enable synchronization of which are connected respectively to the input synchronization data reception unit and access selection control code decoder transformed code. 2. The device according to claim 1, characterized in that the transmitted character converter contains an output data register, a first character type register, a control code selector, a control code trigger, a first ROM constant, an output multiplexer, a first counter, a first AND element, a second AND element , the third element And, the output of the readiness for the issuance of a symbol of which is the output of the transmitter of the transmitted symbols of the same name, the data input of which is the input of the output data register, the output of which is connected to the first information the input of the output multiplexer, the data output of symbol 8b of which is the output of the transmitter of the transmitted symbols of the same name, the local synchronization input of which is connected to the synchronization inputs of the first register of the symbol type, the first trigger of the control code, with the counting input of the first counter and with the synchronization input of the input data register, the converter reset input connected to the reset inputs of the output data register, the first symbol type register, the first trigger of the control code and the first counter, the transfer output which is connected to the second input of the first ROM of constants, with the second inverse input of the second element And, with the second input of the first element And, the inhibit output of which is connected to the inverse input of the reset of the first counter, the input of the symbol type of the transmitter of the transmitted characters is the data input of the first register of the character type, output the first register of the symbol type is connected to the first input of the first ROM of constants and to the input of the selector of the control code, the output of the selection of the control code of which is connected to the first input of the third element And, the output the flag setting of which is connected to the data input of the trigger of the control code, the direct output of which is connected to the first input of the first element And, with the first inverse input of the second element And, with the third input of the first ROM constants, the output of the special symbol code of which is connected to the second information input of the output multiplexer, the output the sign of the special symbol of the first ROM of constants is the output of the transmitter of the transmitted symbols of the same name and is connected to the control input of the output multiplexer, the inverse trigger output is connected to the second input of the third element I. 3. The device according to claim 1, characterized in that the converter of received symbols contains a second ROM of constants, a second symbol type register, a second control code trigger, an input multiplexer, an input symbol type register, an input data register, the output of which type of received symbol is the same output a converter of received symbols, the information input of which is connected to the input data of the input data register and to the first input of the second ROM constant, the second input of the second ROM constant is the input of the special character a converter of received symbols allowing input of the ROM is an input of a sign of connection of a converter of received symbols, the output of the symbol type of the second ROM constants is connected to the data input of the second register of the symbol type and the first information input of the input multiplexer, the output of the selection of the control code of the second ROM constants is connected to the data input of the second the trigger of the control code and with the input of the reset register of the input symbol type, the data input of which is connected to the output of the input multiplexer, the second information the input of which is connected to the output of the delayed symbol type of the second symbol type register, the synchronization input of which is the local synchronization input of the received symbol converter and connected to the synchronization inputs of the second trigger of the control code, the input symbol type register and the input data register, the output of which is the information output of the received characters.

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