LU102832B1 - ROW CONNECTIONS OF AN ACTIVE MATRIX DISPLAY - Google Patents

Abstract

The invention relates, inter alia, to a drive circuit for an active matrix display, comprising: a plurality of columns (C1, C2, C3, C4), each of which can be connected to a data terminal of a pixel circuit; and a plurality of rows (Z1, Z2, Z3, Z4), each having one end connected to a source terminal of a (demux) transistor; According to the invention, at least two drain connections of (Demux) transistors of different rows are short-circuited with one another and led to the outside as a common row connection (R1, R2, R3, R4) of the respective rows.

Description

to UNIVERSITAT DES SAARLANDES 1 P57235/LU ACTIVE MATRIX DISPLAY WITH COMBINED LINE CONNECTIONS LU102832 The invention relates to an active matrix display and a method for controlling it.

TECHNICAL BACKGROUND AND PRIOR ART Active matrix displays for mobile phones are typically implemented in the form of a shift register circuit on the display glass using TFT technology. The edge of the display is narrow in this case. The number of connections required is negligibly small.

On larger displays, such as television displays, the row connections are brought out directly so that they can be connected to one or more row drivers.

With increasing display resolutions, the speed of the line control must increase. However, when using TFT technology with only one type of transistor, such as NMOS or PMOS, the power consumption of the known active matrix displays increases considerably. In addition, the quality of the control signals (eye diagram) deteriorates. If CMOS TFT technology is used, power consumption is lower, but not negligible. First of all, the cost is higher due to CMOS.

The power consumption increases again when the display is driven over time, e.g. with Pulse Width Modulation (PWM). A specific example is the digital control of AMOLED displays, which requires a 20-fold increase in line control speed.

OBJECT OF THE INVENTION | The object of the invention is therefore to provide an improved active matrix display and a method for controlling it, which can be implemented using a simple TFT process, particularly for large displays with high resolution, requires only narrow display edges and comparatively fewer electricity consumed.

BRIEF SUMMARY OF THE INVENTION This object is achieved by an active matrix display according to patent claim 1, an active matrix display according to patent claim 8, a method for driving an active matrix 1

DI en UNIVERSITY OF SAARLANDES P57235/LU Display according to claim 9 and a driver chip according to claim 15. Advantageous embodiments of the invention are the subject matter of the dependent claims.

LU102832 : According to a first aspect, the invention includes a driving circuit for an active matrix display, comprising a plurality of columns, each of which can be connected to a data terminal of a pixel circuit; and a plurality of rows each having one end connected to a source terminal of a (demux) transistor; characterized in that at least two drain connections of (Demux) transistors of different rows are short-circuited with one another and are designed as a common row connection of the respective rows to the outside.

A gate of a (demux) transistor can be connected to a control line.

The other end of the rows can each be connected to a source connection of a further (demux) transistor.

The drains of several other (demux) transistors can be shorted together and connected to a LOW voltage.

The gates of several other demux transistors can be shorted together and controlled by another signal.

A ratio of a number of row terminals and a number of rows can be 1:2 0-1:4.

The drains of all MP transistors can be connected to a fixed potential.

The transistors can be TFT transistors.

The active matrix display can be an AM-LCD, an AM-OLED or an AM-MicroLED display.

According to a second aspect, the invention includes an active matrix display, comprising a drive circuit according to one of the above aspects.

The (demux) transistors can be implemented on a glass of the active matrix display.

The lines can be connected to one or both edges of the display.

The Demux transistors can be placed at the edges of the display.

The LOW voltage can be provided by a driver chip.

The drive signals for the demux transistors can be connected to the top of the driver chip.

The | Drive signals may be generated by circuitry such as shift register circuitry on the driver chip.

The driver chip can be placed on the column side.

The driver chip can be manufactured using CMOS technology, in particular from monocrystalline silicon. | . According to a third aspect, the invention includes a method for driving an active matrix display, comprising the steps of driving a row connection with an address signal, the row connection being a common row connection of a plurality of rows of the active matrix display; 2 ——"—"—"""""""

a UNIVERSITAT DES SAARLANDES P57235/LU sistors at least one of the multiple rows of the active matrix display addressed via the common row connection in order to switch them to active, characterized in that | y102832 all rows that are not activated have a LOW potential at the common row connection during this time. The LOW potential can be provided statically, in particular by applying a corresponding voltage to the rows that are not actively switched. Alternatively, the LOW potential can be provided dynamically, in particular using a storage effect of input capacitances of pixel circuits of the rows. The LOW potential can be provided by the address signal being inverted for a predetermined time interval at the end of the addressing time of a row, in particular in order to discharge the input capacitances of the pixel circuits. At the beginning of the addressing time, an overvoltage higher than the HIGH signal can be applied to the row terminal to reduce a rise time of the row potential. Furthermore, at the end of the addressing time, an undervoltage lower than the LOW signal can be applied to the row terminal in order to reduce a fall time of the row potential. The - row potential can be refreshed when activated again by short-circuiting the row with LOW. According to a fourth aspect, the invention further includes a driver chip for an active matrix display, which implements a method according to the third aspect of the invention. The driver chip can be implemented using CMOS technology, in particular from monocrystalline silicon. It can be set up to also drive the columns of the active matrix display. The driver chip can drive signals from the pixel circuit, in particular for the rows; generate connections, in particular by means of a shift register circuit. In addition to the reduction in the number of row connections, the above-mentioned aspects enable lower power consumption, a more favorable voltage waveform in a row and a narrower display edge.

BRIEF DESCRIPTION OF THE FIGURES FIG. 1 shows a demultiplexing circuit Demux for rows of an active matrix display according to a first embodiment of the invention. ; 2 shows an extended demultiplexer circuit. Figure 3 shows an example of a port to row ratio of 1:4. 3 dd a UNIVERSITY OF SAARLAND P57235/LU FIG. 4 shows a more advantageous and symmetrical arrangement according to a further embodiment of the invention. ; Figure 5 shows a diagram of the drive signals for the circuit in Figure 1. Figure 6 shows a diagram of the drive signals for the circuit in Figure 1 when an overvoltage is applied to the row terminal according to another embodiment of the invention.

EXEMPLARY EMBODIMENTS FIG. 1 shows a demultiplexer circuit Demux for the rows according to a first embodiment of the invention. All transistors are TFT in this version and are implemented on the display glass. A demux ratio of 1:2 is shown here for simplicity. A higher ratio is equally possible, as will be shown. Row 1 line Z1 is connected to transistor MA1, as is row 2 Z2 to MA2, row 3 Z3 to MA3 and row 4 Z4 to MA4. The gate of the addressing transistor of a pixel circuit is connected to a row, while the data terminal of a pixel circuit is connected to a column C1, C2, C3, C4, etc. The display can be AM-LCD or AMOLED. One end of a row line is connected to the source of a demux transistor such as MA1, MA2, MA3, MA4, etc., respectively. For a 1:2 demux implementation, the gates of odd demux transistors MA1, MA3 etc. are connected to control line DA1 and the gates of even demux transistors MA2, MA4 etc. are connected to control line DA2. The drains of the demux transistors are short-circuited in pairs and run to the outside as row connections R1, R2, etc. This halves the number of line connections in a display. With a higher demux ratio, the number of row ports is reduced accordingly. The classic single-line addressing method (general demultiplexing method) can be implemented with this circuit. Since addressing is a binary process, the control signals only have two states, namely LOW or HIGH. The data signals for the Dis- ; 4 | |

N UNIVERSITY OF SAARLAND P57235/LU ; play, which are created via the columns, are usually analog. In this invention it is about the row terminals, so only the terminals Rı, R2, DA1 and DA2 are of interest LU102832. The LOW and HIGH potentials for the row connections Rı and R2 and for the control signals from demux transistors DA1, DA2 have physically different heights (levels) and are named as follows: RH = HIGH for Rı or R2 RL = LOW for R1 or R2 DAH = HIGH for DA1 or DA2 DAL = LOW for DA1 or DA2 Examples of this are given below. If the driver chip applies a high signal RH, e.g. 8V to the Rı connection and at the same time an even higher signal called DAH, e.g. 16V, is applied to DA1, it is ensured that MA1 is switched through. All gates of the pixel circuits on row 1 receive the RH potential from R1. R2 and DA2 each receive a LOW signal RL, RAL from the driver chip. This turns MA2 and MA4 off. MA3 is on, so Z3 gets the RL potential from R2. In this embodiment, NMOS-TFT is used. A version with PMOS-TFT works in the same way, only with inverse polarity of the control voltages. In this example it is also considered that the pixel circuits are addressed with positive row voltage. Reverse polarity pixel circuits can be addressed using the same principle, applying a LOW to the gate of the pixel circuit. A pixel circuit must be placed in a passive state, e.g. by a low on gate, if it is not addressed. In this way, line 1 is now addressed. The data or the voltages on the columns C1, C2 etc. are read in by the respective pixel circuits Pixels. When DA1 is switched to LOW DAL and DA2 is switched to HIGH DAH, row 2 is addressed since R1 is at RH. In the next step, Rı can be switched to RL and R2 to RH, line 4 wire addressed since DA2 is on DAH. In the next but one step, DA2 can be switched to DAL and DA1 to DAH, so that row 3 is addressed.

| | dd

Co UNIVERSITAT DES SAARLANDES P57235/LU According to the invention, the addressing sequence can also be different.

If DA1 is switched to DAH and DA2 to DAL and at the same time R1 is switched to RL and R2 to RH, row 3 is addressed_U102832.

Then DA1 is switched to DAL and DA2 to DAH so that line 4 is addressed.

Any sequence of addressing is possible.

The sequence line 1, 2, 4, 3, 5, 6, 8 etc. has the advantage over the sequence 1, 2, 3, 4, 5, 6, 7, 8 that the signals at R1, R2, R3, R4 etc. need to be switched less often.

The addressing sequence can be freely selected depending on the impact on visual quality, power consumption, control schemes, etc.

Figure 2 shows an expanded demux circuit.

To ensure that the addressing for the display works completely, another demux transistor such as MP1, MP2, etc. is added to the other end of a row line.

The drains of MP1, MP2, MP3, MP4 etc. are shorted together and connected to a LOW voltage VP that can be provided by the driver chip.

Odd demux transistors MP1, MP3 etc. have their gates shorted together and are controlled by signal DP1.

The gates of the even demux transistors are also shorted together and are controlled by signal DP2.

The task of the transistors MP1, MP2, MP3, MP4 etc. is that the potential of all non-addressed row lines is set to LOW.

This ensures that the data signals applied to C1, C2 etc. are only received by the pixel circuits on the row addressed.

The left side of the circuit in Figure 2 ensures that only one row is addressed, i.e. that only one row of e.g.

Z1 is HIGH.

It is realized as described above that one of the row connections e.g.

R1 gets a HIGH signal from the driver chip, while all other - terminals R2 etc. get a LOW signal from the driver chip.

A demux transistor e.g.

MA1 is turned on when the driver chip applies a HIGH signal to DA1.

At the same time, a LOW signal is applied to DA2, so that line 2 Z2 is not connected to the HIGH signal of Rı.

The DA1 and DA2 signals are alternating, ie.

HIGH/LOW or LOW/HIGH.

When DA1 is HIGH, all odd DA transistors are on.

Since only one row terminal is HIGH while all other row terminals are LOW, only one odd row is HIGH while all other odd rows are LOW.

Since DA2 is LOW at the same time, all DA transistors on the even rows are off and 6

Lo UNIVERSITAT DES SAARLANDES P57235/LU separated from the line connections.

In order to set the potential of the even rows to LOW so that these rows remain passive while an odd row is addressed, | |;100832 DP2 a HIGH signal from the driver chip.

As a result, all even transistors on the right side MP2, MP4 are switched on, so that all even rows are connected to the supply VP, which has a LOW potential as described above.

DP1 must be LOW when DA1 is HIGH.

As a result, there can be no short circuit between R1 HIGH and VP LOW.

That is, DA1 and DP1 are alternating, as are DA2 and DP2. The odd and non-addressed ones are turned on as described above by the odd demux transistors on the left and also to LOW by the LOW potential of the non-addressed row connections.

Consequently, all rows have a defined state, namely | a line e.g.

Z1 is HIGH and all other rows are LOW.

If an even line is addressed e.g.

Z2 is to be, then DA2 and DP1 are switched to HIGH and DA1 and DP2 to LOW.

The row connection for the row to be addressed is HIGH and all other row connections are LOW.

The right row terminals are always connected to the LOW potential.

An example of the control potential is listed below.

Assume that a pixel circuit is activated at 8V gate input and can be programmed by a column signal.

With -3V gate input the pixel circuit is not programmable.

The same applies to the TFT transistors.

At Vgs = 8V, the transistor is on and at Vgs = -3V, the transistor is off.

The potentials for the control for this example are then: Signals Potential V DAH 16 : DAL -6 DPH 5 DPL -6 RH 8 RL -3 VP -3 The structure of a Demux circuit can also be brought to a more general form, e.g. if the demux ratio is higher than 1:2.

Figure 3 shows an example for 1:4.

The ratio is arbitrary.

Each row is now connected to the source of two transistors MA and MP.

The drains of several MA Trans- 7 —_

a UNIVERSITY OF SAARLAND P57235/LU gates are short-circuited with one another and connected to a row connection. A row connection can receive a HIGH or a LOW signal from the driver chip. The drains of all LU102832 MP transistors are connected to a fixed potential VP. The drains of multiple MA transistors are shorted together. Each of these MA transistors has its own control signal at the gate, e.g. DA1, DA2 etc. This enables demux operation. The signal at a row terminal can be connected to a specific row, e.g. Z1, if the gate of the MA transistor on that row is driven HIGH while all other gates are driven LOW. This drastically reduces the number of row lines routed to the outside, while any row can be uniquely and exclusively addressed. As an example, the control signals for rows 1 - 8 Zı - Z8 from Figure 3 are given in the following table (H = HIGH; L = LOW):

TEA AEE |

A TE PIES

PPT TE A A A Bl IE I IE Ere

PEUT IE ET PE TETE TRI" IP TE IE The driving principle is such that one of the DA transistors Demux for addressing is HIGH H, while all other DA transistors are switched off, i.e. are LOW. A row connection R1 or R2 or etc. is HIGH which contains the row to be addressed while all other row terminals are LOW The combination of DA transistor switched HIGH and the row terminal connected HIGH clearly gives the addressed row 8

LA a UNIVERSITY OF SAARLAND P57235/LU ; The row to be addressed consequently determines the DA signals and the signals for the row connections as described above, as well as the DP signals.

The DP signal for the | to be addressed |) 492832 line is LOW.

The other DP signals Demux Passive are HIGH.

This means that the DA signal and the DP signal of a line are always alternating.

This means that the potential of each row is always defined, since a transistor is always switched on.

Table 1 gives an example of the levels of the potentials for HIGH and LOW for DA and DP control and the line connections. | The single addressing scheme, in which all passive lines are usually open and do not have to have a defined potential, can be implemented using the invention in such a way that at the point in time at which a row has a defined HIGH potential and is thus addressed, all other rows have a defined LOW potential and are passive, which ensures reliable passivation of the pixel circuits and prevents crosstalk from the addressed row to the passive rows.

This circuit enables a reduction in row connections.

With a number of rows of n and a demux ratio of 1:m, the number of row connections is n/m.

At the same time, 2m connections for controlling MA transistors and MP | transistors required.

With m= root n/2 the minimum of 2*root 2*n results for the connections.

In addition, a line for VP is required.

A numerical example would be: number of rows = 800, Demux ratio = 20, number of row connections = 40, total number = 80. This means that the number of leads is reduced by a factor.

If the above mathematical operations do not return integer results, the result can be rounded up.

A row connector can contain no more than m lines, but can contain fewer than m lines.

Also, the demux ratio need not be root n/2.

A different number will also greatly reduce the total number of leads.

The driver chip is usually placed on a column side, e.g. at the top.

This means that the lines must be connected to the top of one or both edges of the display.

The Demux transistors can also be placed only on the edges of the display.

The control signals for the demux transistors DA and DP are also connected to the top of the driver chip.

The space required for the demux transistors and the associated control lines and row connections determines the width of the display edge (bezel). It should be as narrow as possible or below a certain limit. 9 I. dd

© SAARLAND UNIVERSITY | P57235/LU It is therefore important that the connections required are drastically reduced. This affects LU102832 above all the number of row connections, while the control signals for DA and DP transistors can be above the TFT transistors DA and DP depending on the TFT process. Of course, the demux ratio should not be so high that the demux transistors and the required control signals take up a large amount of space. It is crucial that the total width for row connections and demux transistors is minimal or lies below certain limits. ; This results in the possibility that these connections are routed to a driver chip on the outer edge of the display, which can also drive or control the columns. The width of these connectors is small, so the bezel of the display can be narrow. The number of pads on the driver chip for connecting the rows is correspondingly small. Another big advantage is that the control signals from the circuit such as | be generated by a shift register circuit on the driver chip. A driver chip is usually CMOS and of course made of single crystal silicon. The power loss for this is negligible. In contrast to this, a shift register circuit made from a TFT transistor type NMOS or PMOS causes high power loss, which is disadvantageous for mobile applications in particular. Even a TFT-CMOS shift register requires a non-negligible performance with a higher number of lines or a higher frame rate. Here you can see the advantage of realizing the row driver function of an IC, but not a TFT circuit. Therefore, a suitable row termination method is important. The following structure results from the above numerical example and according to the arrangement in FIG. On the left are 20 DA signals and 40 row connections. On the right side there are 20 DP signals and one VP line. This asymmetry is unfavorable. The left side should be significantly wider than the right side. FIG. 4 shows a more advantageous and symmetrical arrangement according to a further embodiment of the invention. In the upper half of the display, the DA lines and row connections are on the left and the DP lines and the VP line are on the right. In the lower half, the DP lines and the VP line are on the left and the DA lines and the row connectors are on the right. Of course, the left/right division can be designed in more than two blocks. In such an embodiment, the multiplexing ratio m can be chosen differently than in the asymmetric embodiment of Figure 3, since 2*m drive signals must be supplied on each side and may require a different width.

THERE

N UNIVERSITA DES SAARLANDES P57235/LU It is advantageous that the line addressing time remains unchanged through demux operation.

It LU102832 equals the frame period divided by the number of lines as in non-demux operation and is referred to as TROW in this description.

A limiting factor for achieving a high number of lines or a high frame rate is the charging or discharging of the input capacitances of all pixel circuits on a line.

The power is supplied by the driver chip, which is not critical.

However, it must be replaced by a TFT transistor such as MA or

MP transistor flow.

Since a TFT has low mobility, this transistor has to be large.

However, the problem is identical to that of the prior art with a TFT shift register, in which the current must also flow through at least one TFT transistor. | The number of lines can be further reduced with an additional or even several demux stages.

This affects both the DA and DP lines and the line connections.

However, the effect is weaker because the m number of Demux ratio and the number of row connections is much smaller than the number of rows n.

At row connections, the addition of more stages is somewhat more critical since the demux transistors must charge the input capacitances of all pixel circuits on a row, so the demux transistors must be oversized so that the series resistance of the demux transistors is not too large is advised and it does not take too long to charge the input capacitance.

Overall, it's a trade-off between the width of the display bezel, performance speed and eye diagram, and the number of ports.

Another approach to realizing Demux operation is based on dynamic storage.

The starting point is FIG. 1. The problem here is that the potential of a row is not defined after addressing, since the row line is not connected to any potential and is therefore in the Z state.

The potential of this row was HIGH during the addressing, so that there is a risk that the potential will remain HIGH.

However, for the addressing to function correctly, the line must have the LOW potential.

The second method in this invention is based on the storage effect of the input capacitances of the pixel circuits.

FIG. 5 shows a diagram of the drive signals for the circuit according to FIG. 1. In the first addressing period time between 0 and TROW, DA1 is HIGH H, where TROW is the row addressing time.

DA2 is LOW alternating.

In this period, R2 is LOW L.

Rı is HIGH H first, just before reaching TROW -TDIS, Rı goes to a low level L 11 -

Cl UNIVERSITAT DES SAARLANDES P57235/LU switched. DA1, DA2, R1 and R2 are generated by the driver chip. Z1, Z2, Z3 and Z4 are the circuit's response to these external signals. | LU102832 Zı increases from time 0. The limited slew rate is due to the input capacitances of the pixel circuits and resistances of the demux transistor and the supply line as well as the internal resistance of the driver chip. The increase is shown linearly for the sake of simplicity. It is important that the voltage at least substantially reaches the HIGH level, e.g. 8V, so that the pixel circuits on row 1 are activated. During the time that Z1 is HIGH, the data signals on C1, C2, C3, C4 can be read from the pixel circuits on row 1. The other rows Z2, Z3 and Z4 have LOW levels in this period, so that the pixel circuits on these rows are passive and are not affected by the applied column signals. While the potential of Z2 and Z4 is stored capacitively, the potential of Z3 is updated or refreshed to LOW by the switched-on MA3. This applies to all odd lines except for the addressed line Z1. Ri is switched to L in the time between TROW-TDIS and TROW. The potential Z1 drops accordingly. At the time of TROW, the potential should be at least substantially LOW, e.g. -3 V. This means that the pixel circuits on row 1 are already deactivated at this point in time. In the second addressing period between TROW and 2*TROW, DA1 is LOW, but DA2 is HIGH. Re remains LOW. R1 has the same shape as in the time between o and TROW. Z2 reacts like Z1 in the first addressing period. Z4 and all other even rows except row 2 are refreshed to LOW. In the third and fourth addressing periods, DA1 and DA2 are again HIGH/LOW and LOW/HIGH. Row 1 and row 2 are updated respectively.

The passive rows are updated or refreshed after m Demux ratio addressing periods m*TROW. This is a relatively short time. Consequently, the risk of an unintentional activation of a passive line can be assessed as low. This implements demux operation with a simple circuit. The price for this is that the time in which the column signals are read in is reduced. It is less than the addressing time of a line TROW.

12 —_—————————

0 UNIVERSITÂT DES SAARLANDES P57235/LU The time in which Z1 is HIGH should be longer than the rise time and the fall time together. In the Zı HIGH time, the pixel circuits must receive the signals on the columns. Because these received signals are typically analog and need to be accurate, a longer time is required, which can be several times the RC time constant, while activating and deactivating the pixel circuits is a binary operation and does not require an accurate voltage. FIG. 6 shows that an overvoltage can also be applied to the row connection in order to reduce the rise time or the fall time. R1 gets an Hpre signal higher than H in the phase between time 0 and Tpre. This shortens the rise time of Z1. After Tpre, the Z1 potential falls or rises to H depending on the potential at time Tpre. In the phase between TROW-TDIS and TROW, R1 sinks to Ldis, which is lower than L. Consequently, the fall time is also reduced. Thus, there is more time in which the pixel circuits can read the column signals, i.e. be programmed. The control of the row connections is somewhat more complex. a After addressing the first row, the Z1 potential can be slightly lower or slightly higher than L. In the further course, the potential remains stored capacitively and can drift somewhat depending on: the leakage current of the demux transistor. When DA1 is HIGH again, in this case in the third line, Z1 is short-circuited with LOW and is thus updated or refreshed. The signals for Z2, Z3 and Z4 follow the same principle. The line connectors and the demux transistors can be split on both sides of the display - so that the two bezel edges become narrower and symmetrical. With increasing display resolutions, the addressing time TROW can become too short. First, TROW itself becomes smaller because the number of rows n is higher. In addition, the charging and discharging of the input capacitances of the pixel circuits take longer. This time increases disproportionately with the number of columns, e.g. quadratically. The result is that the time for programming the pixels, i.e. reading in the column signals, is too short. A proven method is to connect the lines on two sides. This means that two MA transistors or two MA and two MP transistors are connected at the two ends of a row. This halves the effective number of columns, so that the time for charging and discharging is reduced, e.g. halved. The price for this is that the number of connections is doubled. 13

TUE

© UNIVERSITAT DES SAARLANDES P57235/LU Another positive effect of the two methods is that the voltage history waveform of a line is better compared to a TFT shift register, since the waveform of a TFT shift register at high frequency LU102832 differs significantly from the ideal shape is removed. Compared to a TFT shift register, an IC can generate a much higher frequency | and requires a much lower power loss. In this way, a higher demux ratio can be realized for the columns. At the same time, the number of connections on the driver chip for the columns is reduced.

14 ; EEE)

Claims (15)

Fer UNIVERSITY OF SAARLAND P57235/LU es LU102832 PATENT CLAIMS 1. Driving circuit for an active matrix display, comprising: - a plurality of columns (C1, C2, C3, C4), each of which can be connected to a data terminal of a pixel circuit; and - a multiplicity of rows (Z1, Z2, Z3, Z4), one end of each of which is connected to a source connection of a (demux) transistor; characterized in that at least two drain connections of (Demux) transistors of different rows are short-circuited with one another and run upwards as a common row connection (Ru, R2, R3, R4) of the respective rows. 2. Control circuit according to claim 1, wherein a gate of a (demux) transistor is connected to a control line (DA1, DA2, DA3, DA4). 3. Drive circuit according to claim 1, wherein the other end of the rows (Z1, Z2, 73, Z4) is connected to a source connection of a further (demux) transistor (MP1, MP2, MP3, MP4). 4. Control circuit according to claim 1, wherein the drain connections of several further (Demux) transistors (MP1, MP2, MP3, MP4) are short-circuited together and connected to a passive voltage (VP). 5. Control circuit according to claim 1, wherein the gates of a plurality of further demux transistors (MP1, MP3 etc.) are short-circuited with one another and controlled by a further signal. 6. Control circuit according to one of the preceding claims, wherein the drains of all MP transistors are connected to a fixed potential (VP). 7. Control circuit according to one of the preceding claims, wherein the transistors are TFT transistors. : dd To SAARLAND UNIVERSITY | P57235/LU ; | 8. Active matrix display, in particular an AM-LCD, AM-OLED or an AM-LU102832 MicroLED display, comprising a drive circuit according to one of claims 1 to 7. 9. A method for driving an active matrix display, comprising the steps: - driving a row connection (R1, R2) with an address signal, the row connection being a common row connection of a plurality of rows of the active matrix display; and driving a gate connection of a (demux) transistor of at least one of the multiple rows of the active matrix display addressed via the common row connection in order to switch them to active, characterized in that | all non-actively switched rows at the common row connection (R1, R2) meanwhile have a LOW potential (static or dynamic). 10. The method according to claim 9, wherein the LOW potential is provided statically, in particular by applying a corresponding voltage (Vpassive) by means of transistors to the non-actively switched rows. 11. The method according to claim 9, wherein the LOW potential is maintained dynamically, in particular using a storage effect of input capacitances of pixel circuits of the rows. 12. The method according to claim 9 or 11, wherein the LOW potential thereby ready; the address signal is inverted for a predetermined time interval (Tdis) at the end of the addressing time (TROW) of a row, in particular in order to discharge the input capacitances of the pixel circuits. 13. The method according to any one of claims 9 to 12, wherein at the beginning of the addressing time, an overvoltage (Hpre) is applied to the row connection (RI, R2), which is higher than the HIGH signal in order to increase the time of the row potential (Z1, Z2) to reduce. 16 ———————————— eu UNIVERSITY OF SAARLAND | P57235/LU 14. The method as claimed in claim 12, wherein at the end of the addressing time an undervoltage (Ldis) which is lower than the | Uy102832 LOW signal is to reduce a fall time of the row potential (Z1, Z2). 15. Driver chip for an active matrix display, which implements a method according to claims 9 to 14. 17 . LLC