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KR980006321A - Capacitor Formation Method for DRAM Device - Google Patents

Capacitor Formation Method for DRAM Device Download PDF

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Publication number
KR980006321A
KR980006321A KR1019960022877A KR19960022877A KR980006321A KR 980006321 A KR980006321 A KR 980006321A KR 1019960022877 A KR1019960022877 A KR 1019960022877A KR 19960022877 A KR19960022877 A KR 19960022877A KR 980006321 A KR980006321 A KR 980006321A
Authority
KR
South Korea
Prior art keywords
photoresist pattern
film
forming
charge storage
storage electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019960022877A
Other languages
Korean (ko)
Inventor
이진순
장명식
양예석
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960022877A priority Critical patent/KR980006321A/en
Publication of KR980006321A publication Critical patent/KR980006321A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/043—Manufacture or treatment of capacitors having no potential barriers using patterning processes to form electrode extensions, e.g. etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명의 저장 용량이 개선된 디램의 캐패시터 형성방법이 개시된다. 개시된 본 발명은 트랜지스터와 트랜지스터 상부에 절연막이 형성되고, 트랜지스터의 접합 영역중 어느 하나가 노출되도록 절연막을 식각하여 콘택홀이 형성된 반도체 기판을 제공하는 단계; 반도체 기판 전면에 후막의 전하 저장 전극용 폴리실리콘막을 증착하는 단계; 전하 저장 전극용 폴리실리콘막 상부에 일정 거리 만큼 간격을 갖고, 반구의 형태로 배열된 포토레지스트 패턴을 형성하는 단계; 포토레지스트 패턴에 의하여 전하 저장 전극용 폴리실리콘막을 일정 깊이만큼 식각하는 단계; 포토레지스트 패턴을 제거하는 단계를 포함하여, 원통의 표면적만큼 디램의 용량을 증대시킬 수 있다.Disclosed is a method of forming a capacitor of a DRAM having an improved storage capacity of the present invention. The present invention provides a semiconductor substrate having a contact hole formed by forming an insulating film on a transistor and an upper portion of the transistor, and etching the insulating film so that any one of the junction regions of the transistor is exposed; Depositing a polysilicon film for a charge storage electrode of a thick film on the entire surface of the semiconductor substrate; Forming a photoresist pattern spaced by a predetermined distance on the polysilicon film for the charge storage electrode and arranged in a hemispherical shape; Etching the polysilicon layer for the charge storage electrode by a photoresist pattern to a predetermined depth; Including the step of removing the photoresist pattern, it is possible to increase the capacity of the DRAM by the surface area of the cylinder.

Description

디램 소자의 캐패시터 형성방법Capacitor Formation Method for DRAM Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a 내지 제2c는 본 발명의 디램 소자의 캐패시터 중 전하 저장 전극의 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming a charge storage electrode in a capacitor of a DRAM device of the present invention.

Claims (5)

트랜지스터와 트랜지스터 상부에 절연막을 형성하고 트랜지스터의 접합영역중 어느 하나가 노출되도록 절연막을 식각하여 콘택홀이 형성된 반도체 기판을 제공하는 단계; 상기 반도체 기판 전면에 후막의 전하 저장 전극용 폴리실리콘막을 증착하는 단계; 상기 전하 저장 전극용 폴리실리콘막 상부에 일정 거리 만큼 간격을 갖고, 반구의 형태로 배열된 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴에 의하여 전하저장 전극용 폴리실리콘막을 일정 깊이만큼 식각하는 단계; 상기 포토레지스트 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 디램 소자의 캐패시터 형성방법.Providing a semiconductor substrate having a contact hole formed by forming an insulating film over the transistor and etching the insulating film so that any one of the junction regions of the transistor is exposed; Depositing a polysilicon film for a charge storage electrode of a thick film on the entire surface of the semiconductor substrate; Forming a photoresist pattern spaced by a predetermined distance on the polysilicon film for the charge storage electrode and arranged in a hemispherical shape; Etching the polysilicon film for charge storage electrode by a predetermined depth by the photoresist pattern; And removing the photoresist pattern. 제1항에 있어서, 상기 반구 형태의 포토레지스트 패턴은 포토레지스트막의 노광시, 과도 노광하여 형성하는 것을 특징으로 하는 디램 소자의 캐패시터 형성방법.The method of claim 1, wherein the hemispherical photoresist pattern is formed by over-exposure upon exposure of the photoresist film. 제1항에 있어서, 상기 반구형태의 포토레지스트 패턴의 간격은 노광장비로 형성할 수 있는 최단거리인 것을 특징으로 하는 디램 소자의 캐패시터 형성방법.The method of claim 1, wherein the space between the hemispherical photoresist pattern is the shortest distance that can be formed by exposure equipment. 제1항에 있어서, 상기 폴리실리콘막은 반구 형태의 포토레지스트 패턴에 의하여, 과소 식각되는 것을 특징으로 하는 디램 소자의 캐패시터 형성방법.The method of claim 1, wherein the polysilicon layer is under-etched by a hemispherical photoresist pattern. 제1항에 있어서, 상기 포토레지스트패턴을 제거하는 단계 이휴 유전율이 높은막 및 플레이트 전극을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 디램 소자의 캐패시터 형성방법.2. The method of claim 1, further comprising forming a film and a plate electrode having a high dielectric constant in the step of removing the photoresist pattern. 3. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960022877A 1996-06-21 1996-06-21 Capacitor Formation Method for DRAM Device Withdrawn KR980006321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960022877A KR980006321A (en) 1996-06-21 1996-06-21 Capacitor Formation Method for DRAM Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960022877A KR980006321A (en) 1996-06-21 1996-06-21 Capacitor Formation Method for DRAM Device

Publications (1)

Publication Number Publication Date
KR980006321A true KR980006321A (en) 1998-03-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960022877A Withdrawn KR980006321A (en) 1996-06-21 1996-06-21 Capacitor Formation Method for DRAM Device

Country Status (1)

Country Link
KR (1) KR980006321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023037B2 (en) 2000-08-11 2006-04-04 Samsung Electronics Co., Ltd. Integrated circuit devices having dielectric regions protected with multi-layer insulation structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7023037B2 (en) 2000-08-11 2006-04-04 Samsung Electronics Co., Ltd. Integrated circuit devices having dielectric regions protected with multi-layer insulation structures

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19960621

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid