KR970005830B1 - Audio codec board - Google Patents

Abstract

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Description

Audio codec board

1 is an overall configuration diagram of an audio codec board of the present invention.

* Explanation of symbols for main parts of the drawings

1: DSP 2: reset circuit

3: clock generator 4: audio input / output circuit

5 PC and DSP connection part 6 Memory and decoding circuit part

The present invention relates to a 7KHz audio codec board for an ISDN PC performing a 7KHz audio codec function to provide a high quality voice service through ISDN.

Existing audio codec for ISDN PC coded voice signal within 300 ~ 3.4KHz with 64Kbps bit rate by Pulsc Code Modulation (PCM) method. Therefore, the signal is less than 300Hz and more than 3.4KHz, it is inferior in understanding or naturalness in terms of quality, and when all 64Hbps 1B channels are used for voice, a separate 1B channel must be used.

Disclosure of Invention The present invention devised to solve various problems of the prior art has an object of providing a 7KHz audio codec board for an ISDN PC for providing a high quality voice service through ISDN.

In order to achieve the above object, the present invention, a general-purpose DSP (Digital Signal Processor) connected to an external communication network connection unit and built-in A / D, D / A conversion circuit on a personal computer; Reset means connected to the DSP and having a separate reset switch to press the switch to discharge charges charged in the capacitor; Clock generation means connected to said DSP and generating a DSP core clock and a division of a sampling clock of a SIGMA-DELTA codec; PC and DSP connection means connected to the host terminal of the DSP to communicate with the DSP and to transmit data if the selection area of the selection switch and the program area match; An audio input / output means for making a voltage of VCC by division of resistance from resistance in the DSP and using it as a reference voltage of an input / output amplifier using a voltage follower, and responsible for sound input and output; It characterized by having a.

Briefly, the present invention increases the understanding, naturalness and speaker recognition by subband ADPCM (Adaptive Differential PCM) of speech signals from 50 to 7KHz, and enables the coding bit rate to be changed to 48K, 56K, 64Kbps. When data transmission is required, data and voice can be transmitted through the same channel.

In the present invention, an audio codec board is implemented on a IBM PC by using a general-purpose digital signal processor (DSP) chip in which A / D and D / A conversion circuits are embedded, so that the audio codec board can be flexibly used for various application services.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is an overall configuration diagram of an audio codec board according to the present invention, where 1 is a DSP, 2 is a reset circuit, 3 is a clock generator, 6 is a memory and decoding circuit, 5 is a PC and a DSP connection, and 4 is audio. I / O circuit sections are shown respectively.

Looking at the function of each component in detail as follows.

First, the reset circuit section 3 has a separate reset switch in the board. When the switch is pressed, the potential charged to the capacitor is discharged and immediately goes low. This signal is input to the trigger pin of the NE555 to provide an external resistor and chip capacitor. Keep the output high for a certain time constant. The reset signal of the DSP chip is used to invert it again. The reset DRV signal and the trigger input of the NE555 are wired-or ORed so that the DSP is reset even in a PC reset state.

The clock generator (2) oscillated 32MHz using an external crystal oscillator and connected to the EXTAL pin, and the 40MHz DSP core clock using the frequency division PLL of the 16KHz sampling clock of the SIGMA-DELTA codec. Occurs.

The memory and decoding circuit section 6 can have 64K regions independently of both P and X memories.

P memory decodes S0000-SFFFF area by 8K (S2000) by 74F138 by 'PS / DS' signal and 'RD' signal.In mode 0, P: SC000 If the program is downloaded from the area and in mode 1, a jumper is set to select the DSP core to read P: SC000 (-SCFFF) as 'low' and load it through the host. In addition, in other modes, jumpers are provided to randomly allocate the decoding region of the ROM.

The X memory was selected using 'PS / DS' only, and each S8000-SFFFF area was divided by 8K using the 74F139 decoder. The current circuit is designed to use only 8K-word RAM and has a jumper to allocate an arbitrary area of 8000-SFFFF, and the remaining SE000-SFFFF area is partially used as a peripheral memory map of the DSP.

Program memory should use ROM with fast access time (within 25nS) to eliminate delays in access.

The external memories and decoders do not need to be used as long as they have enough capacity as the DSP's internal memory.

Since the PC and DSP connection 5 can be used as the I / O address of the I / O channel, up to S100-S3FF, the area setting must be identical with the selection area of the selection switch and the program area using the comparator 74HCT688. Communication and data transfer with DSP are available.

I / O address decoding uses 8 addresses but there are 8 address areas for register control and data transfer of HI (HOST INTERFACE) inside DSP.

Address selection from A9 to A4 should be set with selection switch first and changed so that area matches in program.

When the input of the comparator is in the P = Q state, the output goes 'low' to gate the data bus buffer 74HCT245 and select the register of HI according to the state of A0-A2. Thereafter, according to the read / write (RD / WR) state, the DSP can control the 'HW / R' and 'HEN' signals to read or write. 74HCT245 is bidirectional, allowing direction to be controlled by 'IOR'.

In order to send a command from the PC to the DSP, there is an interrupt method using a host command vector and a polling method of manipulating a flag (HF0-3) of a register.

Data transmission / reception between the PC and the DSP uses the data transfer registers of RXH, RXL-HTX, TXH, and TXL-HRX to check the empty and full flags of the status register and then write the data. (write) or read.

The audio input / output circuit unit 4 creates the voltage of the VCC by the voltage divider by the resistor in the DSP and uses it as a reference voltage of the input / output amplifier using a voltage follower. At this time, it is required to remove the V _DIV terminal and the V _REF terminal with an appropriate capacitor to handle the noise. This reference voltage can also be used as a microphone power supply. The audio input has two terminals, a microphone and an AUX, but there is no difference between them.

In addition, in order to use a low voltage condenser microphone that does not use a local power supply, a reference voltage of 2V can be supplied. The audio output allows the loudspeaker to be directly connected between the differential output terminals SPKP and SPKM, which can be applied to a headset or handset. In the case of HANDS FREE, a separate amplifier circuit was used to increase the output, and the two output states were switched using jumpers. The encoder's output code is sent via the STD0 pin of SS10 inside the DSP without any circuitry, and the input code of the detoder is received from the SRD0 pin and processed. This operation is synchronously or asynchronously and internal clock or external clock selection, in the case of the internal clock, the clock frequency parameters, etc. can be flexibly enabled by the selection of the register.

The connection between the codec and the transmit / receive port separates only the audio data from the data received from the network connection and transmits it to the codec board at 48K BIT / S, 56K BIT / S or 64K BIT / S, or vice versa. Make connections with the site.

Therefore, the present invention as described above can provide a high-quality audio service through ISDN, such as 7KHz telephone, there is an effect that can be variously used in the audio processing unit of the video terminal, such as video telephony, video conferencing.

Claims (2)

A general-purpose digital signal processor (DSP) 1 connected to an external communication network connection unit and having built-in A / D and D / A conversion circuits on a personal computer; Reset means (3) connected to the DSP (1) and having a separate reset switch for pressing the switch to discharge the potential charged in the capacitor; Clock generation means (2) connected to said DSP (1) for generating a division of a sampling clock of a SIGMA-DELTA codec and a DSP core clock; A PC and DSP connection means (5) connected to the host terminal of the DSP (1) to communicate and transmit data with the DSP (1) when the selection area of the selection switch and the program area coincide; And an audio input / output means (4) for making a voltage of the VCC by the voltage divider by the resistance in the DSP (1) and using it as a reference voltage of the input / output amplifier using a voltage follower, and in charge of sound input and output. ; Audio codec board comprising a. Memory and decoding means (6) connected to said DSP (1) and implemented in ROM within 25 nS of fast access time to eliminate delays in access; The audio codec board further comprises.