KR970004818B1 - Staircase sidewall spacer for improved source/drain architecture - Google Patents

Abstract

No content.

Description

Semiconductor device manufacturing process

1 is a cross-sectional view showing the formation of a gate and the next oxide layer to form a prior art MOS device.

2 is a cross-sectional view showing the formation of n ⁻ / n ⁺ source and drain regions for the prior art device of FIG.

3 is a cross-sectional view showing prediction of source and drain region formation of the prior art device of FIG. 2 due to a change in sidewall oxide slope.

4 is a cross-sectional view of the present invention showing the formation of a gate on a silicon substrate over the gate and the substrate and the formation of the next oxide layer.

5 is a cross-sectional view of the formation of a nitride layer on the oxide layer of FIG.

FIG. 6 is a cross sectional view of the gate region of the device of the present invention with sidewall spacers remaining after etching the oxide and nitride layers of FIG.

7 is a cross-sectional view of the FIG. 6 device after remaining nitriding is removed on the sidewall spacers.

FIG. 8 is a cross-sectional view illustrating n ⁻ implantation to form n ⁻ source and drain regions for the FIG. 7 device.

FIG. 9 is a cross-sectional view showing n ⁺ implantation to form n ⁺ source and drain regions for the device of FIG.

FIG. 10 is a cross-sectional view showing the source and drain regions of the FIG. 9 device after annealing in which n ⁻ / n ⁺ regions are diffused in the substrate.

Fig. 11 is a cross sectional view showing the formation of sidewall spacers at each gate of the n ^- channel and p ^- channel regions of the CMOS device of the present invention.

FIG. 12 is a cross-sectional view showing n ⁻ implantation to form n ⁻ source and drain regions for the device of FIG.

FIG. 13 is a cross-sectional view showing n + implantation to form n + source and drain regions for the device of FIG.

FIG. 14 is a cross-sectional view showing p ⁻ implant to form p ⁻ source and drain regions for the device of FIG. 13.

FIG. 15 is a cross-sectional view showing p ⁺ implant for forming p ⁺ source and drain regions for the device of FIG.

FIG. 16 is a cross-sectional view showing the CMOS device of FIG. 15 after annealing.

FIG. 17 is a cross-sectional view showing another embodiment in which a raised polysilicon layer is formed on a substrate adjacent to a sidewall spacer of the present invention.

FIG. 18 is a cross sectional view showing the formation of n ⁻ / n ⁺ source and drain regions under the elevated polysilicon of FIG. 17 ^; FIG.

19 is a cross-sectional view showing another embodiment of the CMOS device in which n ⁻ / n ⁺ and p ⁻ / p ⁺ source and drain regions are formed under elevated polysilicon.

FIG. 20 is a cross sectional view showing another embodiment of the CMOS device with a raised polysilicon layer adjacent to the sidewall spacers and formed over the substrate and having a thickness to raise the polysilicon layer over the spacer foot to inject a narrow area in the substrate. .

FIG. 21 is a cross-sectional view of the elevated polysilicon device of FIG. 20 with the next salicide layer.

The present invention relates to a process for forming fields of MOS integrated circuits, in particular source and drain regions of CMOS integrated circuit devices.

Several processes in integrated circuit design are known for manufacturing actual devices. The technique includes several layers formed on a silicon substrate. Here, these layers involve one or more of several photolithography, patterning, etching, exposure, implantation steps, etc. to form the required device. One form of integrated circuit is a metal oxide semiconductor (MOS) field effect transistor (FET) in which the source and drain regions of a transistor are separated by a channel region under the transistor gate. Here, the transistor is formed on a substrate, and source and drain regions are formed in the substrate and gate regions remaining on the surface of the substrate.

Generally, the source and drain regions are formed by doping the substrate in the region where these regions are formed. Ion implantation is one technique for doping the source and drain. Using gate alignment, adjacent dielectric spacers and gates are used to align the substrate region where the doping occurs.

A well known practice is to provide a second injection for defining a second injection region and a first injection for defining a first injection region. The second injection region is the actual source or drain and the injection region is a graded doped or lightly doped region between the source or drain from the channel to provide improved device integrity, in particular a high breakdown drain voltage. to provide.

Although these techniques are well known, the various specific treatments can be used to produce devices of any size.

As a device geometry slink, an attempt is made to form more transistors on a given area of a semiconductor wafer.

For example, semiconductor devices fabricated using submicron technology include more circuit elements per unit area than devices fabricated using ab-micron technology. Therefore, for devices of a given size, such as devices manufactured using Dimension 1.5 Ota's above technology, which require device slinks and / or variously formed layers to become more critical as device sizes subsequent to the slinks. Suitable errors in forming the source and drain regions are not suitable for advanced devices, such as devices manufactured using 0.35, 0.5 or even 0.8 micron techniques.

GB-A-2214349 (examples of FIGS. 2A-2C and corresponding text) describes a process for fabricating semiconductor devices using el-type spacers adjacent to the gate of a CMOS device and also describes a lightly doped drain (LDD) structure. do.

The present invention is provided for an improved method of forming source and drain regions in a semiconductor device, with sharper limitations such as source-drain spacing and tighter control of the source and drain doping profiles. Is permitted for device manufacture, and an improved method is also provided to facilitate manufacturing in device manufacture.

Stepped gate sidewall spacers are described as dense dimension typos of spacers provided for source-drain spacing and for tight control of the source and drain doping profiles, particularly applied to double doped source and drain regions. The sidewall spacers are utilized to align regions of the substrate with respect to ion implantation of the source and drain regions.

The source and drain regions are either n ^- channel devices or p ^- channel devices. By combining the n ^- and p ^- channels, a CMOS device is manufactured.

After the gate is formed over the substrate, a conformal oxide layer and a conformal nitride layer are formed. The next anisotropic etch remains in the oxide spacer adjacent the gate sidewall due to the selective etching of the overlapped nitride layer.

After removal of the remaining nitride by either isotropic or anisotropic etching, stepped sidewall oxide spacers remain.

Next, n ⁻ (or p ⁻ ) implantation is performed following n ⁺ or (p ⁺ ) implantation to form a double doped source and drain region.

Since the first implant is formed at a higher energy level, ions penetrate through the lower portion of the stepped spacer. The second implant is at a lower energy level than the first so that ions do not penetrate the spacer quickly. Thus, after annealing, ionic damage is removed and implantation is also controlledly diffused into the substrate, with the isolation region of n ⁻ (or p ⁻ ) remaining between the n ⁺ or (p ⁺ ) region and the channel region. Moreover, because the footprint dimensions of the spacers are tightly controlled during their formation, sharp definitions of the source and drain region locations are achieved.

Moreover, considerable simplification of the process is achieved by the process structure of the present invention. In particular n ⁻ and n ⁺ (or p ⁻ and p ⁺ ) implantation are performed in one ion implantation machine operation. Thus, the number of process steps is reduced and allowance for cost and production risk reduction in manufacturing.

A semiconductor device manufacturing process using stepped spacers for improved formation of doped regions is described. The prior art is first described to provide a better understanding of the advantages induced by the practice of the present invention. In the description below, specific thicknesses, temperatures, etc. are described to provide an understanding of the invention. Therefore, it will be apparent to one skilled in the art that the present invention may be practiced without these specific techniques. In other instances, well known treatments have not been described in detail to observe the present invention.

Referring to FIG. 1, a semiconductor device 10 of the prior art is shown. The device 10 is a metal-oxide-semiconductor (MOS) device having a substrate 11, which is generally made of silicon.

The circuit elements formed on the substrate 11 are usually separated by pulsed oxidation regions, such as the field-oxidation region 12 of FIG. The gate 14 is thus formed on the substrate 11.

The gate 14 generally consists of a polysilicon region 15 separated from the substrate 11 by a dielectric region 16, which is made of an oxide such as silicon oxide (SiO 2).

Leveraging self-aligned technology, gate 14 is used to define the channel region within engine 11 under gate 14.

The source and drain regions are continuously defined as regions of the substrate that are connected with the channel regions, and consequently, the source and drain regions do not extend to the substrate 11 under the gate 14. Before forming the source and drain regions, an oxide layer 17 is deposited.

Using well known photoresist deposition, photolithography and etching techniques, oxide layer 17 is etched into the exposed portion of substrate 11 for the purpose of forming source and drain regions, as shown in FIG.

The etching process is generally anisotropic as part of the oxide layer 17 remains adjacent to the vertical side of the gate 14. At any moment, a portion of the oxide layer 17 is commonly referred to as a spacer, and the gate 14 is bounded by a spacer region 22, as shown in the cross-sectional view of FIG.

Next, masking techniques are used to expose only those areas that accept the implant. As shown in FIG. 2, n ⁻ region 23 is formed due to n implantation. Subsequently, a second masking step is utilized to define the area for forming n ⁺ implantation. The n ⁺ region 24 remains in the n ⁻ region 23, which boundary is particularly important in the region close to the channel region under the gate 14.

An annealing step is used to anneale the source and drain, the annealing step extending into the n ⁻ and n ⁺ regions towards the channel region, at which point the n ⁻ region extends into the channel region, and the gate (14) It does not extend somewhat to the underlying channel region. One technique for forming the n ⁻ and n ⁺ (double doped) source and drain regions is 1, based on substrate current analysis of IEEE Report ED-32, No. 2, pages 429-433, published in February 1985 by Masmoto et al. An optically escaped drain (LDD) structure is described and discussed in Optimal and Reliable LDD Structures for -μm NMOSFETs.

The spacer 22 cooperates with the gate 14 and functions to align the substrate 11 for the implantation step. The spacer 22 has a distinct n ⁻ and n ⁺ region 23 and 24 profile and n- or two n ⁻ and n ⁺ regions 23 and 24 extend somewhat into the channel region of the gate 14 and It is used to ensure that it is not. Moreover, two separation mask and masking steps are required to first implant the n ⁻ region 23 and the second stage is the separation of the n ⁺ region from the channel region for the purpose of providing a better source and drain isolated from the channel region. It is necessary to inject n ⁺ region 24 to provide.

At some instant, the n ⁺ region is first doped according to the doping of the n ⁻ region.

The advantage of n ⁻ formed first is that the ion channeling effect is slightly reduced.

The width of the area under each of the sidewall spacers 22 is generally named footprint. For the apparatus 10 of FIG. 2, the footprint for one of the sidewall spacers 22 is shown by the footprint distance 27. The width of the footprint 27 is evaluated by a threshold measurement to determine the extent of horizontal penetration of the n ⁻ region 23 in the substrate. The loose error in the width of the footprint 27 needs to generate a width imbalance in the penetrating range of the n ⁻ region 23, and thus more confronts the penetrating range of the n ⁺ region 24. Recognition of this change is a solution to understanding motivation while practicing the present invention. Therefore, it is desirable to maintain a small change with respect to the average value specified for the width of the footprint 27.

As shown in FIG. 3, the change in the inclination of the sidewall spacers 22 causes a corresponding difference in the width of the footprint 27, and this change in the inclination is inclined (as shown by dot line) 30,31. Is explained by). The difference in the width of the footprint 27 is n ⁺ region 24 and / or n − region to change correspondingly (shown as doped regions 32 and 33) from the channel region under the gate 14. Occurs. Any significant change in the position of n ⁺ region 24 and / or n ⁻ region 23 is the last effect of operating parameters of device 10, such as threshold, through hole voltage, source-drain leakage current. In the example of FIG. 3, the doped region 33 extends significantly into the channel region.

When region 33 extends slightly in the channel region, it is undesirably present and even deadly for the transistor (in the case of an extremely short channel device).

The change in element affects the dimensional width of the footprint 27. More notable elements are the gate 14 profile, as well as its nonuniformity, the inclination of the sidewall spacers 22, the nonuniform deposition of the oxide layer 27, the oxide layer 17 for forming the sidewall spacers 22. Etching irregularity, the imbalance crosses the wafer.

In addition, the slope of the sidewall spacer 22 at any moment changes during the next metal forming step and, with respect to the gate contact line remaining on the upper portion of the metal string gate 14, according to the sidewall 22, Extending from the source and / or drain region to the metal contacts. This condition causes an electrical short of the source and / or drain to the gate.

Finally, similar problems are encountered in the formation of p ^- channel devices. The p ⁻ and p ⁺ injections are equivalent to n ⁻ and n ⁺ injections, respectively. Therefore, the result or effect of the change in footprint error is more pronounced with n-channel devices than with p-channel devices.

Moreover, the change in footprint 27 is estimated to be less critical when applied to a device utilizing 1.5 micron technology and the error is not a threshold. However, when devices use smaller micron technology, such as 0.8, 0.5 or 0.35 micron technology, they are manufactured, so these errors are more progressively thresholded due to staging and contact of nearby device elements.

The semiconductor device of the present invention is provided for crystals in prior art devices to fabricate semiconductor devices utilizing sub-micron technology under 1.0 micron, more broadly using 0.8, 0.5 or 0.35 micron and smaller technology. do. Moreover, the technique is implied to improve the steps for submicron double doped source and drain. One technique that utilizes the inverse T-gate structure for a submicron LDD transistor is described by Brother et al in pages 1742-745 of a Novell submicron LDD transistor with an inverted T-gate structure in IEEE IDEM.

Referring to FIG. 4, a semiconductor device 40 of the preferred embodiment is shown. The device 40 is a MOS device having a substrate 41 that is typically made of silicon. Field oxide regions 42 are formed on the substrate 41 for localization of circuit element formation. The field oxide regions are shown in FIG. 4 to isolate the region of device 40 for the formation of a given circuit element. A gate 44 is formed in the substrate 41, which consists of a pulley silicon region 45 separated from the substrate 41 by the dielectric region 46.

The dielectric region generally consists of an oxide such as silicon oxide (SiO 2).

After formation of the gate 44, an oxide layer 47 is deposited over the device 40. In a preferred embodiment, oxide layer 47 is conformally covered with silicon oxide (SiO2) and suitable chemical vapor deposition (CVD) known to obtain conformal topologies (isometric means in which the deposited layer adapts to underlying topologies). ) Is deposited by treatment. Such deposition of SiO 2 is well known in the art. CVD oxide layer 47 is deposited to a thickness in the range of approximately 100-1000 GPa. SiO 2 is good by providing SiO 2 for the minimum and controllable interface charge provided by SiO 2 on the underlying silicon.

Referring to FIG. 5, it is shown that a CVD conformal nitride layer 48 is next deposited over the CVD oxide layer 47. Nitride layer 48 is deposited by CVD, such as thermal decomposition of salane SiH ₄ and ammonia NH ₄ to a thickness of approximately 100-1000 kPa. Thus, the nitride layer 48 of this preferred embodiment is made of silicon nitride Si ₃ H ₄ , although any dispositionable material with optionally good etching, depending on SiO ₂ and Si, may be used. Polysilicon is used less well because its conductivity remains in the next step below.

Next, the two layers 47 and 48 are selectively etched to expose the portion of the substrate 41 between the FOX regions 42 and 44. The exposed substrate region later forms a source and a drain region for the gate 44. Nitride layer 48 is etched first, and the more selective for the SiO ₂ SiO ₂ layer 47 it is further selectively etched with respect to silicon nitride and both. This technique is allowed for endpoint detection and a more defined staircase structure is shown in FIG.

Dry anisotropic etching is used for both etching cycles.

Because of the formation of the nitride layer 48 on the oxide layer 47, several advantages exist. The nitride etch not only provides for a more uniform etch cycle than oxide etch, but also has better anisotropic properties. Incidentally, with the use of nitride etching, the FOX region is allowed for controlled isolation (field-inverson voltage threshold) and does not etch away. In the prior art device of FIG. 1, it is apparent that the oxide etching of the oxide layer 17 results in the portion of the FOX region 12 to be etched separately from the case where the thickness of the oxide layer 17 is not constant. Therefore, with the device 40 of the present invention, nitride etching is used, and therefore, because of better selectivity, the FOX region 42 is not etched and at least not provided as an oxide etch of the prior art device 10 and controlled isolation. And for controlled metal line parasitic capacitance.

Referring to FIG. 6, an apparatus 40 after a nitride etch cycle is described. Because of the anisotropic nature of the nitride etch, a portion of the oxide 47 is adjacent to the axial wall of the gate 44 that remains completely. This sidewall spacer 52 is wider at the base as appropriate for the substrate 41, so that the portion 53 of the nitride layer 48 is formed at the spacer 52 due to the conformal topology of the initially formed layer 47. Remaining adjacent, the nitride appears thick due to anisotropic etching to the sharp sidewall confinement of the gate 44. Next, nitride portion 53 is selectively removed by isotropic or anisotropic nitride etching.

After removal of the nitride remainder 53, only the sidewall spacers 52 remain adjacent to the gate 44. Due to the initial bottom nitride 53 protecting the bottom oxide spacer 52, a stepped shape is provided for the shape of the sidewall spacers 52, as shown in FIG. 7.

Because of conformal deposition of the oxide layer 47, the thickness of the spacer 52 and the upper portion is approximately equal to the thickness 51 of the lower portion of the spacer 52. Thus, the thickness 50 of the spacer 52 adjacent to the gate 44 sidewalls is determined by the thickness of the conformal oxide layer 47.

At some point, the portion of the original oxide layer 47 is estimated to remain normally on the top surface of the gate 44. At another instant, the upper range of the sidewall spacers 52 lies below the plane formed by the top surface of the gate 44, whereby the sidewall portions of the gate 44 are exposed. Therefore, at every instant the critical element maintains a nearly constant footprint with respect to the spacer 52 as described below.

7 shows the footprint 54 of one sidewall spacer 52. The footprint 54 is separated by the separating portion 57 (forming a staircase shape) from the surface of the spacer 52 in the footprints 55 and 56.

The footprint 55 is determined by the width of the spacer 52 from the separation portion 57 to the sidewall of the gate 44, and the width is equal to the thickness 50.

The footprint 56 is determined by the width of the spacer 52 portion from the separator 57 to the distal end of the lower portion of the spacer 52.

Because of the initial lower nitride layer 48 and the selectivity of the nitride etch and the measurement of the footprint 54, the footprints 55 and 56 are evaluated to maintain a close error. These parameters depend on the thickness of the layers 47 and 48 and the nitride etch step described above. That is, the width of the footprint 55 is determined by the deposition thickness of the oxide layer 47, while the width of the footprint 56 is determined by the nitride layer 48 and the deposition thickness. Therefore, the sum of the thicknesses of the two layers 47 and 48 determines the width of the overall footprint 54.

Moreover, the inclination formation of the spacer 22 of the prior art device 10 is intended to change the footprint 27, and such inclination change is reduced because the lower nitride region 53 is not present.

The lower spacer area 52 is protected thereby maintaining small changes in the sharp profile and the footprints 55, 56.

Referring to FIG. 8, a mask layer 60 is formed, where the mask layer 60 keeps these areas exposed and n ⁻ implantation takes place. Next, n ⁻ implantation is achieved by using one of the variations of known self-aligned implantation techniques. The energy of n ⁻ implant is chosen to be sufficient to have an ion through hole and the lower portion of the spacer 52 for reaching the portion of the substrate corresponds to the footprint 56 and the through gate 44 and the spacer 52 It does not have a sufficient value for the upper portion 59 of.

The n ⁻ implantation step also implants an ion wall into the exposed substrate 41. Thus, the upper portion 50 of the spacer 52 and the gate 44, adjacent to the gate 44, provide self alignment during the migration step. Each of the n ⁻ regions 63 formed on the opposite side of the gate 44 extends in the substrate region below the lower portion 58 of the spacer 52 formed in the substrate and designated as footprint 56.

As indicated in the figure, the depth of n ⁻ implant in the substrate bottom footprint is not as deep as the implant region of the exposed substrate.

In FIG. 9, the following n ⁺ injection steps are described.

The next masking layer need not be used for n ⁺ implantation and is similar to the prior art device case of FIG. The use of the same masking layer for both n ⁻ and n ⁺ implantation means that only one mask and masking step cycle are used during the manufacture of the device 40 of the present invention. As shown in FIG. 9, the same masking layer 60 is used for n ⁺ ion implantation. The use of the same masking step for two injections reduces the step factor and allows for reduced manufacturing costs and production risks.

Since the implantation energy level is sufficiently low, the lower portion 58 functions as a mask to prevent the proper penetration of n ⁺ ions into the substrate region under the spacer, and the n ⁺ source and the substrate 41 in the substrate 41. Drain region 64 extends substantially from the edge of footprint 56 toward FOX region 42.

At the end of the n ⁺ implantation step, the double doped source and drain regions have n ⁺ region 64 separated from the channel region lower gate 44 by n ⁺ region 63. The n ⁺ region 64 is implanted first, followed by n ⁻ implantation to form the n ⁻ region 63. At some point, n + implantation is provided to provide added control of the n− profile, so that part of this region transfers by limiting the ion channeling effect.

Referring to FIG. 10, the following annealing step is shown in which n ⁻ and n ⁺ regions 63 and 64 are also diffused onto the substrate, including diffusion towards the channel region. Accurate control is obtained as a horizontal diffusion range of n ⁻ and n ⁺ regions 63, 64 towards the channel region, as well as the tight errors obtained in the spacer 52 footprint 54. Thus, the n ⁻ region 63 extends to a position just below the sidewall of the gate 44. This control allows for a turn-on characteristic and provides instantaneous minimum capacitance for the source or drain to the gate. That is, the boundary of n ⁻ region 63 diffuses from footprint region 56 to footprint region 55, whereas the boundary of n ⁺ region 64 extends footprint region 56 (during the annealing step). (See Figure 7).

Dense source drain spacing control, source, made of device elements, because of the sharper distinction of the boundary positions of each of the regions 63 and 64 referenced to the channel region within the apparatus 40 of the present invention, as compared to the prior art apparatus. And drain doping profiles are obtained. This provides improved limitations on the devices to be formed for use in devices fabricated using submicron techniques such as 0.8, 0.5 and 0.35 micron techniques.

Moreover, equivalent techniques can be used to provide for source and drain regions in p ^- channel devices. p ^- injection is performed instead of n ^- injection. Conversely, instead of n ⁺ injection, p ⁺ injection is used. As with the n ^- channel device, either p ^- or p ⁺ implantation is performed first, and the nitride layer thickness and implant energy, source and drain characteristic profiles and dimension are tightly controlled by controlling the oxide layer thickness. .

Referring to Figures 11-16, a compensation-metal-oxide peninsula (CMOS) device 70 of the present invention fabricated on a silicon substrate is shown. The p ^- channel wall (41a) and the n ^{- -} p in the wall (41a) formed in the channel wall (41b) are known in the art. The n ⁻ channel device 40a is manufactured on the p ⁻ wall 41a, while the p ⁻ channel device 40b is manufactured on the n ⁻ wall 41b. The FOX region 42a not only separates the p and n regions, but also separates each region from other regions of the circuit configuration.

When the first 11 degrees to the reference n ^- channel and p ^- channel device region (41a) and (41b), after forming the gate (44a, 44b) above the substrate in each, respectively, a side wall spacer of claim 4-6 in Fig. Are formed for each gate 44a and 44b according to the process described earlier for this.

At that time, after etching the nitride residues 53a and 53b, an n ⁺ / n ^- mask layer 60a is formed by exposing the implanted n-channel device region, as shown in FIG. The p ⁻ channel device region is covered during n ⁻ and n ⁺ implantation. The n ⁻ implantation is formed, which is the same as the process described with reference to FIG. 8 to form the n ⁻ region 63a in the p ⁻ wall 41a. Next, using the same masking layer 60a, n ⁺ region 64a is formed in the substrate according to the process initially described with reference to FIG. Thus, the n ⁻ channel device 4a is equivalent to the device 40 of FIG. 9 and is formed in the p ⁻ wall 41a.

Thus, a p ⁺ / p ⁻ mask layer 60b is formed, exposing an implanted p ⁻ channel device region as shown in FIG.

Next, p ⁻ implantation is performed according to the process described earlier.

Next, as shown in FIG. 15, p ⁻ injection is made.

The p ⁺ channel device 40b fabricated on the n ⁻ wall 41a is equivalent to the device described earlier in FIG. 9 except that it is a p ⁻ channel device having p ⁻ and p ⁺ implants, Thus, during the annealing step, the n ⁻ , n ⁺ , p ⁻ , and p ⁺ regions 63a, 64a, 63b, 64b provide equivalent n ⁻ channel and p ⁻ channel devices as described with reference to FIG. 10. To spread. The last product is the CMOS device 70 shown in FIG. 16 and has n ^- channel and p ^- channel devices made in accordance with the practice of the present invention. The CMOS device 70 is fabricated using submicron technology, such as 0.8, 0.5, 0.35 and smaller micron technology. Again, either the injection of p ⁻ or p ⁺ as well as n ⁻ or n ⁺ is performed first.

Referring to FIG. 17, another embodiment of the present invention is shown. After formation of the gate 44c, the removal of the remaining nitride relative to the sidewall spacers 52c and the sidewall spacers 52c is in accordance with the process described earlier in the present invention, wherein the polysilicon layer 73 is each exposed substrate region. The formation and use of rising polysilicon (rising poly) layers formed on the substrate is well known, and such techniques are described by O.H. et al. In a new MOSFET structure with self-aligned polysilicon source and drain electrodes of an IEEE electronic device letter of 1984. See pages 400-402 of EDL-5, 10, and Yamada et al. On pages 35-38 of spread source / drain (SSD) MOSFETs, which selectively use silicon growth for IEEE IEDM's 64Mbit DRAM in 1989.

After formation of the elevated poly 73, n ⁻ and n ⁺ implants 63c and 64c are performed according to the steps described earlier in the practice of the present invention.

The annealing step diffusion is described to control the doping profile under the foot region as initially described. Thus, during the annealing step, silicidation of the elevated silicon (silicidation is a metal silicide formation on the source and drain and / or self-aligned gate regions) occurs when a silicide forming metal such as titanium or cobalt is present. do.

The final result is illustrated in FIG.

Since the polyside layer overlapped with the polysilicon is not complicated as shown in Fig. 18, the formation of the silicide layer can be shown in Fig. 21, and the polysilicon layer shown in Fig. 18 (both rising and gate poly) Is formed on the phase. Equivalent techniques are readily used to fabricate p-channel devices that provide rising polys.

The lower portion 58c (step portion of the staircase) of the spacer 52c is designed to be larger, equal or smaller than the thickness of the polysilicon 73. The next source / drain regions are thus formed in the base substrate as well as polysilicon 73.

In FIG. 19, the CMOS autonomous 77 refers to FIG. 16 except that the source and drain regions of the n-channel device and p ^- channel device elements 63d, 64d, 63e, 64e have a rising poly 73a. The same is shown with the CMOS device 70 described as. A sufficient advantage of using raised poly technology is that implanted ions are implanted or deposited into the raised poly before diffusing the dopant into the substrate.

Therefore, implant damage and initial doping are initially included in the rising poly and there is no real single crystal substrate. This reduces the source / drain to substrate capacitance and reduced junction leakage.

Implantation in a good grain polysilicon rise drain injects a fast masking gate in crystalline silicon, thereby providing a fast transverse expansion medium to overcome normally displayed shadowing effects.

Referring to FIG. 20, another embodiment is shown using raised polysilicon 73f. In this embodiment, the polysilicon 73f is thicker than the lower portion (foot) of the spacer 52f. One selectively dope the n ⁻ region, making the lower portion of the spacer thinner than the rising drain.

In other words, the suppressing portion 65 is formed between the spacer 52f and the polysilicon 73f. When n ⁻ implantation is formed at a controlled energy level, the n ⁻ region is actually formed in the substrate under the suppressor 65. Then n ⁺ implant finally diffuses over a limited range in the substrate below the polysilicon 73f and the substrate overlapping with the suppressor 65 and injects low energy into the rising polysilicon. Thus, a narrow n ⁻ pocket region 63f is formed between n ⁺ region 64f and the channel region.

Again either n ^- or n ⁺ injection is formed first. This technique is also well used as a p-channel device. The resulting structure with the next silicide metallization layer 74 is shown in FIG.

An improved stepped sidewall spacer for source / drain formation is therefore described. It is apparent that other changes can be obtained in which the change in the doping profile is observed under greater control than the practice of the prior art.

Claims (7)

In the process of manufacturing a semiconductor device 40 having a source 44 formed under a source and a drain gate adjacent to a channel region, and having a gate 44 formed on the substrate 41, a conformal oxide layer 47 is formed on the substrate and the gate. Depositing, depositing a conformal nitride layer 48 over the oxide layer, and oxide portions adjacent to each side of the gate to form sidewall spacers 52, however, until a portion of the substrate is exposed. Isotropically etching the nitride and oxide layers having portions 53 of the nitride layer remaining therefrom, each spacer remaining therefrom, and remaining on each spacer to be exposed underneath the oxide spacers Etching portions of the nitride layer and removing portions of the nitride layer remaining on each spacer so as to be exposed underneath the oxide spacers. Selectively removing the bag, wherein each of the oxide spacers has an upper portion having a first width 55 and a base portion having a second width 54, the upper portion to form a step shape The first width is approximately equal to the thickness of the oxide layer and the second width is approximately equal to the sum of the thicknesses of the oxide and nitride layers, and the polysilicon layer 73 is disposed on the exposed substrate. And injecting first energy at a first energy level, wherein the first ions are formed from the bottom substrate of the raised polysilicon layer and the raised polysilicon layer and a first doped region in the substrate ( Implanting second ions into a lower staircase portion of the oxide spacer to form a second step, and implanting second ions at a second energy level that is lower than the first energy level. And the second ions are implanted into the oxide spacer to form a nearly doped polysilicon layer and a second doped region 64 in the substrate underneath the raised polysilicon layer, the lightly doped 63 with the correct position An implanted source that provides a heavily doped region forming a doped source and drain, wherein the source and drain also diffuse into the substrate while the source and drain hardly extend into a channel region under the gate; And annealing the drain. The method of claim 1 wherein the first doped region is ^n-n obtained by the ^{insertion-region} and the second doped region is n ⁺ region in a semiconductor device manufacturing process, obtained by a n ⁺ implant. The process of claim 2, wherein implanting the second ions to form the n ⁺ region occurs before implanting the first ions to form the n ⁻ region. The method of claim 1 wherein the first doped region is a ^p-p obtained by the ^{insertion-region} and the second doped region is a p ⁺ region obtained by the semiconductor device manufacturing p ⁺ implantation. The process of claim 4, wherein implanting the second ions to form the p ⁺ region occurs before implanting the first ions to form the p ⁻ region. The process of claim 6 wherein the oxide layer has a thickness of approximately 100-1000 GPa and the nitride layer has a thickness of approximately 100-1000 GPa. The n ⁻ channel device has a step of forming using the process as claimed in claim 1, whereas the first ion implantation step comprises n ⁻ ion implantation, and the second ion implantation step is n ⁺ An ion implantation, the p ^- channel device having a step formed using a process as claimed in claim 1, wherein the first ion implantation step comprises a p ⁻ ion implantation, and a second ion The implantation step comprises a p ⁺ ion implantation process.