KR960011651B1 - Dram cell device - Google Patents

Abstract

a branched active region(26) with three branches(26a,26b,26c) connected with each other on the surface of a semiconductor substrate; a word line(WL) cross connected one to one with the two branches(26a,26b) of the active region(26) by forming a gate insulating layer on the active region(26); and a drain contact(30) formed on the remaining branch(26c) of the active region.

Description

DRAM Cell Memory Device

1 is a circuit arrangement diagram showing a portion of a DRAM memory device integrated on a substrate according to the prior art.

2 is a circuit arrangement diagram showing only the active region in FIG. 1, and FIG. 2a is a circuit arrangement diagram of word lines and drain contacts formed on the circuit arrangements of FIGS. 2b and 2a. Floor plan.

3 is a circuit arrangement diagram showing an arrangement of active regions formed in accordance with the present invention.

4 is a circuit arrangement diagram showing word lines and drain contacts formed on the active region shown in FIG.

FIG. 5 is a circuit arrangement diagram showing a bit line connected to the active region through a drain contact formed on the circuit arrangement shown in FIG. 4, and a bird contact for connecting the storage electrode.

6 is a circuit arrangement view showing a storage electrode formed on the circuit arrangement shown in FIG.

* Explanation of symbols for main parts of the drawings

10, 26: active region 12, 28: separation oxide film

16, 30: drain contact 20, 32: bird contact

22, 34: storage electrodes T1, T2: cell transistors

The present invention relates to a semiconductor DRAM cell memory device, and more particularly, to a circuit arrangement of a DRAM cell integrated on a semiconductor substrate.

In the manufacture of DRAM (Dynamic Random Access Memory) cell memory devices, one of the requirements for improving the degree of integration is to reduce the area of the unit memory cell. In general, the density of the memory device is increased by four times, and thus the area of the chip is also reduced by one quarter. It is well known to those of ordinary skill in the art that the minimum feature size (abbreviated as F) should be reduced to one half to reduce the chip area to one quarter. As the integration density increases, the minimum wiring width becomes smaller and smaller. For example, the minimum wiring width F of a 64 megabit DRAM is known as about 0.2 μm. If the minimum wiring width is small, it is difficult to secure an alignment margin according to the photo-lithography process, and thus, the stability of the transistor becomes a problem. In addition, another problem that arises as the minimum wiring width becomes smaller is a technique of designing a layout to have an efficient circuit arrangement. An example of the prior art for the circuit arrangement of such a highly integrated memory device is A.28μm ² Bit-Line Shielded Memory Cell Technology for 64Mb DRAMS at 1990 VYSIOS ON VLSI TECHNOLOGY by Hitachi, Kawamoto et al. Was released. Hereinafter, a description of the above-described prior art will be disclosed. For more details, refer to pages 13-14 of the 1990 SYMPOSIUM ON VLSI CIRCUITS DIGEST OF TECHNICAL PAPERS, which is a collection of papers published in the symposium.

FIG. 1 is a circuit arrangement diagram of the DRAM cell disclosed in the related art, and FIG. 2 is a diagram for showing the circuit arrangement shown in FIG. 1 in detail. FIG. 2a is a circuit arrangement diagram showing only an active region in FIG. FIG. 2B is a circuit arrangement diagram in which a word line and a drain contact are formed on the circuit arrangement of FIG. 2A.

Referring to FIG. 1, after forming an active region 10 and a field oxide layer on a semiconductor substrate, a word line 14, a drain contact 16, a bit line 18, and a bird contact 20 are formed thereon. And a circuit arrangement diagram formed by sequentially forming storage electrodes 22 for storage capacitors.

2A includes a plurality of active regions 10 formed on a main surface of a semiconductor substrate and a field oxide film 12 electrically separating the active regions 10. For convenience of explanation, the direction extending in the left and right directions of FIG. 2 is referred to as the A direction and the direction extending in the vertical direction is referred to as the B direction. The active region 10 is formed of an inclined portion 10a and parallel portions 10b and 10c positioned at both ends of the inclined portion 10a. In a subsequent process, the active region 10 includes an inclined portion 10a. A storage line of the storage capacitor connected to the active region 10 through a word contact extending in the B direction and a buried contact on the side thereof, and a bit line extending over the parallel portions 10b and 10c. Is formed.

FIG. 2B is a circuit arrangement diagram in which a word line 14 and a drain contact 16 are formed on the top of FIG. 2A. The word line 14 intersects the active region 10 via the gate insulating layer, and the intersection thereof operates as the cell transistors T1 and T2. The drain contact 16 is formed on the inclined portion 10a of the active region 10 shown in FIG. 2a (formed between two neighboring cell transistors T1 and T2) and consequently two memories. The cell shares one drain contact. Accordingly, two memory cells sharing a bit line are formed in one active region 10 shown in FIG. 2A.

However, the conventional circuit arrangement shown in FIG. 1 has a problem in that the efficiency of the active region and the stability of the cell transistor are deteriorated.

That is, the reason why the efficiency of the active area is lowered is, as shown in FIG. 2A, a wide area located between one active area and an adjacent active area is generated as the empty area 24. According to the related art, since the word line passes through the upper limit region 24, the empty region 24 is necessary to reduce the capacitance load of the word line. Therefore, the generation of the blank area is inevitable, and the occurrence of the blank area results in a reduction in the area capable of forming the active area in the entire area of the semiconductor substrate surface. That is, in terms of forming the active region, the efficiency is lowered, resulting in a decrease in the density.

In the prior art shown in FIG. 1, the drain contact 16 and the edges of the cell transistors T1 and T2 are formed very narrowly. As a result, the alignment margin is small in the photo-lithography process, making the manufacturing process difficult.

In addition, as the doping of the bit line with a high concentration of impurities in order to increase conductivity, the junction depth of the drain contact 16 portion becomes deep, so that adjacent cell transistors are vulnerable, thus ensuring stability of the transistor. it's difficult.

Accordingly, an object of the present invention is to provide a DRAM cell memory device having an electrically stable cell transistor even in a highly integrated memory device.

Another object of the present invention is to provide a DRAM cell memory device having an improved degree of integration by eliminating occurrence of an empty area between neighboring active areas.

Another object of the present invention is to provide a DRAM cell memory device having a sufficiently spaced distance between a drain contact and a cell transistor to which a bit line is connected to an active region so that the cell transistor can be stably operated.

It is still another object of the present invention to provide a DRAM cell memory device having a circuit arrangement capable of securing an alignment margin of a photolithography process by adjusting the width of a word line.

According to the present invention for achieving the above objects, an active region formed on a main surface of a semiconductor substrate is formed of three branched active regions connected to each other at predetermined portions, and a word line is formed of two branched portions of the active region. Each cell transistor is formed to cross each other in the active region, and the drain cell to which the bit line is connected is formed on the other branch active region not connected to the word line. As a result, the cell transistor and the tre contact are positioned on different branch active regions, thereby ensuring a sufficient separation distance therebetween.

Therefore, according to the present invention, a sufficient separation distance between the drain contact for connecting the bit line and the cell transistor is secured, thereby increasing the stability of the cell transistor and ensuring sufficient alignment margin of the drain contact forming process. Since no blank area is generated between the active areas, the degree of integration can be improved by increasing the efficiency of the active area arrangement.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6. 3 to 6 are diagrams showing a preferred embodiment of the present invention, which is a circuit arrangement diagram sequentially showing circuit arrangements for each layer according to the integration of memory devices. Among the figures 3 to 6, in particular, the figures in which the features of the invention are revealed are 3, 4 and 5, respectively. If those skilled in the art look at the order from 3 to 6, it will be fully understood in the present invention without referring to the following description.

First, look at FIG. 3 is a circuit arrangement diagram showing an active region formed in accordance with the present invention, in which a plurality of active regions 26 are electrically insulated from each other by a separate oxide film 28 on the main surface of the semiconductor substrate. The active region 26 is formed of three branched active regions 26a, 26b and 26c connected to each other on a portion thereof.

In a subsequent process, word lines intersecting the two branch active regions 26a and 26b of the active region 26 through a gate insulating film are formed, and an intersection portion of the word line and the active region is formed. Will operate with each cell transistor. The bit line extends in the direction orthogonal to the word line on the other branch active region 26c, and the bit line and the branch active region 26c are connected to each other by a drain contact. Therefore, since the cell transistor and the drain contact are sufficiently separated from each other, the stability of the cell transistor is increased, and the alignment margin of the drain contact process is sufficiently secured. In FIG. 3, one active region 26 has six active regions around it, and it can be seen that an empty region does not occur between neighboring active regions. Therefore, it is possible to secure a sufficient active area so that no blank area is generated between the active areas. Therefore, sufficient active area can be secured, and the efficiency of the active area can be increased, and as a result, the degree of integration can be improved.

4 is a circuit arrangement diagram showing the word line WL and the drain contact 30 formed on the circuit arrangement shown in FIG. The word line WL is formed to intersect the two branch active regions 26a and 26b of the active region 26 through the gate insulating film, and thus, the portion where the word line WL and the active region 26 cross each other is formed. The cell transistors T1 and T2 are operated. The drain contact 30 is a contact for connecting the bit line and the active region 26 in a subsequent process and is formed on the other branch active region 26c. Particularly, the portion of the word line WL adjacent to the drain contact 30 is formed to reduce its width. The reason why the width of the word line is narrowed in this area is to secure the alignment margin when forming the drain contact in a subsequent process. That is, the word line WL according to the present invention is formed such that the word line width of the region adjacent to the drain contact 26 is narrowed to a predetermined size as compared with the portion to operate as the gate electrode of the cell transistor. Please note that this is one of the technical ideas. Therefore, according to the present invention, a sufficient separation distance between the cell transistor and the drain contact is secured, and an alignment margin between the word line and the drain contact is sufficiently secured.

FIG. 5 shows a bit line BL orthogonal to the word line on the circuit arrangement shown in FIG. 4 and connected to the branch active region 26c via the drain contact 30, and then branches in the subsequent process. FIG. 26 is a circuit arrangement diagram in which a buried contact 32 for connecting the storage electrodes 26a and 26b with the storage electrodes of the storage capacitor is formed. The bit line BL is formed to be orthogonal to the word line WL, and is connected to the branch active region 26c disposed below the drain line 30 through the drain contact 30. The buried contact 32 is a contact for connecting the storage electrode of the storage capacitor with the lower branch active regions 26a and 26b. The buried contact 32 is formed between the word lines WL having no drain contact 30.

FIG. 6 is a circuit arrangement diagram in which the storage electrode 34 is formed on the circuit arrangement of FIG. The storage electrode 34 is connected to the lower branch active regions 26a and 26b through the buried contact 32. After the formation of the storage electrode 34, a dielectric film and a plate electrode are generally formed through a manufacturing process.

Although the present invention has been described in accordance with the embodiments shown in FIGS. 3 to 6, the present invention is not limited thereto and can be implemented in various modified forms within the basic idea category of the present invention. Anyone with knowledge will know it clearly.

As described above, according to the present invention, since the cell transistor is sufficiently spaced apart from the drain contact, it is possible to ensure the stability of the transistor operation, and the portion located on the side of the drain contact at the time of forming the word line is formed of the word line. Since the width is reduced, the alignment margin at the time of forming the drain contact is sufficiently secured.

This effect of the present invention is achieved by forming an active region into three branched active regions connected to each other on a portion, forming a cell transistor on the two branched active regions, and forming a drain contact in the other branch.

Claims (2)

A DRAM cell memory device comprising: three branched active regions connected to each other on a part of a main surface of a semiconductor substrate, and the branched active regions intersect one to two of the branched active regions through a gate insulating film at an upper portion thereof; And a circuit arrangement including a word line to be connected to each other and a drain contact formed at the other side of the branch active region. The DRAM cell memory device of claim 1, wherein the word line is formed to have a narrower line width at an adjacent portion of the drain contact to a predetermined size than other portions.