KR960015603B1 - Aal5 common part convergence sublayer and reconstruction method by respective buffer method - Google Patents

Abstract

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Description

Individual buffered A.A. type 5 common partial convergence sublayer receiver and reassembly circuit

1 is a schematic configuration diagram to which the present invention is applied;

2 is a schematic configuration diagram of the present invention,

3 shows an example of format allocation of a control buffer.

4 is an exemplary format allocation diagram of a reassembly buffer.

* Explanation of symbols for main parts of the drawings

1: Service Specific Convergence Sublayer (SSCS)

2: Common Part Convergence Sublayer (CPCS)

3: Segmentation and Reassembly (SAR)

4 ATM matching unit 5 control buffer

6: control buffer control unit 7: reassembly buffer

8: message buffer control unit 9: message buffer

10: Completed Message Pointer FIFO

11: Free List FIFO 12: Register

The present invention is located on the ATM layer in the Asynchronous Transfer Mode (ATM) method, which is a transmission method used in a Broadband-Integrated Services Digital Network (B-ISDN), and reassembles a cell accompanying an ATM layer into a message. Individual buffered AAL Type 5 Common Part Convergence Sublayer (hereinafter referred to as CPCS) and Reassembly (Segmentation) that deliver messages to Dependent Convergence Sublayer (hereinafter referred to as SSCS) and Reassembly, hereinafter referred to as SAR).

Conventionally, in order to implement a SAR and CPCS receiver, a cell received at an ATM layer is stored in a shared memory with information of a message belonging to each cell in a shared memory using a shared buffer scheme, and when the message is completed, all cells belonging to the message are completed. There was a method of completing the message by reassembly, but the above method has a disadvantage in that the buffer control is complicated and not easy to implement.

The present invention devised to solve the above problems of the prior art, by using a reassembly buffer of a fixed size by the size of the maximum message to be reassembled without using a complex buffer control circuit of the individual buffer type AAL type 5 The purpose is to provide a common partial convergence sublayer receiver and a reassembly circuit.

In order to achieve the above object, the present invention provides a common partial convergence sublayer receiving unit and reassembly for delivering a message to a service specific convergence sublayer (SSCS) by reassembling a cell received at an ATM layer into a message. A circuit, comprising: ATM matching means for performing matching with an ATM layer; A reassembly buffer connected to said ATM matching means and storing a reassembled cell; Control Buffer control means for determining the address and message assembly state of the reassembly buffer using the parameters extracted from the ATM matching means: Control buffer connected to the ATM matching means, the information of the reassembly buffer Control buffer to store current address and starting address parameters; A message buffer controller configured to read the completed message in the reassembly buffer, perform a CRC, and remove padding; A message buffer for storing the message transmitted from the message buffer control means for the SSCS to read; Completed message pointer first-in first-out means for receiving a parameter and a pointer from the control buffer to first-in, first-out a completed message pointer to the message buffer control means; Free list first-in, first-out means connected to said message buffer control means for storing each start address of said reassembly buffer; And a register connected to the control buffer control means and the message buffer control means for transmitting information on an operation mode, an operation state, and an interrupt of each control block to an external microprocessor.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1 is a schematic hardware diagram to which the present invention is applied, in which 1 is a Service Specific Convergence Sublayer (SSCS), 2 is a Common Part Convergence Sublayer (CPCS), 3 Denotes a reassembly (Segmentation and Reassembly (hereinafter SAR)), respectively.

As shown in the figure, when explaining block by block in the hardware configuration to which the present invention is applied, the SAR (3) is a part which removes a header from a cell received at an ATM layer and reassembles it into a message. ) Is a part that removes the padding data from the reassembled message and performs an error check by performing a cyclic redundancy check (CRC), and SSCS (1) adds a header and a trailer for each specific service to the finally assembled message. to be. The present invention relates to SAR and CPCS, which are commonly required for assembling a message before a message is reprocessed for a specific service.

2 is a schematic view showing a schematic configuration of the present invention, in which 4 is an ATM matching unit, 5 is a control buffer, 6 is a control buffer controller, 7 is a reassembly buffer, 8 is a message buffer controller, and 9 is a message buffer. 10 denotes a Completed Message Pointer FIFO, 11 denotes a Free List FIFO, and 12 denotes a register.

As shown in the figure, the present invention provides an ATM matching unit 4 which separates cells raised from an ATM layer into IDs, parameters, and VCIs, and a start address, a current address, and a completion address of a reassembly buffer using the VCIs as addresses. A control buffer 5 for storing information, a control buffer controller 6 for controlling the control buffer 5, a reassembly buffer 7 for storing the ID for each VCl, and a completed in the reassembly buffer 7 The message buffer control unit 8 reads a message, performs a CRC, removes padding, and delivers the message to the message buffer 9, and stores the message transferred from the message buffer control unit 8 so that the SSCS can read it. The message buffer 9, the start and end address of the reassembly buffer when the message is completed in the control buffer 5, and the completed message pointer first-in-first-out unit 10 for storing the parameters, and each start address of the reassembly buffer. Save it Has a free list of first-in-first-out unit 11, a register 12 for storing the message to transfer the operation and status parameter together as they pass towards the SSCS of the message buffer (9).

First, the cells raised from the ATM layer are separated from the ATM matching unit 4 by the contents of the payload (hereinafter referred to as ID), the parameters, and the connection number (Virtual Channel Identifier; hereinafter referred to as VCI). The extracted VCI directly designates the address area of the control buffer 5, and at the designated address, information regarding the start address of the message in the reassembly buffer of the VCI, the address of the message currently being assembled, and the message completion are stored.

3 is an exemplary diagram of format allocation of the control buffer 5.

As shown in the figure, the control buffer 5 is allocated a control area of 8 bytes, i.e., 64 bits, for each VCI, so that the start address of the reassembly buffer 7 for the VCI is assigned to the upper 3 bytes. The byte contains the address of the VCI that was previously assembled, that is, the address of the reassembly buffer (7) that will now store the VCI, and the last two bytes contain 10 bits for storing the timer value, the parameters and message sent from the ATM cell. Record information about the status in the remaining six bits. Since the VCI of the ATM cell is 16 bits, there must be 65536 64 bit control regions in the control buffer 5. In this way, an ATM cell transmitted with a specific VCI value can be messaged for each VCI.

If a cell is the first cell to arrive at a particular VCI, then the free address is first-in-first-out (11) to get the start address of the currently available reassembly buffer; otherwise, if it is the second or more arrival cell, the current reassembly buffer address Is stored at the VCI address in the control buffer 5. At this time, the ID is stored in the address of the reassembly buffer 7 delivered from the control buffer 5 if the VCI cell has arrived more than the second time and from the free list first-in-first-out unit 11 if the cell arrived first. In the free list first-in-first-out part 11, the start address of the reassembly buffer 7 should be recorded for each message when the power is applied to the circuit.

If the cell is being reassembled into a message and contains information indicating that the cell arrived this time is the last cell of the VCI message, the parameter extracted from the ATM matching unit 4 is stored in the VCI address of the control buffer 5. The start address of the reassembly buffer 7 and the parameters stored in the completed message pointer first-in-first-out 10 and used by another VCI for the start address of the reassembly buffer 7 that was used for assembling the VCI message. It stores in the free list first-in-first-out part 11.

4 shows an example of format allocation of the reassembly buffer 7.

As shown in the drawing, in the reassembly buffer 7, if a message is assumed to have a maximum length of 10 cells, that is, 480 bytes, an area capable of assembling a 480-byte message must exist as the maximum number of messages (k) that can be assembled at the same time. do.

If a message is assembled and a message is assembled in the reassembly buffer 7, and the address and parameters related to the message are stored in the completed message pointer first-in-first-out section 10, the message buffer control section 8 is completed. After reading the address and parameters of the reassembly buffer from the message pointer first-in-first-out unit 10, read the assembled message from the assembly buffer 7, perform CRC, remove the padding, and read SSCS. It is stored in the message buffer 9 so that it can go. If there is no error, an interrupt is generated to the CPU and the SSCS, which is loaded to the CPU, is read from the message in the message buffer 9 and the operation and status information in the register 12. At this time, the start address of the reassembly buffer which is not used since the message assembly is completed is stored in the free list first-in-first-out unit 11 for use by other VCI messages. Here, description of terms used in the drawings is as follows. n is the number of VCIs, CLP is the Cell Loss Priority, AUU is the ATM-User-to-User Indication, CI is the Congestion Indication, and k is the maximum number of messages that can be assembled simultaneously.

Therefore, the present invention constructed and operated as described above has a relatively simple SAR and CPCS receiver circuit without a buffer control circuit dressed by having an individual reassembly buffer as much as an acceptable message size for each VCI and having a control buffer as much as an available VCI. There is an effect that can be configured.

Claims (3)

In a common partial convergence sublayer receiver and reassembly circuit for reassembling a cell received at an ATM layer into a message and delivering a message to a service specific convergence sublayer (SSCS), matching with the ATM layer is performed. ATM matching means 4 to perform; A reassembly buffer (7) which is connected to said ATM matching means (4) and stores the reassembled cell; Control buffer control means (6) for determining the address and message assembly state of the reassembly buffer (7) using the extracted parameters from the ATM matching means (4); A control buffer (5) connected to the ATM matching means (4) and storing information (e.g., current address and start address parameters) of the reassembly buffer (7); A message buffer control unit 8 for reading a completed message in the reassembly buffer 7 to perform a cyclic redundancy check (CRC) and to remove padding; A message buffer 9 for storing the message transmitted by the message buffer control means 8 so that the SSCS can read it; Completed message pointer first-in first-out means (10) for receiving a parameter and a pointer from the control buffer (5) and first-in first-out with a completed message pointer by the message buffer control means (8); Free list first-in, first-out means (11) connected to said message buffer control means (8) for storing each start address of said reassembly buffer (7); And a register 12 connected to the control buffer control means 6 and the message buffer control means 8 to transmit information on an operation mode, an operation state and an interrupt of each control block to an external microprocessor. An individual buffer type A. A. Type 5 common partial convergent sublayer receiver and reassembly circuit. The control buffer (5) according to claim 1, wherein the control buffer (5) is allocated with a 64-bit control area so that the upper three bytes are assigned the start address of the reassembly buffer (7) for the VCI, and the subsequent three bytes are the current VCI. The address of the reassembly buffer (7) to store the data, the last 2 bytes to allocate 10 bits for storing the timer value, and to record the information about the parameters and message assembly status transmitted from the ATM cell in the remaining 6 bits An AB type 5 common partial convergent sublayer receiver and reassembly circuit of an individual buffer type, characterized in that the configuration. 2. The reassembly buffer (7) according to claim 1, wherein the reassembly buffer (7) has an area capable of assembling 480 byte messages of up to 10 cells (assuming 480 bytes) as long as the maximum number of messages (k) that can be assembled at the same time. A.A.L of the individual buffer method, characterized in that configured to. (AAL) Type 5 common partial convergent sublayer receiver and reassembly circuit.