KR960009774A

KR960009774A - Clock fault detection circuit of all electronic switch

Info

Publication number: KR960009774A
Application number: KR1019940019402A
Authority: KR
Inventors: 오환규
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-08-06
Filing date: 1994-08-06
Publication date: 1996-03-22

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야; 전전자 교환기의 클럭 폴트 검출기술이다.1. the technical field to which the invention described in the claims belongs; It is a clock fault detection technology of an electronic switch.

2. 발명이 해결하려고 하는 기술적 과제; 고집적화가 용이한 클럭 폴트 검출회로를 제공함에 있다.2. The technical problem to be solved by the invention; The present invention provides a clock fault detection circuit that can be easily integrated.

3. 발명의 해결방법의 요지; 발명의 회로는 차례로 연결된 다수의 지연소자를 포함하며, 입력클럭이 제1레벨로서 미리 설정된 클럭구간동안 인가될시 제1폴트 신호를 제공하는 제1검출부와; 차례로 연결된 다수의 지연소자를 포함하며, 상기 입력클럭이 상기 제1레벨과 반대인 제2레벨로서 상기 미리 설정된 클럭 구간동안 인가될시 제2폴트신호를 제공하는 제2검출부와; 상기 제1, 2검출부의 제1, 2폴트신호를 게이팅하여 클럭 폴트신호를 발생하는 신호 발생부를 포함한다. 여기서, 상기 제1, 2검출부는 D타입 플립플롭 회로들로 구성되어 있으며, 상기 미리 설정된 클럭 구간은 상기 입력클럭을 소정 분주한 클럭으로서 사용하는 기준 클럭의 정수배 구간에 대응된다.3. Summary of the Solution of the Invention; The circuit of the invention comprises a plurality of delay elements connected in turn, the first detecting portion providing a first fault signal when an input clock is applied for a preset clock period as a first level; A second detecting unit including a plurality of delay elements connected in sequence and providing a second fault signal when the input clock is applied as the second level opposite to the first level during the preset clock period; And a signal generator for gating the first and second fault signals of the first and second detectors to generate a clock fault signal. Here, the first and second detectors are configured of D-type flip-flop circuits, and the preset clock period corresponds to an integer multiple of a reference clock using the input clock as a predetermined divided clock.

4. 발명의 중요한 용도; 교환 시스템의 클헉 감시용에 사용된다.4. Significant use of the invention; Used for clock monitoring of the exchange system.

※선택도: [제2도]※ Selectivity: [Figure 2]

Description

Clock fault detection circuit of all electronic switch

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 클럭 폴트 검출 회로도이다.2 is a clock fault detection circuit diagram of the present invention.

Claims

A circuit for detecting a fault of an input clock in an all-electronic exchange, comprising: A first detection unit including a plurality of delay elements connected in turn and providing a first fault signal whether the input clock is applied during a preset clock period as a first level; A second detecting unit including a plurality of delay elements connected in sequence and providing a second fault signal when the input clock is applied as the second level opposite to the first level during the preset clock period; And a signal generator for generating a clock float signal by gating the first and second fault signals of the first and second detectors.

The circuit of claim 1, wherein the delay element is configured of a D type flip-flop.

The circuit according to claim 2, wherein the predetermined clock section corresponds to an integer multiple section of a reference clock using the input clock as a predetermined divided clock.

2. The circuit of claim 1, wherein the signal generator comprises an ora gate for orating the first and second fault signals.

A digital circuit for detecting a fault state of an input clock in an electronic exchange, comprising: a plurality of flip-flop elements connected in turn, the first clock signal being provided as a high level to provide a first fault signal when applied for a preset clock period; First detecting means; A second detecting means including a plurality of flipple elements connected in turn and providing a second fault signal when the input clock is applied as the low level during the predetermined clock period; The first. And a fold signal generating means for generating a clock fault signal by ORing the first and second fault signal frames of the second detecting means.

※ Note: The disclosure is based on the initial application.