KR950009878B1 - DRAM with sense amplifier's own control circuit - Google Patents

Abstract

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Description

DRAM with sense amplifier's own control circuit

1 is a block diagram showing the configuration of a conventional DRAM.

2 is a circuit diagram of a conventional DRAM.

3 is an operation timing diagram of a conventional DRAM circuit.

4 is a block diagram showing the configuration of a DRAM according to the present invention.

5 is a sense amplifier enable circuit diagram of an embodiment according to the present invention;

6 is an operation timing diagram of FIG. 5 according to the present invention.

7 is a sense amplifier enable circuit diagram of another embodiment according to the present invention;

8 is an enable circuit diagram of another embodiment according to the present invention;

9 is an operation timing diagram of FIG. 8 according to the present invention.

* Explanation of symbols for main parts of the drawings

10: low decoder 20,20a to 20n: cell array

21: memory cell 30,30a to 30n: sense amplifier array

31: sense 40: low address buffer

50: delay circuit 60, 60a to 60n: sense amplifier enable circuit

61: logic circuit 62: precharge section

70: precharge circuit 71: precharge circuit

80a to 80n: dummy cell array 81: dummy cell

WL1 to WLn: word line BL, / BL: bit line

DBL: 1 dummy bit line F1 to F7: First to seventh field effect transistor

INV1 to INV3: Inverter NOR: NORGATE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM, and in particular, in determining an enable time of a sense amplifier, a self-control (sense control) to improve the processing speed of a DRAM and reduce a peak current. Relates to a DRAM having its own control circuit.

A conventional DRAM cell structure generally used is a memory cell composed of a plurality of memory cells connected to a plurality of word lines WL1 to WLn connected to a row decoder 10 to store information, as shown in FIG. A plurality of bit lines B1 (/ BL) to be connected to the array 20 and the respective memory cells, and to maintain a uniform level of voltage on the bit lines BL / BL. A precharge circuit 70 formed of a precharge circuit, a plurality of sense amplifier arrays 30 connected to the bit lines BL / BL to determine whether each memory cell has information, and an external low address buffer A delay circuit 50 for delaying the low address strobe (/ RAS) signal of (40) for a predetermined time and an enable circuit (60) for driving the sense amplifier array (30) by the signal of the delay circuit (50). It is composed.

FIG. 2 is a circuit diagram of a conventional DRAM. The memory cell 21 of the DRAM is composed of one MOS FET and one capacitor C. In order to determine whether or not information is contained in the capacitor C, FIG. The data of the memory cell 21 is read by the sense amplifier 31 connected to the pair of bit lines BL1 (/ BL1). Here, VBLP is a bit line precharge voltage, which is usually 1 / 2VCC.

The bit line equalizing signal is a signal that causes a pair of bit lines BL1 (/ BL1) to be equalized (equalized) to 1 / 2VCC.

In addition, BS denotes a block selection signal, and BL and / BL denote a pair of bit lines, and DATA and / DATA denote a pair of data selected by the selection signal.

The SN and SP are equalized by the sense amplifier equalization signal SEQ as a signal for enabling the bit line sense amplifier 31 indicated by the latch type.

SPC and SNC are the voltages responsible for the pull-up and pull-down of the sense amplifiers 31, respectively. The SPC and SNC are equalized to about 1/2 VCC by the sense amplifier equalizing signal (SEQ) and then applied to the enable (SP) signal. As a result, the pull-up signal SPC of the sense amplifier 31 changes to VCC, and the pull-down SNC of the sense amplifier 31 changes to VSS.

3 is an operation timing diagram of a conventional DRAM.

The operation of the conventional DRAM made as described above is performed when the external low address strobe signal (hereinafter referred to as “/ RAS”) is reduced from the VCC level to the VSS level as shown in the timing diagram of FIG. The address is latched by the internal circuit and the bit line equalization signal BEQ is slightly delayed than the / RAS signal to become VSS, so that the precharge circuit 71 is stopped, so that the equalization of the bit lines BL1 (/ BL1) is stopped. Therefore, it is separated from the bit line precharge voltage VBLP. At this time, the block selection signal BS is initially maintained at VCC and, in the case of the selected block, becomes VPP, which is a voltage level higher than VCC + Vth, and falls to the VSS level when not selected.

After that, the selected word line receives a low address and becomes the VPP level, and charge stored in one cell of the pair of bit line BL1 (/ BL) lines is applied, thereby causing a slight "high" or "low" level voltage. Will have

In this case, as the / RAS signal is delayed by the delay circuit 50 and then applied to the enable circuit 60, the enable signal SP SN of the sense amplifier 31 is “high” and “low” states, respectively. When the voltage difference is widened between VCC and VSS between a pair of bit lines BL1 (/ BL1), the data stored in the cell is transferred to the bit lines BL1 (/ BL1) to the data lines according to the selection signal. Delivered.

In the conventional DRAM as described above, the enable signal SP of the enable circuit 60 for controlling the sense amplifier array 30 is written with a circuit delayed by the delay circuit 50 from the / RAS signal. By delaying enough margin (WL) and bit line equalization (BEQ) signals to prevent malfunctions in preparation for process conditions, changes in external voltage levels, and poor operating conditions.

As a result, the speed reduction due to the margin is caused, and the enable signal SP of the enable circuit 60 is enabled at the same time for the sense amplifier array 3 of all the bit line sense amplifiers. The peak current caused by the large current flow increases, which may cause noise by the power line and reliability of the wiring line.

In order to solve the above problems, the present invention divides a plurality of memory cells and a plurality of sense amplifiers into a plurality of memory cell arrays and a sense amplifier array block, and enables the dummy cell and the sense amplifier between each memory cell array block. By adding a circuit, the enable circuit of each block is controlled by the delay of the word line and the dummy bit line, thereby improving the processing speed of the DRAM and reducing the peak current, thereby improving the reliability of the DRAM. SUMMARY OF THE INVENTION An object of the present invention is a DRAM having a sense amplifier circuit, comprising: a plurality of memory cell arrays in which a plurality of memory cells connected to a plurality of word lines are divided into predetermined unit blocks, and a bit line of each of the memory cell array blocks; A plurality of sense amplifier arrays connected to each other to detect the presence or absence of information stored in the memory cell; A plurality of enable circuits connected to each of the sense amplifier arrays to drive a sense amplifier array when one word line is selected from among a plurality of word lines, and an enable circuit connected between the plurality of memory cell array blocks to select a word line. The present invention provides a self-control circuit of a DRAM sense amplifier including a plurality of dummy cell arrays for controlling and enabling a sense amplifier automatically by signal delays of word lines and dummy bit lines.

Another object of the present invention is an enable circuit in which the first to third field effect transistors F1 to F3 are connected in series to control a sense amplifier, the OR gate and an inverter (INV1). A logic circuit 61 connected to the third field effect transistor F3 and the dummy cell bit line DBL to combine the signals of the sense amplifier equalizer signal SEQ and the dummy cell bit line DBL, and the dummy cell bit line. A fourth field effect transistor F4 and an output terminal of the logic circuit 61 which are connected to the fourth field effect transistor F4 for transmitting a signal of the dummy cell bit line DBL to the logic circuit 61 by a sense amplifier equalizer signal SEQ. The present invention provides a DRAM having its own enable circuit of a sense amplifier, in which a three field effect transistor F3 is connected and an inverter INV2 for inverting a signal applied to the first field effect transistor F1 is connected.

Hereinafter will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a DRAM having a self-control circuit of a sense amplifier according to the present invention. When the enable points of the plurality of sense amplifier arrays 30a to 30n are enabled, the word lines WL1 to WLn become “high” and the dummy cell. Signals are transmitted to the dummy bit lines DBL by the arrays 80a to 80n, and the enable signals are operated through the plurality of enable circuits 60a to 60n via the dummy bit lines DBL to sense amplifier arrays 30a. 30n), and the sense amplifier enable timing may be changed according to the delay of the word lines WL1 to WLn by dividing the sense amplifier arrays 30a to 30n of the memory cell arrays 20a to 20n into several. It was.

That is, when one of the plurality of word lines WL1 to WLn is selected in the row decoder 10, a slight delay occurs when the word line signal passes through each block of the plurality of memory cell arrays 20a to 20n. Whenever the word line signal passes through the dummy cell arrays 80a to 80n, the corresponding dummy cell is operated and the enable circuits 60a to 60n connected thereto operate to operate the sense amplifier arrays 30a to 30n. .

Therefore, the enable circuits 60a to 60n are driven by the natural natural signals generated in the word lines WL1 to WLn so that the multi-block sense amplifier arrays 30a to 30n are self-controlled in sequence to provide instantaneous peak current. Will be reduced.

FIG. 5 illustrates an embodiment of an enable circuit according to the present invention, which will be described in detail with reference to the timing diagram of FIG.

As shown in FIG. 6A, when the signal of the word line WL1 changes from the "low" level to the "high", the dummy cell 81 is turned on so that the dummy bit line DBL becomes the Vcc level as shown in d, and the block as shown in b. The block selected by the selection signal BS falls to the Vpp level, and the unselected block falls to Vss.

At this time, when the signal of the dummy bit line DBL becomes “high”, as shown in c, the bit line equalizer signal BEQ and the sense amplifier equalizer signal SEQ fall to the “low” level. The two enable signals SPC SNC become "high" and "low" as shown in e and f, and the voltage difference between the pair of bit lines BL // BL is increased to the level of Vcc and Vss.

That is, as shown in a and c, when the sense amplifier equalizer signal SEQ falls to the "low" level at the time when the word line WL1 becomes "high", the fourth field effect transistor F4 is turned off, and the dummy The "high" signal of the bit line DBL is inverted to "low" by the inverter INV1, which is the logic circuit 61, and applied to the NOR gate NOR.

In this case, when the NOR gate outputs a “high” signal in combination with the dummy bit line DBL signal to turn on the first and third field effect transistors F3, the second field effect transistor F2 is turned on. By turning off by the sense amplifier equalizer signal SEQ, the enable signal SPC becomes “high” and the other enable signal SPC becomes “low” to operate the sense amplifier 31.

FIG. 7 is another embodiment of the enable circuit according to the present invention. In contrast to FIG. 5, the other terminal connected to the dummy bit line DBL by the gate of the dummy cell 81 is Vcc. On the other hand, in FIG. 7, Vss is composed, and the logic change due to the polarity change is shown.

However, the precharge unit 62 allows the dummy bit line DBL to be completely precharged to Vcc regardless of the block selection signal BS.

That is, the dummy bit line precharge part 62 is connected to the sixth and seventh field effect transistors F6 and F7 which are PMOS, and the sixth and seventh field effect transistors F6 and F7 are connected in series. One side is connected to a separate dummy bit line DBL, and the other side is applied with Vcc, and the gate terminal of the sixth and seventh field effect transistors F6 and F7 is connected to the sense amplifier equalizer signal SEQ through the inverter INV3. ) Is authorized.

Referring to the operation of the other embodiment, when the sense equalizer signal SEQ goes “low” at the time when the word line WL1 becomes “high,” the precharge unit may be inverted to “high” by the inverter INV3. The sixth and seventh field effect transistors F6 and F7 of 62 are turned off to stop the precharge of the dummy bit line DBL, and the sense amplifier equalizer signal when the word line WL1 is not selected. SEQ is set to the "high" level, and is inverted to "low" by the inverter INV3 of the precharge unit 62, so that the sixth and seventh field effect transistors F6 and F7 are turned on to thereby be turned on. The dummy bit line DBL separated by the five field effect transistor F5 is precharged.

That is, the precharge unit 62 completely precharges the dummy bit line DBL regardless of the block selection signal BS.

FIG. 8 is a further embodiment of the enable circuit according to the present invention, which implements a small overlap current compared to FIGS. 5 and 7 and slowly turns the enable signal SPC SNC "high". And a circuit for increasing the noise margin of the sense amplifier 31 by making the transition to " low ".

In FIG. 8, VPV corresponds to Vcc of FIG. 5 and represents a voltage higher than the threshold voltage V _TN of the NMOS transistor.

The clock CLK signal is an additional control signal to reduce the current. The clock signal is "low" in the standby state, and is "high" before the signal enters the dummy bit line DBL. At this time, MN7 is for setting the dummy bit line DBL to the Vss voltage during standby, and the sense amplifier equalizer signal SEQ is the same signal as those in FIGS. 5 and 7.

9 shows the timing diagram of FIG.

That is, as shown in FIG. 9B, when the dummy bit line DBL becomes “high” by the word line WL1, the size of the dummy cell 81 is small, and thus a curve gradually increasing as shown in FIG.

At this time, MN3 and MN5 are turned on. First, the enable signal SN is increased by the degree of g by MN3, and at about the same time, the enable signal SP is gradually decreased by MN5.

Then, as the enable signal SP decreases, the MN2 is turned on to increase the enable signal SN more quickly. When the enable signal SN increases, the enable signal SP is increased more quickly by the MN6. Decrease.

Accordingly, the enable signal SP is latched into a “high” and a “low”, respectively. In this process, the enable signal SP has a double slope.

That is, when the enable signal SP (SN) has a double sloper (i.e., initially slowly and later later) such as g and h, and changes to "low" and "high" states, respectively, it is 1 / 2Vcc. The sense amplifier enable signal (SPC) (SNC), which is maintained, is changed to have a "high" and "low" with a double slope as shown in i.

Since the latch type bit line sense amplifier 31, which is usually used in DRAM, is required to gradually transition the enable signal SNC to “high” and “low” for the initial noise margin, the circuit It can be optimized for the purposes of the present invention.

As described above, the present invention provides a plurality of memory cell arrays 20a to 20n in which a plurality of memory cells 21 connected to a plurality of word lines WL1 to WLn are divided into predetermined unit blocks. A plurality of sense amplifier arrays 30a to 30n connected to bit lines BL (/ BL) of each of the memory cell arrays 20a to 20n to sense the presence or absence of information stored in the memory cells 21; A plurality of enable circuits 60a to 60n connected to each of the sense amplifier arrays 30a to 30n to drive the sense amplifier arrays 30a to 30n when one of the word lines WL1 to WLn is selected. A plurality of dummy cell arrays 80a to 80n connected between a plurality of memory cell arrays 20a to 20n blocks to control the enable circuits 60a to 60n when a word line is selected may include a plurality of memory cell arrays 20a to 20n. Bit automatically by enabling the sense amplifier automatically due to signal delay By enabling the line sense amplifier automatically by the delay of the word line and the bit line, the speed is improved compared to the conventional method of enabling the / RAS signal, and the word line delay is divided into several cells. It is possible to reduce the peak current when it is sequentially enabled by using the circuit, and also to enable the double signal as an enable signal when using a circuit that can reduce the expected overlap current since the dummy bit line gradually becomes “high”. There is an advantage.

Claims (2)

In a DRAM having a sense amplifier circuit, a plurality of memory cell arrays 20a to 20n in which a plurality of memory cells 21 connected to a plurality of word lines WL1 to WLn are divided into predetermined unit blocks; A plurality of sense amplifier arrays 30a to 30n connected to bit lines BL (/ BL) of each of the memory cell arrays 20a to 20n to sense the presence or absence of information stored in the memory cells 21; A plurality of enable circuits 60a to 60n connected to each of the sense amplifier arrays 30a to 30n to drive the sense amplifier arrays 30a to 30n when one of the word lines WL1 to WLn is selected; Word lines and dummy bit lines, including a plurality of dummy cell arrays 80a to 80n connected between the plurality of memory cell arrays 20a to 20n and controlling the enable circuits 60a to 60n when a word line is selected. Sense to enable the sense amplifier automatically by the signal delay of DRAM having a self-control circuit of the loop. In an enable circuit for controlling the sense amplifier by connecting the first to third field effect transistors F1 to F3 in series, the third field effect transistor F3 includes a NOR gate and an inverter INV1. And a logic circuit 61 coupled to the dummy cell bit line DBL to combine the signals of the sense amplifier equalizer signal SEQ and the dummy cell bit line DBL, and connected to the dummy cell bit line. A fourth field effect transistor F4 which transmits a signal of the dummy cell bit line DBL to the logic circuit 61 by a signal SE, and a third field effect transistor at an output terminal of the logic circuit 61. Having a sense amplifier enable circuit of a DRAM having F3 connected thereto and an inverter INV2 for inverting a signal applied to the first field effect transistor F1 connected thereto. DRAM.