KR940017441A - ATM adaptation layer receiver for fixed bit rate video service - Google Patents

Abstract

The present invention provides ATM Adaptation Layer (ATM) for providing fixed bit rate video service in ATM network among ATM (Asynchronous Transfer Mode) service recommended by CCITT, an international standard organization. The present invention relates to a video receiving apparatus in which a SAR header is searched and compensated for by a SAR sublayer for a fixed bit rate SAR-PDU transmitted to an ATM network, and FEC decoding is performed for a CS-PDU in a convergence sublayer to obtain pure video information. Because it transmits with video codec, it can be used for fixed bit rate video communication in ATM network. On the other hand, if the output connection is modified to connect with the audio codec, there is an advantage that can accommodate a high-quality voice service of a fixed bit rate.

Description

ATM adaptation layer receiver for fixed bit rate video service

Since this is an open matter, no full text was included.

1 is a schematic block diagram of an ATM adaptive layer receiving apparatus for fixed bit rate video service, FIG. 3 is a block diagram of a SAR header checking circuit, FIG. 4 is a block diagram of an image information compensation circuit, and FIG. Block diagram.

Claims (8)

Input / output signal generation means (1) driven according to the system clock provided from the network and receiving external buffer status signals and management signals, and input / output control signals from the input / output signal generation means (1) to the ATM layer. SAR header checking means (2) for receiving the SAR_PDU transmitted from and checking whether there is an abnormality of the SAR header, and an input / output control signal from the input / output signal generating circuit means (1) connected to the SAR header checking means (2). Is applied to output a recognition bit signal and compensates for abnormal SAR PDUs, and receives only valid SAR_PDU payloads from the image information compensation means 3 to output NRZ data and a reconstructed DS3 clock. And a fixed bit by receiving a converging layer layer restoring means 4 for restoring the CS_PDU, a recognition bit from the image information compensating means 3 and a network driving clock from the outside. Clock restoring means (5) for providing a DS3 restoring clock to the converging layer restoring circuit means (4) for receiving a video service, and receiving NRZ data and restoring DS3 clock from the converging part restoring means (4); And a video codec connecting means 6 for performing impedance matching and line coding when transmitting to the video codec, and management and status signal processing means 7 connected to an external control unit and outputting status signals and management signals. ATM adaptation layer video receiving apparatus, characterized in that. 2. The counting means (9) according to claim 1, wherein the input / output signal generating means (1) receives a system clock from a system clock circuit and receives a respective buffer status signal to drive a counter and the counting means (9). Decoding means 10 for receiving a counter output from the decoder and decoding, and input / output signal processing means 11 for receiving a decoding signal from the decoding means 10 to perform input / output signal processing. ATM adaptation layer video receiving apparatus. 2. The first buffering means (12) according to claim 1, wherein the SAR header checking means (2) receives an input / output control signal from the input / output signal generating means (1) and stores SAR_PDUs transmitted from an ATM layer, The input / output control signal is received from the input / output signal generating means 1 and the demultiplexing means 13 for separating the SAR header and the payload and the output signal from the demultiplexing means 13 are outputted a parity alarm. An error for receiving an input / output control signal from the parity bit checking means 14 and the input / output signal generating means 1 and an output signal from the parity checking means 14 to replace error detection and error correction. The input / output control signal is received from the detection / correction means (A) and the input / output signal generation means (1), and the payload discard signal from the error detection / correction means is received and stored. The second buffering means 18 receives the input / output control signal from the input / output signal generating means 1, and the output signal from the second buffering means 18 and the validity from the error detection / correction means A are effective. Multiplexing means 19 for multiplexing only SAR headers and payloads, and input / output control signals from the input / output signal generating means 1 and output signals from the multiplexing multiplexing means 19 to sort only the paid SAR_PDUs. And an effective SAR_PDU alignment resisting means (20). 2. The video information compensating means (3) according to claim 1, wherein the video information compensating means (3) comprises: buffering means (21) for storing valid SAR_PDUs from the SAR header checking means (2), and input / output control from the input / output signal generating means (1). A demultiplexing means 22 for receiving a signal and receiving and demultiplexing an output signal from the buffering means 21, and receiving an input / output control signal from the input / output signal generating means 1 and receiving the demultiplexing means ( A sequence number comparison means 23 for receiving an output signal from 22) and comparing a difference between neighboring sequence numbers; and an input / output control signal from the input / output signal generation means 1 and receiving the sequence number comparison means 23. Recognition bit synthesizing means 25 for synthesizing the recognition bits for clock recovery by receiving the status signal and the recognition information from and the input / output control signal from the input / output signal generating means 1 A reproduction signal generation means 24 for generating a reproduction signal by a difference of the sequence number from the sequence number comparison means 23, and an output signal from the reproduction signal generation means 24 and the inverse of the signal; A payload buffering means 28 for selecting an effective SAR_PDU payload input unit by receiving an output signal of the multiplexing means 27 for receiving and outputting the output from the multiplexing means 22, and the reproduction signal generating means 24; And a compensation buffering means (29) for receiving an output signal from the input signal and the output signal from the payload buffering means (28) and inputting the same to the multiplexing means. The method according to claim 1, wherein the converging unit layer restoring means (4) stores the payload compensated according to the input / output signal from the input / output signal generating means (1) in 128 rows to form 47 octets in a row to 128 octets. FEC decoding means for checking and outputting the code length of 128 octets from the octet deinterleaving means 30 in accordance with the input / output signal from the input / output signal generating means 1 and the octet deinterleaving means 30 for outputting each row. (31), restoring line determining means (32) connected to said FEC decoding means (31) for selecting image information output order in accordance with an input / output signal from said input / output signal generating means (1), and said restoring line determining means And serial-to-parallel buffering means (33) which are connected to (32) and serially convert and input 8-bit parallel data. 2. The clock driving means (6) according to claim 1, wherein the clock recovery means (6) receives a network driving clock and receives an output signal from the image information compensation means (3) and divides the frequency information generating means (34) and the network driving clock. A reference frequency generating means (35) for receiving a network driving clock frequency division information from the frequency division information generating means (34) and generating a reference frequency, and receiving a reference frequency from the reference frequency generating means (35). And PLL means 36 for detecting a phase difference between the frequency inputs and generating an output frequency, and a frequency divider 37 for receiving an output signal from the PLL means 36 and feeding it back to the PLL means 36. ATM adaptation layer video receiver. 2. The input / output driver 38 and the input / output driver 38 of claim 1, wherein the video codec connection means 6 receives NRZ data and a DS3 clock from the convergence layer reconstruction means 4; B3ZS / NRZ conversion means 39 for receiving the output signal NRZ data and the DS3 clock from B3ZS / NRZ conversion and the output signal from the B3ZS / NRZ conversion means 39 to perform impedance matching to the B3ZS signal. NRZ impedance matching means for impedance matching the output from the B3ZS impedance matching means 40 and the output from the input / output driver 38 to transmit the NRZ signal and the DS3 clock to the video codec. 41. An ATM adaptation layer video receiving apparatus, comprising: The data input / output driver (44) and the data input / output driver (44) for outputting management signal data connected to an external control unit. Management signal registration means 47 for receiving an output signal and outputting a management signal, a control signal input / output driver 45 connected to an external control unit and outputting an input control signal, and the control signal input / output driver 45. Control signal processing means (46) for applying an output control signal and providing an input signal to said management signal registration means (47), an address signal input driver (46) connected with an external control unit to output an address signal, and said address signal An address that receives an output signal from the input driver 46, applies a management signal decoding signal to the management signal registration means 47, and outputs a status signal decoding signal. And a status signal register means (48) for applying signal decoding status signal data to said data input / output driver (44). ※ Note: The disclosure is based on the initial application.