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KR930011000A - Ipyrom device - Google Patents

Ipyrom device Download PDF

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Publication number
KR930011000A
KR930011000A KR1019910021694A KR910021694A KR930011000A KR 930011000 A KR930011000 A KR 930011000A KR 1019910021694 A KR1019910021694 A KR 1019910021694A KR 910021694 A KR910021694 A KR 910021694A KR 930011000 A KR930011000 A KR 930011000A
Authority
KR
South Korea
Prior art keywords
voltage
memory cell
word lines
word
erased memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1019910021694A
Other languages
Korean (ko)
Inventor
김건수
서강덕
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910021694A priority Critical patent/KR930011000A/en
Priority to TW081108104A priority patent/TW219997B/zh
Priority to DE4237002A priority patent/DE4237002A1/de
Priority to FR9213412A priority patent/FR2684480A1/en
Priority to GB9224833A priority patent/GB2261971A/en
Priority to JP32014292A priority patent/JPH05225791A/en
Publication of KR930011000A publication Critical patent/KR930011000A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명의 이이피롬은 과도소거된 메모리셀이 존재하더라도 상기 과도 소거된 메모리셀의 워드라인에 그것의 드레쉬홀드전압보다 낮은 절대값을 가지는 워드라인전압을 인가할 수 있는 수단을 구비한다.The ypyrom of the present invention includes a means for applying a word line voltage having an absolute value lower than its threshold voltage to the word line of the over erased memory cell even if there is an over erased memory cell.

Description

이이피롬 장치Ipyrom device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 일실시예.2 is an embodiment according to the present invention.

제3도는 본 발명에 따른 다른 실시예.3 is another embodiment according to the present invention.

Claims (4)

하나의 트랜지스터로 이루어지고 과도소거된 메모리셀을 가지는 이이피롬 장치에 있어서, 상기 과도소거된 메모리셀에 연결된 비선택 워드라인에 상기 메모리셀의 드레쉬홀드전압보다 최소한 낮은 절대값을 가지는 전압을 공급하는 수단을 구비함을 특징으로 하는 이이피롬장치.In an EPROM device comprising a transistor and having an over erased memory cell, a voltage having an absolute value at least lower than the threshold voltage of the memory cell is supplied to an unselected word line connected to the over erased memory cell. Ipyrom device characterized in that it comprises a means for. 이이피롬장치에 있어서, 복수개의 워드라인들과, 상기 복수개의 워드라인들에 직교하여 배열된 복수개의 비트라인들과, 상기 복수개의 워드라인들과 비트라인들에 연결되고 하나의 셀트랜지스터로 이루어지며 최소한 하나 이상의 과도소거된 메모리셀들을 포함하는 복수개의 메모리셀들과, 상기 복수개의 워드라인들의 각각에 제1 또는 제2전압을 어드레스신호에 응답하여 선택적으로 공급하는 워드라인드라이버와, 상기 워드라인드라이버로 상기 제2전압을 공급하는 수단올 구비하며, 상기 제2전압이 상기 과도소거된 메모리셀의 드레쉬홀드전압보다 최소한 낮은 절대값을 가짐을 특징으로 하는 이이피롬장치.In the EPI device, a plurality of word lines, a plurality of bit lines arranged orthogonally to the plurality of word lines, and a plurality of word lines and bit lines connected to the plurality of word lines are formed of one cell transistor. A plurality of memory cells including at least one over-erased memory cell, a word line driver to selectively supply a first or second voltage to each of the plurality of word lines in response to an address signal, and the word Means for supplying the second voltage to a line driver, wherein the second voltage has an absolute value at least lower than the threshold voltage of the over-erased memory cell. 제2항에 있어서, 상기 제1전압이 상기 메모리셀을 턴온시키는 레벨에 있음을 특징으로 하는 이이피롬장치.4. The apparatus of claim 2, wherein the first voltage is at a level that turns on the memory cell. 이이피롬 장치에 있어서, 복수개의 워드라인들과, 상기 복수개의 워드라인들에 직교하여 배열된 복수개의 비트라인들과, 상기 복수개의 워드라인들과 비트라인들에 연결되고 하나의 셀트랜지스터로 이루어지며 최소한 하나 이상의 과도 소거된 메모리셀들을 포함하는 복수개의 메모리셀들과, 상기 복수개의 워드라인들의 각각에 제1 또는 제2전압을 어드레스신호에 응답하여 선택적으로 공급하는 워드라인 드라이버와, 상기 워드라인 드라이버로 상기 제2전압을 공급하는 수단을 구비하여, 상기 워드라인 드라이버로 상기 제2전압을 공급하는 수단을 구비하여, 상기 제2전압이 상기 과도소거된 메모리셀의 드레쉬홀드 전압보다 최소한 낮은 절대값을 가지며, 상기 수단이 상기 제1전압과 상기 제2전압을 전압원으로 사용하고 상기 어드레스신호에 응답하여 상기 제1전압 또는 제2전압을 출력하는 인버터를 구비함을 특징으로 하는 이이피롬장치.In an Epyrom device, a plurality of word lines, a plurality of bit lines arranged orthogonal to the plurality of word lines, a plurality of word lines and bit lines connected to the plurality of word transistors A plurality of memory cells including at least one over erased memory cell, a word line driver for selectively supplying a first or second voltage to each of the plurality of word lines in response to an address signal; Means for supplying said second voltage to a line driver, and means for supplying said second voltage to said wordline driver, wherein said second voltage is at least greater than the threshold voltage of said over erased memory cell. Has a low absolute value and said means uses said first voltage and said second voltage as voltage sources and responds to said address signal And an inverter for outputting the first voltage or the second voltage. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910021694A 1991-11-29 1991-11-29 Ipyrom device Abandoned KR930011000A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019910021694A KR930011000A (en) 1991-11-29 1991-11-29 Ipyrom device
TW081108104A TW219997B (en) 1991-11-29 1992-10-13
DE4237002A DE4237002A1 (en) 1991-11-29 1992-11-02
FR9213412A FR2684480A1 (en) 1991-11-29 1992-11-06 DELETE PROGRAMMABLE MEMORY DEVICE (EEPROM) ELECTRICALLY DELETED.
GB9224833A GB2261971A (en) 1991-11-29 1992-11-27 Electrically erasable programmable read only memory (EEPROM) device
JP32014292A JPH05225791A (en) 1991-11-29 1992-11-30 Electrically erasable programmable read- only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910021694A KR930011000A (en) 1991-11-29 1991-11-29 Ipyrom device

Publications (1)

Publication Number Publication Date
KR930011000A true KR930011000A (en) 1993-06-23

Family

ID=19323843

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910021694A Abandoned KR930011000A (en) 1991-11-29 1991-11-29 Ipyrom device

Country Status (6)

Country Link
JP (1) JPH05225791A (en)
KR (1) KR930011000A (en)
DE (1) DE4237002A1 (en)
FR (1) FR2684480A1 (en)
GB (1) GB2261971A (en)
TW (1) TW219997B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781977B1 (en) * 2006-11-02 2007-12-06 삼성전자주식회사 Decoder in nonvolatile memory device and decoding method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396459A (en) * 1992-02-24 1995-03-07 Sony Corporation Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line
US5581502A (en) * 1995-05-02 1996-12-03 Advanced Micro Devices, Inc. Method for reading a non-volatile memory array
JP2001085547A (en) * 1999-09-17 2001-03-30 Sony Corp Nonvolatile semiconductor memory device and reading method thereof
US8953380B1 (en) * 2013-12-02 2015-02-10 Cypress Semiconductor Corporation Systems, methods, and apparatus for memory cells with common source lines

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5619676A (en) * 1979-07-26 1981-02-24 Fujitsu Ltd Semiconductor device
US4451905A (en) * 1981-12-28 1984-05-29 Hughes Aircraft Company Electrically erasable programmable read-only memory cell having a single transistor
JPS6226697A (en) * 1985-07-26 1987-02-04 Hitachi Ltd Semiconductor memory
FR2599176A1 (en) * 1986-05-23 1987-11-27 Eurotechnique Sa MEMORY DEADLY PROGRAMMABLE ELECTRICALLY
DE3689475T2 (en) * 1986-06-27 1994-04-28 Nippon Electric Co Semiconductor memory system.
JPH0772996B2 (en) * 1987-01-31 1995-08-02 株式会社東芝 Non-volatile semiconductor memory
JPH0777078B2 (en) * 1987-01-31 1995-08-16 株式会社東芝 Non-volatile semiconductor memory
JP2507576B2 (en) * 1988-12-28 1996-06-12 株式会社東芝 Semiconductor non-volatile memory
EP0403822B1 (en) * 1989-06-19 1994-10-12 Texas Instruments Incorporated Circuit and method for conditioning erased eeproms prior to programming
US5222040A (en) * 1990-12-11 1993-06-22 Nexcom Technology, Inc. Single transistor eeprom memory cell
US5197027A (en) * 1991-01-24 1993-03-23 Nexcom Technology, Inc. Single transistor eeprom architecture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781977B1 (en) * 2006-11-02 2007-12-06 삼성전자주식회사 Decoder in nonvolatile memory device and decoding method thereof

Also Published As

Publication number Publication date
FR2684480A1 (en) 1993-06-04
GB9224833D0 (en) 1993-01-13
DE4237002A1 (en) 1993-06-03
TW219997B (en) 1994-02-01
GB2261971A (en) 1993-06-02
JPH05225791A (en) 1993-09-03

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Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19911129

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19911129

Comment text: Request for Examination of Application

PG1501 Laying open of application
PC1902 Submission of document of abandonment before decision of registration
SUBM Surrender of laid-open application requested