KR930008227Y1 - Current cell circuit - Google Patents

Abstract

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Description

Current cell circuit

1 is a block diagram of a current cell matrix type digital / analog conversion.

2 and 3 are conventional current cell circuit diagrams.

4 is a circuit diagram of a current cell of the present invention.

5 is another embodiment of the present invention.

6 is a circuit diagram of an LC filter formed between a coil and ground.

* Explanation of symbols for main parts of the drawings

1: X decoder 2: Y decoder

3: current cell unit 10: delay unit

NM ₁₁ -NM ₁₄ : NMOS R ₁₁ : Resistance

L ₁₁ : Coil

The present invention relates to a current cell circuit of a CMOS cell matrix system among high speed digital / analog conversion means, and more particularly to a current cell circuit adapted to eliminate glitches.

1 shows a block diagram of a current cell matrix type digital / analog converter, which adopts a thermometer coding scheme and generates an output current by turning on the number of current cells corresponding to the size of an input digital signal. In order to reduce the chip size and reduce the linearity error, the N-bit digital input is divided into two through the X and Y decoders (1, 2) and independently decoded. -OR-NOT) to add this to the logical configuration.

Meanwhile, FIGS. 2 and 3 show a conventional current cell circuit, and the operation thereof will be described below.

The output signals X, Y ₁ and Y _{2 of the} X and Y decoders ₁ and ₂ are NMOS ₁ and NM ₂ in the current cell circuit 3A in the current cell section 3. NM ₃ is inputted as a gate input signal, and when the input signals X and Y ₁ are simultaneously "high" or the input signal Y ₂ is "high", the NMOS ₁ NM ₂ ) is turned on or NMOS (NM ₃₎ is turned on, so this time, the NMOS (NM ₃₎ and a differential coupled NMOS (NM ₄₎ is off, so that flow through the NMOS (NM ₄₎ output current (I _OUT ) becomes 0 and the output voltage Vout becomes "high".

However, when at least one of the input signals X and Y ₁ is "low" and the input signal Y ₂ is "low", no current flows through the NMOSs NM ₁ and NM ₂ . (NM ₃₎ the current does not flow through this time, the NMOS (NM ₃₎ and a differential operation yen, and the moss (NM ₄₎ on which, and thus the NMOS (NM ₄₎ the output current through along (I _OUT) Flows to the output voltage Vout.

That is, the logical expression of the output current (I _OUT ) with respect to the input signals (X, Y ₁ , Y ₂ ) supplied to the gates of the NMOS ₁ -NM ₃ . Therefore, the logical expression V _OUT = X · Y ₁ + Y ₂ of the output voltage (V _OUT ) with respect to the input signals (X, Y ₁ , Y ₂ ).

Meanwhile, in FIG. 3, the input signals X and Y ₁ supplied from the X and Y decoders 1 and 2 are AND-combined in the AND gate AD ₁ , and then the OR gate OR again. ₁₎ as soon supplied to the gate of the signal (Y ₂₎ with the Iowa operation NMOS (NM ₆₎ inputted from the Y decoder (2) in addition, the inverter (I is the NMOS (NM ₆₎ with a differential via a ₁₎ Relation of output current (I _OUT ) with respect to input signal (X, Y ₁ , Y ₂ ) as it is supplied to gate of coupled NMOS ₅ Then, the relation V _OUT = X · Y ₁ + Y ₂ becomes a relational expression of the output voltage V _OUT with respect to the input signals X, Y ₁ , Y ₂ .

However, in the conventional current cell circuit, the former has a large cleat at the output terminal in the transient state of the input signal, and the latter has a large number of constituent elements of the unit current cell circuit, thereby increasing the size of the chip, resulting in linearity error. There was a drawback to increase.

The present invention was devised to reduce the size and glitches of a current cell at the same time to solve such a conventional drawback, which will be described in detail with reference to the accompanying drawings.

4 is a current cell circuit diagram of the present invention, as shown here, an NMOS 11 and Y driven by a signal X input from the X decoder 1 connected in parallel with each other to a power supply terminal V _DD . The NMOS 12 driven by the signal Y ₂ input from the decoder 2, and the input signals X and Y ₂ are supplied to the gates of the NMOS 11 and NM12, respectively. A delay unit 10 for delaying the output signal Y ₁ of the Y decoder 2 and an output signal of the NMOS 11 and NM12 through a drain, and the delay through a gate. NMOS13, which receives the output signal of the unit 10 and outputs the driving output according to the current source I _LSB , is biased by a predetermined voltage V _Bias and is differential from the NMOS13. It is composed of the NMOS (NM14) for outputting the voltage (V _OUT ) according to the lower surface, the operation and effects of the present invention configured as described above And it will be described in detail with reference to Figure 6 as follows.

Logic formula of this circuit Since the input signal (Y ₁ ) is "low" and the input signal (Y ₂ ) is not output as "high" due to the characteristic of the decoder (2) in the previous stage of the current cell, In the end, the existing logic becomes the same.

That is, the output signals X and Y ₁ and Y _{2 of the} X and Y decoders ₁ and ₂ are NMOS ₁₁ and NM in the current cell circuit 3A in the current cell unit 3. ₁₂ ), which is input to the gate input signal of (NM ₁₃ ), when the input signals (X) and (Y ₁ ) are simultaneously "high" or the input signal (Y ₂ ) is "high" (in this case, the input signal (Y) ₁ ) is also "high"), NMOS ₁₁ , NM ₁₃ is turned on or NMOS ₁₂ , NM ₁₃ is turned on, so at this time, NMOS ₁₁ , (NM ₁₃ ) or NMOS (NM) _12), (NM ₁₃₎ the current flows toward the current source (I _LSB) through which the NMOS (NM ₁₃₎ and a differential coupled NMOS (NM ₁₄₎ is turned off, via the NMOS (NM ₁₄₎ accordingly Since the output current I _OUT does not flow, the voltage Vout output at the drain connection point of the resistor R11 and its NMOS ₁₄ becomes "high".

However, if at least one of the input signals X and Y ₁ is " low ", the input signal Y ₂ is " low ", and the input signal Y ₂ is " low " Y ₁ ) is also " low ", since no current flows through the NMOS ₁₁ and NM ₁₃ and no current flows through the NM ₁₂ and NM ₁₃ , at this time, the NMOS ₁₄ is turned on. Accordingly, the output current I _OUT flows through the enmo NM ₁₄ , and the output voltage Vout becomes "low".

Here, the glitch generated in the analog output by the switching of the input signal (X, Y ₂ ) passes through the NMOS ( ₁₃ ) in the configuration of the circuit can significantly reduce the effect at the output terminal.

And after a predetermined delay unit 10 to couple the input signal (X), (Y ₂₎ to the input terminal, the input signal (Y ₁₎ the input signal (X, Y ₂₎ by causing the switching of the input signal (Y ₁₎ Can reduce the impact of.

In addition, as described above, in order for the NMOS NMOS ₁₃ and NM ₁₄ to operate differentially according to the input signals X and Y ₁ and Y ₂ , the NMOS ₁₄ A predetermined bias voltage (V _Bias ) is supplied to the gate of.

On the other hand, Figure 5 is another embodiment of the present invention for improving the glitch characteristics when explaining the operation thereof as follows.

By connecting NMO ₁₁ and NM ₁₂ in parallel and then connecting them in series with NMOS ₁₃ , the glitch flowing into NMOS ₁₁ and NM ₁₂ affects the output node. It is prevented primarily by the NMOS ₁₃ . The glitch flowing into the NMOS 13 is secondarily removed by an LC filter connected to the source of the NMOS 13, thereby suppressing the occurrence of current and voltage transients at the output node.

The LC filter is a coil L11 formed of a first metal layer that is repeated in a "c" shape and a "reverse c" shape, and a second metal layer formed of a panel structure and coupled to the first metal layer at a predetermined interval. It is made of a ground capacitor (C11), (C12) formed by.

Since the data processing speed of the video signal processing D / D converter is 50 MHZ or more, the clock frequency thereof becomes 50 MHZ or more, and the glitch frequency generated is 10 times or more of this, and the coil capacity of the LC filter is about 10- ^. Since it is about ¹ (nH), it can be sufficiently applied to a glitch removing filter.

As described in detail above, the present invention has the advantage of contributing to the miniaturization of the product by simplifying the configuration and reducing the glitch to give the user confidence.

Claims (1)

N-bit digital input is decoded through X, Y decoders (1) and (2), and the output signals (X) and (Y ₁ , Y ₂ ) of the X, Y decoders (1) and ( ₂ ) are calculated. The signal Y ₂ input from the NMOS 11 and the Y decoder 2 driven by the scene X input from the X decoder 1 connected in parallel to the power supply terminal V _DD in the current cell circuit. The output signal Y of the Y decoder 2 until the NMOS 12 driven by the N2 and the output signals X and Y ₂ are supplied to the gates of the NMOSs 11 and NM12, respectively. ₁ ) The delay unit 10 for delaying and the output signals of the NMOS 11 and NM12 are supplied to the drain, and the output signal of the delay unit 10 is supplied to the gate to supply the driving output to the current source ( The NMOS 13 outputted to I _LSB ) and the NMOS 14 supplied with a predetermined bias voltage and outputting the voltage V _OUT according to the differential operation with the NMOS ₁₃ are configured. Characterized by BRUSSELS circuit