KR930008058B1 - Circuit for correcting picture cell data on image scanner - Google Patents

Abstract

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Description

Pixel Correction Circuit of Image Scanner

1 is a schematic block diagram of an image processing system according to the prior art.

2 is a schematic block diagram of an image processing system employing a pixel correction circuit according to the present invention.

3 is a diagram showing pixel coordinate relationships in order to explain the principle of correction according to the present invention.

4 is a detailed circuit diagram of a pixel correction circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

1: CCD image sensor 2: Amplifier

3: sample / holder 4: analog-to-digital converter

5: image processor 10: pixel correction circuit

100: page memory 120: first line memory

140: second line memory 130, 302: inverter

200: first delay means 200: second delay means

300: comparison means 301: exclusive or gate

400: first latch means 420: second latch means

500: control unit 600: line counter

620: pixel counter 700: address generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel correction circuit of an image scanner, and more particularly, an image which converts an analog image signal scanned and output by a CCD image sensor into a digital signal and processes the image according to a desired use. A processing system, which relates to a circuit for correcting pixel information including an error due to characteristics and electrical noise of a CCD image sensor as an image input unit.

In general, image processing systems such as digital copiers, character recognition devices, and facsimiles include an image scanner as an input device for an image. In recent years, a charge transfer device (CDD) using a charge transfer method is widely used. have.

In this manner, a CCD having a function as an image pickup device may be used as a two-dimensional sensor such as a video camera, or used as a one-dimensional sensor in applications such as a facsimile.

FIG. 1 shows a general image processing system using a CCD image sensor. Briefly, the functions of the components of FIG. 1 will be described as follows.

The output of the CCD image sensor 1 which captures the optical image of the subject and converts it into an electrical analog signal is amplified once through the amplifier 2 because the amount of signal charge is generally small. Since the image information received by the CCD image sensor 1 is largely required for high speed processing, an amplifier (using a sample and holder 3 operated by a clock having a predetermined period) is used. Convert the continuous output of 2) into a discrete signal. The analog-to-digital converter 4 converts a discrete analog input signal (image information signal) into a binary, i.e., digital signal, and inputs it to an image processor 5 having an image processing function for a desired use.

However, due to its structural characteristics and operation method, the CCD includes a signal including noise caused by charge injection, noise caused by charge fluctuations in charge transfer, noise detected in charge, and electrical noise caused by variations in power supply voltage. Tends to output

In the image processing system shown in FIG. 1, the analog signal is digitalized using a comparator. Therefore, the analog voltage component is used as it is, so that it is very insensitive to the noise component. Since there is a disadvantage that can not eliminate the spot noise (spot noise) caused by the noise element.

Therefore, in the present invention, in order to solve the above-mentioned conventional problem, in the conventional image processing system, the pixel correction can remove the noise output from the CCD image sensor and the like by connecting to the rear end of the analog-digital converter. The purpose is to provide a circuit.

In order to achieve the above object, in the pixel correction circuit of the image scanner according to the present invention, in order to store the entire image data scanned by the CCD in a page memory and perform pixel correction on the stored data ( Image data is drawn out and stored in the first line memory for each horizontal and vertical component, and the pixel data to be corrected in the data in the first line memory and the pixel data positioned before and after the reference are Delay means is used to delay the pixel data to be corrected and the pixel data positioned before it at regular time intervals so as to be obtained at the same timing at the later stage.

In addition, by means of a comparison means including an exclusive-OR gate and an inverter, the pixel data to be corrected and the pixel data positioned before are compared with each other, and if two pixel data are identical, By latching the pixel data to be corrected in the first latching means, the pixel data to be corrected are written in the second line memory as a result of correction without change, while the two pixel data are different from each other. By latching the data next to the pixel data to be corrected in the second latching means, the pixel data at the next position is written into the second line memory instead of the pixel data to be corrected as the correction result value. . When all the pixel data of one line is corrected by this process, the data of the second line memory is rewritten to the page memory. In the above-described correction process, the pixel correction process in the horizontal direction is first performed on one page unit, that is, the entire pixel data, and then the pixel correction process in the second vertical direction is performed. Each pixel correction process is performed on a line-by-line basis, wherein the address setting for the line and the pixels in the line is in charge of the address generator according to the output of the pixel counter and the line counter that counts the clock output from the controller. have.

The following describes the present invention in more detail with reference to the embodiments shown in FIGS. 2 to 4.

FIG. 2 shows a schematic block diagram of an image processing system employing the pixel correction circuit 10 according to the present invention, the detailed circuit of which is shown in FIG.

3 is a diagram illustrating a pixel correction principle according to an embodiment of the present invention, where A represents a coordinate relationship corresponding to each pixel in a page memory that stores the entire image data that has undergone an analog-to-digital conversion process, and B represents a Represents a pixel value in memory corresponding to a coordinate. In the pixel correction process according to the present invention, the horizontal component pixels are firstly corrected with respect to the input digital image data, and then the vertical component pixels are secondly corrected with respect to the corrected image data of the horizontal component pixels.

Here, the correction process of the first horizontal component pixel is performed by the following algorithm.

P(i, j)=0Ph (i, j) = P (i, j), if P (i-1, j)

P (i, j) = 0

P(i, j)=1P (i + 1, j), if P (i-1, J)

P (i, j) = 1

In the above formula, P (i-1, j), P (i, j), and P (i + 1 j) represent pixel values adjacent to each other in the horizontal direction on the same j line (row). (i, j) is the pixel value to be corrected, P (i-1, j) is the pixel value at the previous position of P (i, j), and P (i + 1, j) is P (i, j) Indicates the pixel value at the next position. Ph (i, j) represents the result of horizontal correction for P (i, j) to be corrected.

As shown in the above equation, if the exclusive-OR logical value of P (i, j) and P (i-1, j) is "0", that is, P (i, j) and P (i If the values of -1 and j are equal to each other, the value of the original P (i, j) is held or latched as it is so as to be the correction result value Ph (i, j). And if the exclusive OR logical value of P (i, j) and P (i-1, j) is "1", that is, the values of P (i, j) and P (i-1, j) are different from each other. , The pixel value of P (i + 1, j) is substituted for the pixel value of P (i, j) so that the correction result value Ph (i, j) = P (i + 1, j).

Meanwhile, the correction process of the secondary vertical component pixels is performed by the following algorithm.

Ph(i, j)=0Pt (i, j) = Ph (i, j), if Ph (i, j-1)

Ph (i, j) = 0

Ph(i, j)=1Ph (i, j + 1), if Ph (i, j-1)

Ph (i, j) = 1

Ph(i, j)=0이면, 즉 Ph(i, j-1)과, Ph(i, j)의 값이 같으면, 원래의 Ph(i, j)의 값을 그대로 유지 또는 래치하여 보정결과 값 Pt(i, j)로 되게한다. 그리고 Ph(i, j-1)

Ph(i, j)=1이면 , 즉 Ph(i, j-1)과 Ph(i, j)의 값이 서로 다르면, Ph(i, j+1)의 화소값을 Ph(i, j)의 화소값에 대치시켜 보정결과 값 Ph(i, j)=Ph(i, j+1)로 되게 함으로써 최종적으로 수평 및 수직 방향에 있어서의 화소 보정이 완료된다.In the above formula, Ph (i, j-1), Ph (i, j), Ph (i, j + 1) are the first-corrected pixel values, which are perpendicular to each other on the same I-th column (column). Ph (i, j) is a pixel value for vertical component correction, Ph (i, j-1) is a pixel value at a previous position of Ph (i, j), and Ph (i, j). j + 1) represents a pixel value at the next position of Ph (i, j). Pt (i-1, j) shows the result of correction in the vertical direction with respect to Ph (i, j), which is the correction target. As you can see from the equation above, Ph (i, j-1)

If Ph (i, j) = 0, that is, if Ph (i, j-1) and Ph (i, j) have the same value, the original Ph (i, j) value is retained or latched as it is. Let it be the value Pt (i, j). And Ph (i, j-1)

If Ph (i, j) = 1, that is, if the values of Ph (i, j-1) and Ph (i, j) are different from each other, the pixel value of Ph (i, j + 1) is converted to Ph (i, j). The pixel correction in the horizontal and vertical directions is finally completed by substituting the correction result value Ph (i, j) = Ph (i, j + 1) in place of the pixel value of.

를 보내어 제 1 라인 메모리(120)를 기입모드로 설정함과 동시에 페이지 메모리(100)에는 읽기제어신호(R=1)를 보내어 페이지 메모리(100)를 독출모드로 설정한다. 이 상태에서, 제어부(500)는 수평축 성분에 대한 화소보정을 행하기 위해 라인 카운터(600)를 하나 증가시키고, 화소카운터(620)를 차례로 증가시키도록 되어 있다. 상기한 라인 카운터(600) 및 화소카운터(620)의 출력은 어드레스 발생부(700)에 인가되며, 이에 따라, 어드레스 발생부(700)는 제 1 라인 메모리(12)로 독출된 1라인 데이터의 어드레스를 페이지 메모리(100)에 인가하게 되며, 그 결과 인가된 어드레스의 값에 따라 페이지 메모리(100)는 제 1 라인 메모리(120)에 1라인 데이터를 내보내게 된다.4 shows a pixel correction circuit capable of performing pixel correction as described above. As described above, the circuit of the present invention is intended to correct an error due to the characteristics and electrical noise of the CCD image sensor generated in the process of converting an analog image signal into a digital signal. First, the digital data scanned by the CCD image sensor and subjected to the analog-to-digital conversion process is stored in the page memory 100. When the storage of all the image data is completed, the controller 500 writes a control signal to the first line memory 12 through the inverter 130.

The first line memory 120 is set to the write mode by sending a signal to the page memory 100, and the page memory 100 is set to the read mode by sending a read control signal R = 1. In this state, the control unit 500 is configured to increment the line counter 600 by one and to increment the pixel counter 620 in order to perform pixel correction on the horizontal axis component. The outputs of the line counter 600 and the pixel counter 620 are applied to the address generator 700, and accordingly, the address generator 700 is configured to read the one-line data read into the first line memory 12. The address is applied to the page memory 100, and as a result, the page memory 100 sends one line data to the first line memory 120 according to the value of the applied address.

Here, when the first line memory 120 enters the write mode, the second line memory 140 is set to the read mode but remains in the read mode until the page memory 100 is switched to the write mode. When this process is completed, the control unit 500 sends a read control signal R = 1 to the first line memory 120 so that three of the data stored in the first line memory 120 are read. The data is applied to the first input terminal of the exclusive or gate (hereinafter referred to as XOR) in the comparison means 300 in the comparison means 300 via the first delay means 200 and the second delay means 220. This second data is applied to the second input terminal of the XOR gate 301 via the first delay means 200 and also to the input terminal of the first latch means 400. In addition, the third read data is immediately applied to the input terminal of the second latch means 420. In this way, if the first and second data applied to the XOR gate 301 are equal to each other, it is considered that no error has been issued. In this case, an "0" output is generated at the XOR gate 301 and the second data is generated. Simultaneously with the latch means 420 disabled, the " 0 " output is inverted to " 1 " by the inverter 302 to enable the first latch means 400. As shown in FIG.

Accordingly, the second read data applied to the input terminal of the first latch means 400, that is, the pixel data to be corrected, is latched to the output terminal of the first latch means 400. On the other hand, when the first and second data applied to the XOR gate 31 are different from each other, this is regarded as an error, in which case an "1" output is generated at the XOR gate 301 to generate Enable the second latch means 420 so that the third data applied to its input end is latched to the output end of the second latch means 420, and the " 1 " output is " 0 " Inverted to disable the first latch means (400).

In this manner, the pixel data value output from the latch means selectively enabled among the first latch means 400 and the second latch means 420 is the same as that of the first line memory 120. It is stored in the two line memory 140. In this way, the correction is completed and the first line of data stored in the second line memory 140 is controlled by the controller 500 so that the second line memory 140 is in the read mode and the page memory 100 is switched to the write mode. In this state, the address generator 700 is written and stored in the address of the page memory 100 designated by the address generator 700.

After the above process, the controller 500 increases the value of the number of counters 620 to designate the next pixel, and then repeats the above-described pixel correction. This process is repeated until one line ends. Subsequently, after the correction for one line is finished, the controller 500 resets the pixel counter 62 and increments the line counter 600 to store the next one line in the first line memory 120. The process is repeatedly performed, and all pixel corrections on the horizontal axis are completed when the series of correction processes as described above are performed for the entire line.

Next, pixel correction is performed on the vertical component, which is performed in the same manner as the horizontal component.

However, the address generator 700 swaps the roles of the line counter 600 and the pixel counter 620 so as to store one line data in the vertical direction in the first line memory 120.

That is, the line counter 600 is used to address each vertical component pixel, and the pixel counter 602 is used to address the vertical component line.

In this way, the image data stored in the page memory after the pixel correction for the horizontal and vertical components is completed is the image data to be obtained immediately.

As described above, in the present invention, since the error is corrected by comparing the digitized pixel data with each other, more accurate error correction is possible, and even the point noise caused by the characteristics of the image can be completely eliminated. Because of the method, it exhibits strong characteristics against external noise.

Claims (3)

A page memory 100 storing the entire digital image data scanned by a CCD image sensor and subjected to an analog-to-digital conversion process, and extracting and storing pixel data of one line to be pixel corrected from the page memory 100. An input terminal of the comparison means 300, which is described later, by the second pixel data to be corrected and the first pixel data of the three pixel data extracted from the first line memory 120 of the first line memory 120 described later. First and second delay means (200, 220) for delaying the first and second pixel data at regular time intervals to be applied simultaneously to the first and second delay means (200). First latch means 400 for receiving two pixel data, and second latch means 4 for receiving third pixel data positioned next to the pixel data to be corrected drawn out from the first line memory 120. 20 and the first and second pixel data applied simultaneously from the first and second delay means 200 and 220, respectively, are compared, and when the two pixel data are the same, the first When the latch means 400 is enabled while the two pieces of pixel data are different from each other, the comparison means 300 enables the second latch means 420 and the comparison means 300 selectively selects the latch means 400. A second line memory 140 which receives pixel data output from the first latch means 400 or the second latch means 420 enabled to store the corrected pixel data, and counts the number of lines to be corrected. A line counter 600, a pixel counter 620 for counting the number of pixels on the one line to be corrected, and one line data to be read according to the output of the line counter 600 and the pixel counter 620. Er of the above page memory An address generator 700 for generating a dress and generating an address of pixel data read from the first line memory 120 and an address of corrected pixel data to be written to the second line memory 140; And a controller 500 for controlling the logical timing relationship and operation mode of all the pixel parts. The method of claim 1, wherein the setting of the write / read mode of the first line memory 120 and the second line memory 140 is performed by the inverter 130 according to the operation mode control output of the controller 500. Pixel correction circuitry of an image scanner, characterized in that configured to be opposite to each other. The method of claim 1, wherein the comparing means 300 performs an exclusive or logic for the first and second pixel data simultaneously applied from the first delay means 200 and the second delay means 220. The exclusive or gate 301 for applying the output to the enable terminal of the second latch means 420 and the input terminal of the inverter 302, and the exclusive or gate 301 And an inverter (302) for inverting the output and applying it to the enable terminal of the first latching means (400).

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