KR930008046B1 - Color converter in color graphic data - Google Patents

Abstract

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Description

Color conversion circuit of color graphic data

1 is a color conversion circuit diagram according to the present invention.

2 is a circuit diagram of one specific embodiment of the level controller of FIG.

* Explanation of symbols for main parts of the drawings

12: decoder 14: memory controller

16: first memory 18: color memory

20: color level controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for converting colors of graphics in a system for performing graphics processing, and more particularly to a circuit for converting a color of a CD (Compact Disk) graphic by a user's selection.

The current compact disk (CD) uses audio and sub-codes not used in the voice to provide the visual effects of subtitles, lyrics, and scores by listening and providing only graphical information. It is evolving to add.

Conventional CDP (Compact Disk Player) for processing such graphic information is to output the color graphics data loaded into the memory from the CD to a display device such as a monitor.

Therefore, in the conventional CDP, only the color graphics provided by the CD itself are seen, and thus cannot be viewed according to the user's perspective. Accordingly, the present invention provides a circuit for changing a color of graphic information provided from a CD on which color graphic information is recorded, by a user's operation.

Another object of the present invention is to provide a color level controller for varying color data of color graphics.

Hereinafter, the accompanying drawings of the present invention will be described in detail.

1 is a color conversion circuit diagram of a CD-graphics according to the present invention. An encoder 12 which decodes color graphic information coded and recorded on a CD and outputs R, G, B, color graphic data and control data is shown. And a first memory 16 which stores color selection data stored in a predetermined address area and outputs color selection data stored by a predetermined control, and the first control device according to graphic control information output from the decoder 12. A memory controller 14 controlling the memory 16, and R, G, and B color graphic data output from the decoder 12, and loaded by the output control of the first memory 16; A color memory (Color Memory; Color Look up table) 18, which outputs G, B color data, and R, G, B color data output from the color memory 18, respectively; , The second control signal (U / And a color level converter 20 which variably outputs each of the R, G, and B color data inputted by (CLK).

At this time, the color level converter 20 has the highest level and the lowest level, respectively, and inputs one color data among R, G, and B color data output from the color memory 18, and then the first and second colors. Control signal (W / R, G, and B level controllers 22, 24, and 26 for variable output by (CLK) or selecting and outputting the set highest or lowest level data.

FIG. 2 is a detailed view of the R level controller 22 in the level controller 20 of FIG. 1, where the first control signal U / ; UP / A counter 46 for outputting a sign bit and counting data by up / down counting an input of a second control signal CLK according to an input state of An adder 48 that adds data and counting data of the counter 46 and outputs a carry bit and added variable color data according to the result, and a set highest value MAX and a lowest value MIN. Multi-data inputting each data of the < RTI ID = 0.0 >)< / RTI > and the variable color data of the adder 48, and selecting and outputting one of the input data by the logic of the sign bit of the counter 46 and the carry bit of the adder 48. It is composed of a multiplexer (hereinafter referred to as MUX), and the same configuration as that of the second diagram is equally applied to the B and G level controllers 24 and 26.

The counter 46 in the configuration of FIG. 2 counts two's complement values each time the clock is input as an UP's 2'S Complement Counter.

In the present invention, an example of a two's complement up / down counter will be described, but it can be configured using a normal binary N bit up / down count.

The first control signal U / in the above-described configuration of FIGS. ) Is an up / down control signal having a logic "1" or "0", and the second control signal CLK is a clock pulse having a predetermined period, and these signals are generated by decoding a key signal selected by a user. It can be produced in a simple configuration from the outside.

An operation example of the present invention will now be described with reference to FIGS. 1 and 2.

If R, G, B color data of a fixed graphic for one screen from the decoder 12 is now output to the line 30, its R, G, B color data is sequentially written to the color memory 18. : loading).

After the R, G, and B data for one screen is loaded into the color memory 18 as described above, when control information for one screen is output from the decoder 12 to the line 28, the memory controller 14 reads the above. The first memory 16 is controlled according to the control information of the line 28. At this time, the control information output from the decoder 12 to the line 28 is screen control information such as a screen scroll.

The first memory 16 provides color selection data recorded in an internal predetermined area to an address of the color memory 18 under the control of the memory controller 14.

Accordingly, the color memory 18 outputs R, G, and B color data according to the color selection data output from the first memory 16, which is output through the respective output lines 34, 36, and 38. It is input to each of the R, G and B level controllers 22, 24 and 26 in the level controller 20.

At this time, the color level controller 20 for inputting the R, G, and B color data output from the color memory 18 receives first, second and third control signals U /. (CKK) (CLR) is input, and the first, second and third control signals U / The color level of the R, G, and B color data inputted by (CLK) (CLR) is adjusted.

In the above, the first, second and third control signals U / (CLK) (CLR) is generated by decoding an input of a key signal by a user's manipulation, and the decoded signal of such a key signal can be easily implemented by those skilled in the art. have.

The operation of each of the R, G and B level controllers 22, 24 and 26 in the color level controller 20 is a first control signal (U /). Is a logic " high ", and when the second control signal CLK is inputted as a clock pulse having a predetermined period, the input color data value is increased and outputted to the lines 40, 42, 44. If the first control signal U / D is the register "0", the value of the color data to be input is reduced and output.

Therefore, the color level controller 20 adjusts the R, G, B color data values inputted by the first, second, and third control signals U / D (CLK) and CLR by the user's key operation. Done.

An operation example of the color controller 20 of FIG. 1 will be described in more detail with reference to FIG.

When 4-bit R data is output from the color memory 18 to the line 34, it is input to the first input line 48a of the adder 48. At this time, the color variable data output from the counter 46 is input to the second input line 48b of the adder 48.

As described above, the counter 48 is an up / down 2's complement counter, which decodes a key input signal and inputs the first, second, and third control signals (U /). Outputs control data by (CLK) (CLR).

For example, the first control signal U / ) Up to the clock pulse of the second control signal (CLK) to be input to the logic "1" to add the sign bit (bit) and 4-bit data (Data) of the adder 48 and the MUX (50) Input to select terminal S2. In contrast to the above, when the first control signal U / D is a logic '0', the input clock is down counted to decelerate the output. Accordingly, the adder 48 performs a first input line 48a and a second input line 48b. 4 bits of R data and 4 bits of counting data are added to output the variable R data and the carry to the output line 48c.

The 4-bit R data output from the adder 48 is input to the data input terminals D0 to D3 of the MUX 50, and the carry bit is input to the select terminal S1. At this time, the MUX 50 inputs another 4-bit top level data and the lowest data to the data input terminals DA and DB, and the data input terminals D0 to D3 (DA) and (DB). One of the data input to is selected and output as shown in Table 1 according to the logic of the carry bit and the sign bit input to the select terminals S1 to S2.

TABLE 1

The data input to the data input terminals DA and DB of the MUX 50 are the maximum level value MAX and the minimum level value MIN of the R color and are used for the highest level and the lowest level clipping of the R color. will be.

Therefore, the MUX 50 outputs the variable color data output from the adder 48 by the carry bits output from the adder 48 and the sine bits output from the counter 46, and the set maximum level value MAX and minimum level value. One of the (MIN) is selected and output to the DAC (Digital to Analog Converter) (not shown) through the output line 46.

As described in FIG. 2, the G level controller 24 and the B level controller 26 in the color level controller 20 of FIG. 1 operate in the same manner, thereby outputting R, G, and B output from the color memory 18. FIG. Each color data is varied according to the user's key operation as described above and is inputted through the respective output lines 42 and 44 to the DAC connected thereto.

The DACs connected to the output lines 40 to 44 of the color level controller 20 convert the variable R, G, and B color data into analog signals. The outputs of the DACs are input to conventional R, G, and B encoders, encoded, and displayed on a monitor. By the above operation, the specific color can be emphasized from the fixed graphic color according to the user's operation, or the color can be adjusted to the user's preference.

As described above, the present invention has an advantage that the visual effect of the graphic can be further increased by converting the graphic color by the user's manipulation of the color loaded and fixed per screen in the CD graphic.

Claims (3)

In the color conversion circuit of color graphic data having an encoder 12 for decoding color graphic information coded and recorded on a CD and outputting R, G, and B color graphic data and control data, the color selection data is a predetermined address. A memory controller for controlling the first memory 16 according to graphic control information output from the decoder 12 and a first memory 16 stored in an area and outputting color selection data stored by a predetermined control; 14 and a color memory for storing R, G, B color graphic data output from the decoder 12 and outputting the stored R, G, B color data by output control of the first memory 16 ( 18) and R, G, and B color data outputted from the color memory 18, respectively, and inputted by the first and second control signals (U / D) (CLK) signals, respectively. R, G, B Cala de And a color level converter (20) for varyingly outputting data. The color level converter (20) is configured with the highest level and the lowest level, respectively, and inputs one color data of R, G, and B color data output from the color memory (18). 1, consisting of R, G, B level controllers 22, 24, 26 for variable output by second control signal W / D CLK or for selecting and outputting the set highest or lowest level data. And a color conversion circuit for color graphic data. 3. The R, G and B level controllers 22, 24 and 26 each up / down the input of the second control signal CLK according to the input state of the first control signal U / D. The counter 46 adds down counting and outputs a sine bit and counting data, and the color data output from the color memory 18 and the counting data of the counter 46 are added, and a carry bit and a variable color added according to the result are added. An adder 48 for outputting data, input data of the set maximum value MAX and the lowest value MIN, and variable color data of the adder 48, and a sine bit and an adder of the counter 46; And a multiplexer (50) for selecting and outputting one of the input data by the carry bit logic of (48).