KR930007567B1 - Multiinput decoder circuit - Google Patents

Abstract

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Description

Multi input decoder circuit

1 is a conventional decoder circuit diagram.

2 is a simplified diagram using the gate of FIG. 1 as a NAND gate.

3 is a simplified diagram using the gate of FIG. 1 as a noble gate.

4 is a multi-input decoder circuit diagram of the present invention.

FIG. 5 is a circuit diagram of the gate of FIG. 4 composed of NAND gates. FIG.

6 is a circuit diagram in which the gate of FIG. 4 is composed of a noble gate.

* Explanation of symbols for main parts of the drawings

I ₁ -I _N : Inverter gate G ₁ , G ₂ : Gate

NM ₁ -NM _N : _N -most transistor PM ₁ -PM _N : P-most transistor

The present invention relates to a multi-input decoder using a NAND gate or a no-gate. In particular, the number of transistors configured in series in the NAND gate and the no-gate can be reduced to reduce the layout area of the chip and reduce the circuit delay time. To one multi-input decoder circuit.

The conventional decoder circuit includes N inverter gates I ₁ -I _{N for} inverting _N input signals A ₂ -A _N , respectively, as shown in FIG. N gates (G _1- ) to obtain N decoder outputs (OUT ₁ -OUT ₂ ) according to the inverted signal (A ₁ -A _N ) and the input signal (A ₁ -A _N ) from ₁ -I _N ). Is a NAND gate circuit diagram in which one gate of G _N is connected in series with an _N-most transistor (NM ₁ -NM _N ), and FIG. 3 shows a gate of one of the gates (G ₁ -G _N ) of FIG. This diagram shows a no-gate circuit composed of MOS transistors (PM ₁ -PM _N ) connected in series. Where P1 is a pull-up circuit and P2 is a pull-down circuit.

The operation of the conventional decoder system configured as described above and the problems thereof will be described as follows.

로 반전되어 게이트(G_N)에 인가되고, 또한 게이트(G_N-1)에는 입력신호(A₁)와 인버터게이트(I₂-I_N)로부터 반전된 신호

가 인가되고, 게이트(G₂)에는 인버터게이트(I₁)의 반전신호

와 입력신호(A₂-A_N)가 인가되며, 게이트(G₁)에는 하이(H) 레벨인 입력신호(A₁-A_N)가 된다. 따라서, 이때 각 게이트(G₁-G_N)를 제2도와 같이 엔-모스트랜지스터(NM₁-NM_N)로 구성하여 낸드게이트로 사용할시 입력신호(A₁-A_N)가 모두 하이(H)신호인 경우 게이트(G₁)의 출력신호(OUT₁)만 저전위신호로 출력되고, 그이외의 게이트(G₂-G_N) 출력신호(OUT₂-OUT2^N)은 모두 고전위신호로 출력된다. 즉, 제2도와 같이 직렬연결된 엔-모스트랜지스터(NM₁-NM_N)에 하이신호인 입력신호(A₁-A_N)가 인가되면 그 엔-모스트랜지스터(NM₁-NM_N)가 모두 턴-온되어 풀업회로(P1)로부터 출력된 신호레벨이 접지로 바이패스되고, 이에따라 출력신호(OUT₁)는 저전위신호가 된다. 또한 입력신호(A₁-A_N)가 모두 저전위신호인 경우에는 게이트(GN)의 엔-모스트랜지스터(NM₁-NM_N)가 모두 턴-온되어 출력신호(OUT₂)만이 고전위신호가 된다. 즉 엔모스 트랜지스터(NM₁-NM_N)의 입력에 하나라도 저전위신호가 인가되면 게이트(G₁-G_N)의 출력은 하이가 되고, 전부 하이신호가 인가될 경우에만 게이트(G₁-G_N)의 출력이 로우가 된다.When the input signals A ₁ -A _N are all high (H), the input signals A ₁ -A _N are low through the inverter gates I ₁ -I _N.

Is inverted by the gate (G _N) is applied, and a gate (G _N-1) from the inverted input signal (A ₁₎ and inverter gate (I ₂ -I _N) to the signal

Is applied, and the inverted signal of the inverter gate I ₁ is applied to the gate G ₂ .

And an input signal A ₂ -A _N are applied, and the gate G ₁ is an input signal A ₁ -A _N having a high (H) level. Therefore, in this case, when the gates G ₁ -G _N are configured as the _N- gate transistors NM ₁ -NM _N as shown in FIG. 2, the input signals A ₁ -A _N are all high (H). ) into an output signal (OUT ₁₎ is only output to a low potential signal, the other gate (G ₂ -G _N) output signal (OUT ₂ -OUT2 ^N), all the high potential signal of the signal when the gate (G ₁₎ Is output. That is, when the input signals A ₁ -A _N , which are high signals, are applied to the _N -MOS transistors NM ₁ -NM _N connected in series as shown in FIG. 2, all of the _N -MOS transistors NM ₁ -NM _N are turned on. The signal level output from the pull-up circuit P1 being turned on is bypassed to ground, whereby the output signal OUT ₁ becomes a low potential signal. In addition, when the input signals A ₁ -A _N are all low potential signals, all of the _N -most transistors NM ₁ -NM _N of the gate GN are turned on so that only the output signal OUT ₂ is a high potential signal. Becomes I.e., NMOS transistor to an input of any of (NM ₁ -NM _N) when applied with the low potential signal gate (G ₁ -G _N) output only when the gate is applied is high, all of the high signal (G ₁ of the - G _N ) output goes low.

On the contrary, when the gates G ₁ -G _N are configured in the P-most transistors PM ₁ -PM _{N as} shown in FIG. 3 and used as the noble gate, the input signals A ₁ -A _N are all low-potential signals. If the gate (G _N) output (OUT ₂ ^N) only to be a high potential signal, the gate of the other (G ₁ -G _N-1) output signals ^{_{(OUT 1 -OUT 2 N-1}} ) are both low potential of It becomes a signal.

That is, when the low-potential input signals A ₁ -A _N are applied to the P-MOS transistors PM ₁ -PM _N connected in series as shown in FIG. 3, all of the P-MOS transistors PM ₁ -PM _N are applied. Turned on, the output signal OUT ₂ ^N becomes a high potential signal.

However, when a NAND gate or a NOR gate is used in such a conventional decoder, when the input signal of each gate is applied to 2 ^N-1 gates and the number of input signals (N) is large, the input of each gate is pulled up of the NOA gate. It is connected to 2 ^N-1 pull ^- down transistors except when connected to a circuit, and is connected to 2 ^N-1 pull ^- up transistors except when connected to a pull-down circuit of a NAND gate. This causes a problem of increasing the delay time of the decoder.

In view of such a conventional problem, the present invention reduces chip layout and delay time by reducing the number of N- and MOS transistors connected in series in a multi-input decoder circuit using NAND or NOA gates. Invented to shorten this, it will be described in detail with reference to the accompanying drawings as follows.

4 is a decoder circuit diagram of the present invention. As shown in FIG. 4, N inverter gates I ₁ -I _{N for} inverting _N input signals A ₁ -A _N and the inverter gates I ₁ -I, respectively. ₄₎ the signals (a ₁ -A _N-1) and input signals (a ₁ -A _N), the gate (G to obtain the 2 ^N-1 of the decoder output ^{_{(OUT 1 -OUT 2 N-1}} ) according to the inversion from ₁₎ and the mouth neoteo gates (I ₁ -I _N) of signal (a ₁ -A _N) and reverse from the input signals (a ₁ -A ^_N) 2 _N of the decoder output (OUT2 ^N-1 + ¹ ~ according to the It is configured as a gate G ₂ for obtaining OUT ₂ ^N ).

가 인가되는 엔-모스트랜지스터(NM₁')는 상기 엔-모스트랜지스터(NM₂-NM_N)와 직렬연결하여 출력신호(OUT₂)를 얻고, 입력신호(A₁)가 인가되는 엔-모스트랜지스터(NM₂')를 반전신호

가 인가되는 엔-모스트랜지스터(NM₁")와 직렬연결한 후 다시 상기 엔-모스트랜지스터(NM₃-NM_N)와 직렬 연결하여 출력신호(OUT₃)를 얻으며, 또한 반전신호

가 인가되는 엔-모스트랜지스터)NM₃')를 반전신호

가 인가되는 상기 엔-모스트랜지스터(NM₁")와 직렬연결한 후 다시 직렬 연결하여 출력신호(OUT₄)를 얻는다. 이와같은 방법으로 엔-모스트랜지스터(NM₄'-NM_N')(NM₂"-NM_N")를 순차적으로 직렬 연결하여 출력(OUT₂ ^N-2-2~OUT₂ ^N-1)을 얻도록 구성한다.FIG. 5 is a NAND gate circuit diagram in which gates G ₁ and G _{2 of} FIG. 4 are sequentially connected to an N-mode transistor, and as shown in FIG. ₅ , a plurality of N-mode transistors NM are included in the pull-up circuit PU ₁ . ₁ -NM _N ) is connected in series to obtain an output signal OUT ₁ between the pull-up circuit PU ₁ and the N-most transistor NM ₁ , and an inverted signal.

The N-most transistor NM ₁ ′ to which the N-most transistor is applied is connected in series with the _N-most transistors NM _{2 to} NM _N to obtain an output signal OUT ₂ , and the _N -MOS transistor to which the input signal A ₁ is applied. Invert signal of transistor (NM ₂ ')

Is connected in series with the n-most transistor (NM ₁ ″) to which N is applied, and then connected in series with the _N-most transistor (NM ₃ -NM _N ) to obtain an output signal (OUT ₃ ), and an inverted signal.

N-Mosistor) NM ₃ ') is applied

Is connected in series with the N-mode transistor NM ₁ ″ to which N is applied, and then connected in series to obtain an output signal OUT _4. In this manner, the N-mode transistor NM ₄ '-NM _N ' (NM Configure ₂ "-NM _N ") in sequence to obtain the output (OUT ₂ ^N-2 -2 ~ OUT ₂ ^N-1 ).

가 인가되는 피-모스트랜지스터(PM₁')는 상기 피-모스트랜지스터(PM₂-PM_N)와 순차적으로 직렬 연결하여 출력신호(OUT₂)를 얻고, 입력신호(A₁)가 인가되는 피-모스트랜지스터(PM₂')는 반전신호

가 인가되는 피-모스트랜지스터(PM₁")와 직렬연결한 후 다시 상기 피-모스트랜지스터(PM₃-PM_N)와 직렬 연결하여 출력 출력신호(OUT₃)를 얻도록 구성하고, 이와같은 방법으로 피-모스트랜지스터(PM₃'-PM_N')(PM₂"-PM_N")를 순차적으로 직렬 연결하여 출력(OUT₄-OUT₂ ^N-1)을 얻도록 구성한다.FIG. 6 is a no-gate circuit diagram formed by sequentially connecting gates G ₁ and G _{2 of} FIG. 4 to a P-MOS transistor, and as shown therein, a plurality of P-MOS transistors PM _{1 in the} pull-down circuit PD ₁ . ₁ -PM _N ) is connected in series to obtain the output signal OUT ₁ between the pull-down circuit PD ₁ and the P-MOS transistor PM ₁ , and the inverted signal.

The P-most transistors PM ₁ ′ to which P is applied are sequentially connected to the P-most transistors PM _{2 to} PM _N to obtain an output signal OUT ₂ , and P to which the input signal A ₁ is applied. Most transistors (PM ₂ ') are inverted signals.

Is connected in series with the P-MOS transistor (PM ₁ ″) to which P is applied, and then connected in series with the P-MOS transistor (PM ₃ -PM _N ) to obtain an output output signal (OUT ₃ ). The P-MOS transistors (PM ₃ '-PM _N ') (PM ₂ "-PM _N ") are sequentially connected in series to obtain outputs (OUT ₄ -OUT ₂ ^N-1 ).

Here, PU ₁ -PU _N is a pull-up circuit, and PD ₁ -PD _N is a pull-down circuit.

Referring to the operation, effects of the present invention configured as described above in detail.

로 반전되어 게이트(G₂)에 인가됨과 아울러 입력신호

가 게이트(G₁)에 인가되고, 또한 입력신호(A₁-A_N)와 인버터게이트(I₁-I_N-1)로 부터 반전된 신호

가 게이트(G₁)로 인가하게 되는데, 이때 제5도와 같이 엔-모스트랜지스터로 구성하여 낸드게이트로 사용할시 입력신호(A₁-A_N)가 모두 하이(H)신호인 경우 게이트(G₁)의 출력신호(OUT₁)만 저전위신호로 출력되고, 그 이외의 게이트(G₁)(G₂)의 출력(OUT₂-OUT₂ ^N)은 모두 고전위신호가 된다. 즉, 제5도와 같이 직렬 연결된 엔-모스트랜지스터(NM₁-NM_N)에 고전위신호인 입력신호(A₁-A_N)가 인가되면 그 엔-모스트랜지스터(NM₁-NM_N)가 모두 턴-온되어 풀업회로(PU₁)로부터 출력된 신호레벨이 접지로 바이패스되고, 출력(OUT₁)는 저전위신호가 된다.As shown in FIG. 4, when the input signals A ₁ -A _N are all high potential signals, the input signals A ₁ -A _N are low through the inverter gates I ₁ -I _N.

Inverted to and applied to the gate (G ₂ ) and the input signal

Is applied to the gate G ₁ and is also inverted from the input signals A ₁ -A _N and the inverter gates I ₁ -I _N-1 .

Is applied to the gate G _1. At this time, when the input signals A _{1 to} A _N are all high (H) signals when the _N- gate transistor is used as the NAND gate as shown in FIG. 5, the gate G ₁ is applied to the gate G _1. Only the output signal OUT _{1 of} ) is output as the low potential signal, and the outputs OUT ₂ -OUT ₂ ^N of the gates G ₁ (G ₂ ) other than the above become high potential signals. That is, the fifth assist series connected yen As-MOS transistor (NM ₁ -NM _N) to a high potential when the input signals (A ₁ -A _N) signal applied to the en-MOS transistor (NM ₁ -NM _N) are all The signal level output from the pull-up circuit PU ₁ by being turned on is bypassed to ground, and the output OUT ₁ becomes a low potential signal.

가 인가되고, 이와 직렬 연결된 엔-모스트랜지스터(NM₂-NM_N)에 고전위신호인 입력신호(A₂-A_N)가 인가되면 엔-모스트랜지스터(NM₁-NM_N)는 모두 턴-온되나 엔-모스트랜지스터(NM₁')는 오프되므로 출력신호(OUT₂)는 고전위신호로 출력된다.In addition, the signal inverted from the inverter gate I ₁ to the N-most transistor NM ₁ ″.

Is applied and, on the other connected in series ene-MOS transistor (NM ₂ -NM _N) the high potential signal, the input signal (A ₂ -A _N) applied when the yen-MOS transistor (NM ₁ -NM _N) are all turned on, The output signal OUT ₂ is output as a high potential signal because it is on, but the N-most transistor NM ₁ ′ is off.

As such, when any low signal is applied to the input of the N-MOS transistor, the outputs OUT _{1 to} OUT ₂ ^N of the gates G ₁ and G ₂ are all low potential signals, and when all the high potential signals are applied. Only the output of gate G ₁ (G ₂ ) becomes low potential.

가 고전위로 되어, 그 출력신호

를 제6도와 같이 게이트에 인가받는 피모스 트랜지스터(PM₁'-PM₁"…)가 오프되므로 출력신호(OUT₂-OUT₂ ^N)는 고전위신호가 출력된다.On the contrary, as shown in FIG. 6, when the input signals A ₁ -A _N are all low-potential signals when the gates G ₁ (G ₂ ) are configured as P-most transistors and are used as noah gates, the P-most transistors PM ₁ -PM _N ) are all turned on so that only output signal OUT ₁ is output as a high potential signal, and all other output signals OUT ₂ -OUT ₂ ^{N become} low potential signals. That is, at this time, the output signal of the inverter gate (I ₁ -I _N ) for generating the input signal A ₁ -A _N

Becomes high potential and its output signal

Since PMOS transistors PM ₁ '-PM ₁ "... Which are applied to the gate are turned off as shown in FIG. 6, the high potential signals are output to the output signals OUT _{2 to} OUT ₂ ^N.

Similarly, when the input signals A ₂ -A _N are low potential signals and the input signals A ₁ are high potential signals, the PMOS transistors PM ₂ -PM _N and the PMOS transistors PM ₁ ′ are turned on. Therefore, only the output signal OUT2 is output as a high potential signal, and the other output signals OUT ₁ and OUT _{3 to} OUT ₂ ^N-1 are output as low potential signals.

As described in detail above, the present invention can reduce the layout area in a chip by using a small number of transistors, and also the gate input speeds up the gate driving speed by reducing the number of transistors in driving the transistors of the gate, The delay time of the decoder is shortened.

Claims (2)

Inverter gates I ₁ -I _N for inverting a plurality of input signals A ₁ -A _N , and inverting the input signals A ₁ -A _N and the inverter gates I ₁ -I _N-1 . Output signal

Receiving an input of an output signal (OUT ₁ -OUT ₂ ^N- ₁₎ decoding an output gate (G ₁₎ and said input signal (A ₁ -A _N-1) and the inverter gates (I ₁ -I _N) to a Inverted output signal

Is configured as a gate (G ₂ ) for receiving and decoding the output signal (OUT ₂ ^N-1 +1 ~ OUT ₂ ^N ), the gate (G ₁ , G ₂ ) is the input to the pull-up circuit (PU ₁ ) The _N mode transistors NM ₁ -NM _N , which receive signals A ₁ -A _N , are respectively connected to the gates in series, and the inverted output signal is connected to the pull-up circuit PU ₂ .

Is connected in series with the NMOS transistor NM ₁ ′ and the NMOS transistors NM ₁ -NM _N applied to a gate, and the input signal A ₁ and the inverted output signal are connected to a pull-up circuit PU ₃ .

Gates each receiving application NMOS transistor (NM ₂ ') to (NM _N ") and the NMOS transistor (NM ₃ -NM _N) and the series connection, in such a manner pull-up circuit (PU ₄ -PU _N) in yen And a NAND gate circuit configured to sequentially connect the MOS transistors and output the output signals (OUT _{1 to} OUT ₂ ^N- ₁ ) at their connection points. 2. The PMOS transistors PM ₁ -PM _N of claim 1, wherein the gates G ₁ and G ₂ respectively receive the input signals A ₁ -A _N from the pull-down circuit PD ₁ . The inverted output signal is connected in series to the pull-down circuit PD ₂ .

Is connected in series with the PMOS transistor PM ₁ ′ and PMOS transistor PM ₂ -PM _{N that} are applied to the gate, and the input signal A ₁ and the inverted output signal are connected to a pull-down circuit PD ₃ .

Is connected in series to the PMOS transistors PM ₂ ′ (PM ₁ ″) and the PMOS transistors PM ₃ -PM _{N that} are respectively applied to the gates, and to the pull-down circuit PD ₄ -PD _{N in} this manner. And a no-gate circuit configured to sequentially connect the MOS transistors so that the output signals (OUT _{1 to} OUT ₂ ^N-1 ) are output at their connection points.

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