KR920007079B1 - Encryption and Decryption Circuits of Digital Telephones - Google Patents

Abstract

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Description

Encryption and Decryption Circuits of Digital Telephones

1 is a specific circuit diagram of a transmitter according to the present invention.

2 is an operation timing diagram of FIG. 1 according to the present invention.

3 is a detailed circuit diagram of a receiver according to the present invention.

4 is an operation timing diagram of FIG. 3 in accordance with the present invention.

The present invention relates to an encryption and decryption circuit using a secretion method in a digital data transmission system.

The encryption part refers to a part for making the information secret, and the decryption part means a part for converting the encrypted information to the original information.

In general, data transmission through a facsimile is converted to an analog signal. This is encrypted by the encryption section of the analog sequencing unit of the transmitter and passes through the exchange. The signal through the exchange is converted into original information by the decryption unit of the receiver analog sequencing device and received by the facsimile. That is, the conventional telephone was an analog system because the conventional telephone was an analog system. However, as the development of digital telephones is activated, the necessity of digital telephones becomes clear.

Accordingly, an object of the present invention is to provide a circuit capable of transmitting a voice image and data information in a digital transmission system as well as a digital telephone communication network so as to encrypt the information appearing on a transmission channel so that a third party can securely prevent eavesdropping. have.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a detailed circuit diagram of an encryption in a transmitter according to the present invention. The 8-bit data input through the data bus 11 is transmitted from the load (LD) signal input through the enterprise control terminal 12 to the transmission clock stage 13. A first exclusion for exclusively ORing the first shift register 11 to generate key data by shifting the clock according to the clock of < RTI ID = 0.0 > and < / RTI > the message data input to the message stage 14 and the output data of the first shift register 11. The output data of the first exclusive oragate 13 is latched and output as channel data according to the signal of the sheave or gate 13 and the clock signal of the transmission clock stage 15 being inverted by the inverter N1. Is composed of a first flip-flop 14.

2 is an operational waveform diagram of FIG. 1 according to the present invention, FIG. 2a is a message data waveform diagram, FIG. 2b is an output data waveform of the first shift register 11, and FIG. 2c is a first exclusive oragate. An output data waveform of (13) is shown, FIG. 2d is a clock waveform of the transmission clock stage 15, and FIG. 2e is an output channel data waveform of the dip-flop 14.

3 is a detailed circuit diagram of the decryption of the receiver according to the present invention. The second deflip-flop which inverts the input clock of the receiver clock stage 32 in the inverter N1 to latch the input data of the channel stage 31. (33), a second shift register (34) for inputting the clock of the reception clock stage (32) and shifting data on the data bus (36) under the control of the write control stage (37); And a second exclusive orifice 35 which outputs a message by exclusively ORing the output data of the deflip-flop 33 and the output data of the second shift register 34.

FIG. 4 is an operational waveform diagram according to the present invention. FIG. 4a is a reception channel data waveform diagram, FIG. 4b is a reception clock waveform, FIG. 4c is an output data waveform of the second deflip-flop 33, and FIG. The output waveform of the two shift registers 34 is shown, and FIG. 4E is the received message data waveform.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 through 4, by using the write control signal of the write control stage 12 and the 8-bit data of the data bus 11. It is possible to set any key value 2b at (11).

Since the key value of the first shift register 11 is 8 bits, it has 2 ⁶ = 256 key values, and if it is 16 bits, it has about 64,000 key values. And the part which adds the said key value and the message data 2a of the message stage 14 is comprised by the exclusive oragate 13. That is, as shown in FIG. 2C.

The data transfer is generated in the second flip-flop 14 as shown in FIG. 2E by the transfer clock of FIG. 2D of the transmit clock stage 15. FIG.

That is, if the key data value is 10101010 as shown in FIG. 2B of the transmitter timing diagram of FIG. 2, the channel value of FIG. 2E when the message is 10110010 is shown as 00011000 according to the transmission clock as shown in FIG. 2A.

The reception is decrypted as shown in FIG. 3 to FIG. 4, in which the receiver receives the second deflip-flop 33 according to the clock of the reception clock stage 32. FIG. That is, the secreting information of FIG. 2E received through the channel stage 31 is synchronized with the clock of the receiving clock stage 4b. At this time, the output of the output terminal Q of the second flip-flop 33 is shifted by 1/2 of the reception clock as shown in FIG. 4C. At this time, the secreted information is 00011000.

Since the shift register value of the second shift register 34 is 10101010, the key and secret information have the same bit synchronization. The message detection output determines the value of the key and secret information at the second exclusive orifice 35. That is, when the secret information is 00011000 as shown in FIG. 4A and the key is 10101010 as shown in FIG. 4D, the message is 10110010 as shown in FIG. 4E.

Accordingly, when 10110010, which is the message of the transmitter, is set to 00011000, it is transmitted through the transmission channel. If eavesdropping occurs in the middle of the channel, the information is so different that the exact message cannot be found. Therefore, it can be seen that the intended secret is made.

As described above, in the digital transmission system, the information appearing on the transmission channel when transmitting and receiving voice, image, and data information is encrypted to prevent the third party from eavesdropping.

Claims (1)

In the encryption and decryption circuit of the digital telephone, 8-bit data input through the data bus 11 is transferred from the load (LD) signal input through the write control stage 12 to the clock of the transmission clock stage 15. A first exclusive oragate that exclusively ORs the first shift register 11 to generate key data by shifting accordingly, the message data input to the message stage 14, and the output data of the first shift register 11; (13) and a first latching output data of the first exclusive oragate 13 in accordance with a signal inverted by the inverter clock signal of the transmission clock stage 15 and outputting the channel data. A second flip-flop (33) for inverting the flip-flop (14), the input clock of the receiving clock stage (32) at the inverter (N1), and latching the input data of the channel stage (31), and the receiving clock stage. The clock of the (32) is input, and the company control stage (37) The second shift register 34 shifting the data on the data bus 36, the output data of the second flip-flop 33, and the output data of the second shift register 34 are exclusively ORed. And a second exclusive oragate (35) for outputting message data.

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