KR920005008B1 - Transmission mediation circuit of signal terminal controller - Google Patents

Abstract

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Description

Transmission mediation circuit of signal terminal controller

1 is a block diagram of a signal terminal control apparatus in a common line signal apparatus signal terminal group to which the present invention is applied.

2 is a block diagram of a signal terminal bus matching unit of FIG. 1 to which the present invention is applied.

3 is a block diagram showing a configuration of the present invention.

* Explanation of symbols for main parts of the drawings

11 level 1 polymerization part 12 protocol processing part

13: signal terminal bus matching unit 14: signal terminal control device

15: signal terminal bus 21: triplex receiving circuit

22: triple transmission circuit 23: transmission intermediate circuit

24: maintenance command and alarm status circuit

31: Arbitration counter 32: Data transmission bus occupied signal generating circuit

33: long time transmission bus occupied signal generating circuit

34: triple signal selection circuit 35: transmission control circuit

36: bus transceiver

The present invention relates to a transmission intermediate circuit in a signal terminal control device implemented in an electronic ventilation common line signal device.

According to the present invention, an arbitration counter and a data transmission bus occupancy signal are placed in a signal terminal control apparatus and a signal terminal group maintenance apparatus in a signal terminal group, and when a signal terminal control apparatus has a message to be transmitted, the message transmission bus occupies a data transmission bus. When the message transmission is completed, the data transmission bus is transferred to another signal terminal control device so that transmission arbitration can be performed. That is, one signal at a time when transmitting in a signal terminal group having up to 32 signal terminal control devices. The purpose of this is to ensure that only the terminal controller can send data, thereby preventing data collisions and allowing all signal terminal controllers to receive the transmission sequence evenly.

In order to achieve the above object, the present invention provides a signal terminal control apparatus transmission arbitration circuit, comprising: an arbitration counter means, a data transmission bus occupancy signal generation means connected to the arbitration counter means, and a long time connection to the data transmission bus refinery signal generation means. And a triplet selection circuit connected to the transmission bus occupying signal generating means and the arbitration counter means, and characterized in that it performs an arbitration function when the signal terminal control device transmits a message to a higher level.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a signal terminal control apparatus in a common line signal device signal terminal group to which the present invention is applied, FIG. 2 is a block diagram of a signal terminal bus matching unit of FIG. 1 to which the present invention is applied, and FIG. 11 is a level 1 bus matching unit, 12 is a protocol processing unit, 13 is a signal terminal bus matching unit 14 is a signal terminal controller, 15 is a signal terminal bus, 21 is a triplex receiving circuit, and 22 is a triplex transmitting circuit. 23 is a transmission arbitration circuit, 24 is a maintenance command and alarm status circuit 31 is an arbitration counter, 32 is a data transmission bus occupied signal generation circuit, 33 is a long time transmission bus occupied signal generation circuit, 34 is a triple signal selection circuit, 35 Denotes a transmission control circuit, and 36 denotes a bus transceiver, respectively.

As shown in FIG. 1, the signal terminal control apparatus 14 in the signal terminal group includes a protocol processing unit 12, a signal terminal bus matching unit 13, and a level 1 matching unit 11, and the protocol processing unit 12 ) Is composed of general purpose CPU (Centrol Processing Unit) and memory to perform the entire level 2 of common line signaling protocols, but to realize and execute various protocols as necessary, the signal terminal control unit 14 can But it can be applied as a packet processor according to the protocol to perform.

The level 1 matching unit 11 multiplexes a 65 Kbps or 56 Kbps signal message from each signal terminal control unit 14 into a 2.048 Mbps PCM frame and sends it to a time switch and performs a reverse function with a level 1 matching device. Perform the interface.

The signal terminal bus 15 is a serial bus that can accommodate up to 32 signal terminal control devices 14, and occupies a data transmission bus, a data reception bus, a data transmission / reception clock, a signal terminal group synchronization signal, and a data transmission bus. It consists of signals such as traffic lights, and important signals are tripled and operated in a triple modular redunancy (TMR) method.

The data transmission / reception clock and the signal terminal group synchronization signal are generated by the signal terminal group maintenance apparatus and supplied to all signal terminal controllers in the form of a bus. The data transmission bus and the data reception bus are serial communication buses, each of which is a bus for transmitting and receiving data by a signal terminal control apparatus, and the data transmission bus occupancy signal is a signal generated by the transmission mediation circuit 23.

The signal terminal bus matching section 13 has a function of triplexing and transmitting the data to be transmitted when there is no transmission prohibition command from a failure or higher level of the signal terminal control device itself as shown in FIG. The triplex receiving circuit 21 functions to extract and accept a signal inputted as a single signal, and to perform a command according to a command from a higher level, or a maintenance command that allows a fault state to be read. And an alarm status circuit 24 and a transmission arbitration circuit 23 that performs transmission arbitration, a function of the present invention, to perform a reliable communication function with a higher level (level 3) through a signal terminal group holding boss device. do.

As shown in FIG. 3, the transmission arbitration circuit 23 includes an arbitration counter 31, a data transmission bus occupied signal generation circuit 32, a long time transmission bus occupied signal generation circuit 33, and a triplex signal selection circuit 34. It is configured to perform the arbitration function when the signal terminal control unit 14 transmits a message to a higher level.

As shown in FIG. 3, the transmission arbitration circuit 23 includes an arbitration counter 31, a data transmission bus occupied signal generation circuit 32, a long time transmission bus occupied signal generation circuit 33, and a triplex signal selection circuit 34. It is configured to perform the arbitration function when the signal terminal control unit 14 transmits a message to a higher level.

The arbitration counter 31 of the transmission arbitration circuit 23 includes two synchronous binary counters 74F 161 located in each signal terminal control device and the signal terminal group maintenance device, and the signal terminal group synchronization signal NSYN C *. It is preset to its physical address (STID 1-6) by the value and then the value is increased by the clock (NCLK) for data transmission and reception. At this time, when the arbitration counter 31 reaches the maximum value FF, the TC (Terminal Count) is output and transmitted to the data transmission bus occupied signal generation circuit.

The data transmission bus occupancy signal generation circuit 32 receives the TC signal from the arbitration counter 31 while the data transmission reservation signal TXRDY is supplied and the current data transmission bus occupancy signal is not generated. Generates data transmission bus occupancy signal (AST) at the rising edge. This signal is transmitted to the transmission bus occupied signal generation circuit 33 for a long time to monitor the time occupying the transmission bus and transmitted to the transmission control circuit 35 of the triplex transmission circuit 22 to occupy the transmission bus for a long time. When the signal is not generated and there is no failure of the data transmission / reception clock and at the same time, there is no prohibition command from the signal terminal group maintenance device, the bus transceiver 36 is enabled and the bus transceiver 36 of the triplex transmission circuit 22 is activated. ), A single signal is input as three signals.

The bus transceiver 36 transmits the triplet output signal to the triplet signal selection circuit 34 and the triplet bus signal TXAST * to the signal terminal bus 15 to control other signal terminal controllers and signal terminals. It lets the group maintenance unit know that it is transmitting. At the same time, the protocol processing unit 12 notifies the transmission start interrupt (ASY *) of its own transmission, and the protocol processing unit 12 starts the transmission and uses the control register to start the transmission so that the transmission start interrupt is not caught again during transmission. Generate an interrupt prohibition signal. When the transmission is completed, the protocol processing unit 12 releases the transmission start interrupt prohibition signal so that the transmission start interrupt can be applied again. All the arbitration counters 31 are stopped at the verb as soon as they generate the data transmission bus occupancy signal. When the protocol processing unit 12 receives the data transmission reservation signal and notifies that the message transmission is completed, the arbitration counter 31 receives the data transmission bus occupation signal and arbitrates. The counter 31 continues to increment again and passes the turn of transmission to the other signal terminal controller.

The data transmission reservation signal generates a data transmission reservation signal in software using the control register in the protocol processing section 12 when there is a message to be transmitted at a higher level. The data transmission bus occupied signal generation circuit 32 was constructed using an AND gate, an OR gate, and a latch 74LS74.

The triplet signal selection circuit 34 selects a value of two or more signal lines having the same logic level as the correct value among the data transmission bus occupied signals input from the bus transceiver 36 of the triplex transmission circuit 22 as a triplet signal. It outputs as one signal so that it is supplied to its arbitration counter 31.

The triple signal selection circuit 34 is implemented using PAL (Programmable Array Logic). The long time transmission bus occupied signal generation circuit 33 receives the long time transmission bus occupied clock signal LASTCLK from the protocol processor 12 and counts the time. If the data transmission bus occupied signal is occupied by the transmission bus for a predetermined time or more, a long time transmission bus occupied signal LASTFT is generated and transmitted to the transmission control circuit 35 of the triplex transmission circuit 22 to control the signal terminal. The device 14 itself prevents the transmission of the message and informs the protocol processor 12 of the content so that appropriate action can be taken. It is also stored in the maintenance command and alarm status circuit 24 so that it can be read by the signal terminal maintenance device if necessary. This long time transmission bus occupied signal generation circuit 33 was constructed using the synchronous binary counter 74F161 and the latch 74LS74.

Since the present invention is constructed and operated as described above, all signal terminal control devices can transmit evenly when multiple signal terminal control devices transmit using a common bus in a common line signal device of an electronic exchange. There is an advantage.

Claims (5)

In the transmission arbitration circuit of the signal terminal control apparatus, the mediation counter means 31, the data transmission bus occupancy signal generation means 32 connected to the arbitration counter means 31, and the data transmission bus occupancy signal generation means 32 It is composed of a long time transmission bus occupancy signal generating means 33 connected, and a triplet signal selection circuit 34 connected to the arbitration counter 31, so as to provide an arbitration function when the signal terminal controller transmits a message to a higher level. Transmitting arbitration circuitry. 2. The mediation counter means (31) according to claim 1, characterized in that the arbitration counter means (31) consists of two synchronous binary counters, which are preset to their physical addresses (STID 1-6) by the signal terminal group synchronization signal (NSYNC *). A transmission arbitration circuit, characterized in that the value is increased by a clock for transmitting / receiving (NCLK) to output a terminal count (TC) when the maximum value (FF) is reached. The data transmission bus occupancy signal generating means (32) is composed of an AND gate, an OR gate, and a latch, so that a data transmission reservation signal (TXRDY) is supplied and a current data transmission bus occupancy signal is not generated. And a data transmission bus occupying signal (AST) at a rising edge of the data transmission / reception clock upon receiving a TC (Terminal Count) signal from the arbitration counter means (31). 2. The apparatus according to claim 1, wherein the long time transmission bus occupancy signal generating means (33) is composed of a synchronous binary counter and a latch to receive a long time transmission bus occupancy clock signal (LASTCLK) from the protocol processor (12). Characterized in that the transmission arbitration circuit. 2. The apparatus of claim 1, wherein the triplet signal selecting means (34) comprises a programmable array logic (PAL). The triplet signal selecting means 34 selects a value of two or more signal lines having the same logic level among the triplet signals to be input as a single signal. And a transmission arbitration circuit, characterized in that it outputs.

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