KR910007810B1 - Synchronous pattern detection circuit of the pulse code modulation apparatus - Google Patents

Abstract

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Description

Synchronous pattern detection circuit of pulse code modulation and demodulation device

1 is a circuit diagram according to the present invention.

2 is a frame synchronization pattern extraction circuit of FIG.

3 is a frame alignment state diagram according to the present invention.

4 is a state transition table diagram in accordance with the present invention.

FIG. 5 is a detailed view of the synchronous state first data detector of FIG.

6 is a detailed view of a synchronous state second data detector of FIG.

7 is a detailed view of the synchronous state third data detector of FIG.

8 is a detailed view of the synchronization state detecting unit of FIG.

9 is a detailed view of the state clock extraction unit.

10 is a detailed view of a remote alarm circuit.

* Explanation of symbols for main parts of the drawings

10: frame synchronous pattern extraction circuit 20-40: first to third flip flop

50: state clock extraction unit 60-80: synchronization situation first to third data detection unit

90: synchronization state detection unit 100: remote alarm circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization pattern detection circuit of a pulse code modulation (hereinafter referred to as PCM) multiple device, and more particularly to a circuit for detecting two synchronization patterns alternately inserted into a predetermined channel of each frame. In the field of digital line transmission, which solves the digital line interface applied to the digital path connecting the switching center and the digital path interconnecting the digital switching center, two synchronization patterns are alternately transmitted from frame to frame on the receiving side, and the receiving side detects the synchronization pattern. It is necessary to judge whether the valid data of the frame or the invalid data are loaded.

This necessity may be the same for the digital paths required for inter-node internal connections of the electronic exchange, or for the internal connection paths of the nodes in the private and exchanges and private exchanges.

In a 32-channel PCM (30B + D structure) multiple device, two synchronization patterns are inserted into the 0 channel of each frame and used alternately.

Among the two synchronization patterns, the first synchronization pattern including the frame array signal and the second synchronization pattern including the frame array signal to avoid the simulation of the frame array signal are related to the bit allocation of channel timeslot 0 of CCITT Recommendation 732. Follow the recommendations.

The first receiving synchronization pattern RS0 (A) including the received frame array signal according to the CCITT recommends that bit 1 reserved for international use is set to "1", and RS0 (A) = 10011011 and sets the frame array signal. The second receiving synchronization pattern RS0 (B), which is not included, sets bit 1 reserved for international use as "1", and bit 2 prescribed as "1" is a warning bit for a remote PCM multiple device. Bit 4 bit 8 is reserved for domestic use and is set to " 1 " to conform to a digital path across the border to enable international use.

Therefore, it is assumed that the second receiving synchronization pattern RS0 (B) = 11 ALT 11111 not including the frame array signal. Here, ALT, bit 3, is a bit for alarming the status of the transmission side, and it is an alarm sound bit for notifying whether the error is regarded as valid data or invalid data at the reception side by notifying whether there is an error on the transmission side.

In addition, bits 4-bit 8 of the second receiving synchronization pattern RS0 (B) not including the frame array signal are set to avoid the simulation of the data pattern and the synchronization pattern by using a code pattern which is not used in the data stream. Therefore, in the 32-channel multiplex device, there is a need to detect alternately inserted synchronization patterns.

Accordingly, an object of the present invention is to alternately insert the first receiver synchronization pattern including the frame array signal and the second receiver synchronization pattern not including the frame array signal in order to avoid the simulation of the frame array signal when the digital line is received. A circuit for detecting a reception synchronization pattern inserted in a reception reception stream is provided.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

와

를 추출하는 동기패턴추출회로(10)와, 상기 수신클럭(RCLK)을 반전하는 임버터(5)와, 소정 상태의 동기상태 천이 제1,제2,제3데이타(D0) (D1)(D2)를 각각 입력하여 소정 제1상태의클럭(CP1)에 의해 상기 각 데이터를 래치하여 현재의 동기상태 데이터를 발생하는 제1,제2,제3플립플롭(20,30,40)과, 상기 인버터(5)의 반전 수신클럭(RCLK : 이하 K1라 칭함)과 제1클럭(K2=8KHZ), 제2클럭 (K2=4KHZ)과 현재의 동기상태 데이터를 입력하여 상기 현재의 동기상태 데이터에 따라 상기 제1클럭, 제2클럭(K1)(K2)과 반전수신클럭(K1)를 제1상태클럭(CP1)과 제2상태클럭(CP2)로 추출 출력하는 상태 클럭추출부(50)와, 상기 프레임 동기패턴 추출회로(10)의 제1수신 동기패턴 RS0(A) 및 그 반전신호

와 제2수신 동기패턴 RS0(B)와 상기 제1,제2,제3플립플롭(20)(30)(40)의 현재의 동기패턴 제1,제2,제3데이타를 입력하여 차기의 동기상태 천이 제1데이타(D0)를 출력하는 동기 천이상태 제1데이타 검출부(60)와, 상기프레임 동기패턴 추출회로(10)의 제1수신동기패턴 RS0(A)와 제2수신동기패턴 RS0(B)의 반전신호

와 상기 제1,제2,제3플립플롭(20,30,40)의 현재의 동기상태 제1,제2,제3 데이터를 입력하여 차기의 동기상태 천이 제2데이타(D1)를 출력하는 동기 천이상태 제2데이타 검출부(70)와, 상기 프레임 동기패턴 추출회로(10)의 제1수신동기패턴 RS0(A)와 제2수신동기패턴 RS0(B)의 반전신호

와 상기 제1, 제2, 제3플립플롭(20,30,40)의 현재의 동기상태 제1,제2,제3데이타의 일부분의 데이터를 입력하여 차기의 동기상태 천이 제3데이타를 출력하는 동기 천이상태 제3데이타 검출부(80)와, 상기 제1, 제2, 제3플립플롭(20,30,40)의 현재 동기상태 데이터를 엔코딩하여 동기상태를 검출하여 동기 검출하여 동기 검출신호(S)를 출력하는 동기상태 검출부(90)와, 상기 프레임 동기패턴 추출회로(10)로부터 출력되는 경보비트(B3)와 상기 제1,제2,제3플립플롭(20,30,40)의 동기상태 제1제2,제3데이타의 일부의 데이터와 동기상태 검출부(90)의 동기검출신호(S) 및 상태클럭 추출부(50)의 출력 제2상태클럭 (CP2)를 입력하여 프레임 정렬 상태에서 연속되는 경보비트(B3)를 검출하여 리모트 알람신호를 출력하는 리모트 알람회로(100)로 구성된다.1 is a synchronization pattern detecting circuit according to the present invention, which shifts serial data RD of a receiving stream line 4 to a receiving clock RCLK of 2.048 MHz frequency and outputs the parallel data, and converts the serial data RD from the converted parallel data. Inverting signals of the first receiving synchronization pattern RS0 (A) and the second receiving synchronization pattern RS0 (A) and the first and second receiving synchronization patterns RS0 (A) and RS0 (B)

Wow

Is a synchronization pattern extraction circuit 10 for extracting the signal, an inverter 5 for inverting the reception clock RCLK, and a synchronization state transition first, second, and third data D0 (D1) ( First, second, and third flip-flops (20, 30, 40) for respectively inputting D2) to latch the respective data by the clock CP1 in a predetermined first state to generate current synchronization state data; The inverted receiving clock RCLK (hereinafter referred to as K1), the first clock K2 = 8KHZ, the second clock K2 = 4KHZ and the current synchronization state data of the inverter 5 are inputted to the current synchronization state data. The state clock extracting unit 50 extracts and outputs the first clock, the second clock K1, the second clock K1, and the inverted reception clock K1 to the first and second state clocks CP1 and CP2. And a first reception synchronization pattern RS0 (A) of the frame synchronization pattern extraction circuit 10 and its inverted signal.

And the second synchronization pattern RS0 (B) and the current synchronization patterns first, second, and third data of the first, second, and third flip-flops 20, 30, and 40 are inputted. A synchronous transition state first data detection unit 60 for outputting a synchronous state transition first data D0, and a first receiver synchronous pattern RS0 (A) and a second receiver synchronous pattern RS0 of the frame synchronous pattern extraction circuit 10. Inverted signal of (B)

Inputting current first, second, and third synchronization states of the first, second, and third flip-flops 20, 30, and 40 to output the next synchronization state transition second data D1; Inverted signals of the synchronous transition state second data detection unit 70 and the first receiving synchronous pattern RS0 (A) and the second receiving synchronous pattern RS0 (B) of the frame synchronous pattern extraction circuit 10.

Inputting data of the first, second, and third data of the first, second, and third current states of the first, second, and third flip-flops 20, 30, and 40 to output the next third state of the third state transition; The synchronization transition state third data detection unit 80 and the current synchronization state data of the first, second, and third flip-flops 20, 30, and 40 are encoded to detect the synchronization state, to detect the synchronization, and to synchronize the detection signal. (S) a synchronization state detection unit (90) for outputting, an alarm bit (B3) output from the frame synchronization pattern extraction circuit (10), and the first, second, and third flip-flops (20, 30, 40). A frame by inputting a part of data of the first, second, and third data of the synchronous state, the synchronous detection signal S of the synchronous state detector 90, and the output second state clock CP2 of the state clock extractor 50. The remote alarm circuit 100 detects a continuous alarm bit B3 in an aligned state and outputs a remote alarm signal.

FIG. 2 is a detailed diagram of the frame synchronization pattern extraction circuit 10 of FIG. 1, which shifts the serial reception data RD received by the reception stream line 4 to the reception clock RCLK of the clock line 3, and thus has 8 bits. A shift register 11 for outputting parallel data, a NAND gate 12 for outputting the signals of the (QA, QB, QD, QE, QH) output stages of the shift register 11 negatively and logically, and the shift register ( An OR gate 13 for ORing and outputting the (QC, QF, QG) output terminal signals of 11), and a first receiver synchronous pattern RSO (A) for ORing the outputs of the NAND gates 12 and the oragate 13; Or an inverter 15 for inverting the output of the oragate 14 and outputting an inverted signal of the first receiver synchronous pattern RS0 (A), the first receiver synchronous pattern RS0 ( A ratio between the first extraction unit 18 for extracting A) and the output bit of the shift register 11 except for the alarm bit output terminal QF. The NAND gate 16 for extracting the second receive synchronization pattern RS0 (B) by inversely inputting the data, and inverting the output of the NAND gate 16 to output the inverted second receive synchronization pattern RS0 (B). It is composed of a second extraction unit 19.

3 is a frame alignment transition state diagram according to the present invention.

4 is a state transition table according to the present invention.

In the state transition table of FIG.

RS0 (A) = 0: State of First Receive Synchronization Pattern

RS0 (A) = 1: Not in the first receive sync pattern

RS0 (B) = 0: Second Receive Sync Pattern State

RS0 (B) = 1: Not in the second receive sync pattern

S = 0: Frame alignment status (1N-SYNC)

S = 1: Frame misalignment (OUT-OF-SYNC)

A1A0 = 00: Sync pattern search clock (K1 = 2,048MHZ)

A1A0 = 01: Alternating synchronization pattern monitoring and searching clock (K2 = 8KHZ)

A1A0 = 10: This is a search clock (K3 = 4KHZ) that monitors only the RS0 (A) or RS0 (B) synchronization pattern.

d: don't care.

FIG. 5 is a detailed view of the synchronous state transition first data detector of FIG. 1, and includes NAND gates 61, 62, 63, and 64 to encode and output an input signal.

6 is a detailed view of the synchronous state transition second data detector of FIG. 1, which is composed of NAND gates 71-77 to encode an input signal to output synchronous state transition second data.

FIG. 7 is a detailed view of the synchronization state transition 3 data detector of FIG. 1, which is composed of NAND gates 81-83 to encode an input signal to output the synchronization state transition third data.

FIG. 8 is a detailed diagram of the synchronization state detection unit shown in FIG. 1, and is a circuit configured to detect the synchronization detection signal S by encoding the current synchronization state data signal which is composed of NAND gates 91-93.

FIG. 9 is a detailed view of the state clock extractor of FIG. 1, which is composed of NAND gates 51-57, and includes the first state clock CP1 and the second clock CP2 among the input clocks K1, K2, and K3 according to the synchronization state data. ).

FIG. 10 is a detailed view of the remote alarm circuit of FIG. 1 and includes a N flip gate 101-103 and a D flip-flop 104 which latches and outputs an output of the NAND gate 103 to a second state clock CP2. And a 4-bit binary counter 105 for counting and outputting the output of the D flip-flop 104, and a monostable triggered by the output of the counter 105 to generate a remote alarm signal for a predetermined time. It consists of 106.

Hereinafter, an operation example of the present invention will be described in detail with reference to FIGS. 1 to 10.

Now, the state clock extractor 50 of the first, second and third flip-flops 20-40 of FIG. 1 is configured as shown in FIG. 9 in the initial state of the S0 state of FIGS. The state clock CP1 is selectively outputted to 2,048MHZ as shown in FIG.

As described above, the state of S0 is an initial state, and is a synchronous pattern search state. At this time, the first state clock CP1 of the state clock extractor 50 has the first, second and third flip-flops 20-40. Is provided by the clock.

In the above state, when the first receiver synchronization pattern data is input to the receive stream line 4 and the output RS0 (A) of the synchronization pattern extraction circuit 10 configured as shown in FIG. 2 is " low " The first, second and third data detection units 60-80 for inputting the output of the sync pattern extraction circuit 10 and the current sync state data of the S0 state are respectively the first, second, and second transition states. 2, third data D0, D1, and D2 are output. At this time, the synchronous state transition first data is "high", and the synchronous state transition second and third data are "low".

The synchronous state transitions of the first, second, and third data (D0, D1, D2) are performed by the first state clock (CP1), 2,048 MHZ (K1) of the state clock extractor 50. The third flip-flop 20-40 is latched and shifted to the state S1 as shown in FIGS. 3 and 4. The S1 state is a state in which a similar synchronization pattern is found, and searches for the second receiving synchronization pattern RS0 (B) of the next received frame.

When the second receive synchronization pattern data is input to the reception stream line 4 of FIG. 1 in the S1 state, the output RS0 (B) of the frame synchronization pattern extraction circuit 10 becomes "low" as described above. At this time, the first clock clock CP1 of the status clock extractor 50 outputs a second clock K2 8KHZ, and the second clock K2 is the first, second and third flip-flops 20-40. Is provided by the clock.

The first, second, and third flip-flops 20-40 latch-output the state S1 of FIG. 4 by the second clock K2 = 8KHZ, thereby outputting synchronous state data that is the logic of the state S2, and thereby the state S2. As it transitions.

If the second receiver synchronous pattern data is not input to the reception stream line 4 in the S1 state, the process returns to the S0 state and searches for the first receiver synchronous pattern RS0 (A). At this time, the first state clock CP1 of the state clock extractor 50 is outputted to the reception clock K1 2,048MHZ to be in the sync pattern search clock state.

As described above, when the second receiving sync pattern RS0 (B) is detected from the sync pattern detecting circuit 10, the first, second, and third of the next sync state transition first, second, and third data detectors 60-80. As the third data D0, D1, and D2 are outputted, the third data D0, D1, and D2 are transitioned to the S2 state from the output state of the first, second, and third flip-flops 20-40.

When the data of the first reception synchronization pattern RS0 (A) is input to the next frame input to the next reception stream line 4, the synchronization pattern extraction circuit 10 configured as shown in FIG. 2 extracts the first reception synchronization pattern state. RS0 (A) is detected. In this case, since the first state clock CP1 of the state clock extractor 50 outputs the first clock K2 (8KHZ), the first reception synchronization state RS0 (A) of the sync pattern extraction circuit 10 is performed. Synchronous state transition by output The first, second, and third transition outputs of the first, second, and third data D0, D1, and D2 of the first, second, and third data detectors 60-80 are output. Flip-flops 20-40 each latch output.

Therefore, in the S2 state of FIGS. 3 and 4, the first receiver synchronous pattern RS0 (A) of the sync pattern extraction circuit 10 detects whether the state transitions to the S0 state or the S3 state.

If the first reception synchronization pattern RS0 (A) of the frame synchronization pattern detecting circuit 10 is detected as described above, the state transitions from the S2 state to the S3 state as shown in FIGS. 3 and 4. As shown in the S3 state, when the outputs Q0, Q1 and Q2 of the first, second and third flip-flops 20-40 are output as "0, 1, 0", the first state clock of the state clock extractor 50 CP1 is a state in which the first clock K1 (8KHZ) is output.

When the data received in the next frame in the S3 state is input to the second receiving sync pattern RS0 (B), the sync state transition first and second are detected by the frame sync pattern extraction circuit 10 configured as shown in FIG. As described above, the first, second and third data D0, D1, and D2 of the third data detector 60-80 are outputted. At this time, the first, second, and third data of the synchronous state transition first, second, and third data 60-80 are the first state clock of the state clock extracting unit 50. The first clock K1 (8KHZ), which is CP1, is latched to the first, second, and third flip-flops 20-40 to transition to the S4 state of FIGS. 3 and 4.

If the second receiving synchronization pattern RS0 (B) is not detected (extracted) in the next frame in the S3 state, the state transitions to the S7 state and the output of the first state clock CP1 of the state clock extractor 50 is also converted. . When the next input frame data is input to the first receiving synchronization pattern RS0 (A) in the transitioned state as shown in FIGS. 3 and 4, the output RS0 of the frame synchronization pattern extraction circuit 10 as described above ( B) becomes "low". In this case, the first state clock C / 1 of the state clock extraction unit 50 outputs a second clock K2, 8KHZ, which is an alternating synchronization monitoring and searching clock, and the second clock K2 is the first and second. It is provided as a clock of the third flip-flop (20-40).

Outputs Q0, Q1, and Q2 of the first, second, and third flip-flops 20-40 output "010" as shown in S3 of FIG. 3 and FIG. As described above, the repetition state of the S3 and S4 states is called a frame alignment state. In other words, the reception stream line 4 is inputted as a normal alternating synchronization pattern of the reception synchronization pattern of the data.

If the reception synchronization pattern input to the reception stream line 4 in the above-described S4 state is not the first reception synchronization pattern RS0 (A), RS0 (A) of the frame synchronization pattern detection circuit 10 is set to " low ". By outputting, all of the synchronous state transitions are output "high" to the data outputs D0, D1, and D2 of the first, second, and third data detection units 60-80.

Accordingly, the first, second, and third latches 20-40 latch all of the " high " by 8KHZ of the first clock K2 of the first state output CP1 of the state clock extractor 50 so as to output S. Transition to state At this time, the state clock extractor 50 inputting the current synchronization state data of the first, second, and third latches 20-40 outputs the first state clock CP1 to the second clock K3 4KHZ. .

When the data input to the frame synchronization pattern extraction circuit 10 is input to the first receiving synchronization pattern RS0 (A) in the S5 state of FIGS. 3 and 4, the first, second, and third data detection units of the synchronization state transition are performed. The output of 60-80 is shifted together with the next output in the state S5 of FIG. 4 so that the first and second are driven by 4KHZ of the second clock K2 of the first state clock CP1 of the state clock extraction unit 50. And latched in third latch 20-40.

Therefore, the state transitions from the S5 state to the S3 state as shown in Figs. 3 and 4, and enters into the alternator search state. When the next received data is RS0 (B), the frame is in the alternating state. At this time, the first state clock CP1 of the state clock extractor 50 is output as the first clock K1 and 8KHZ.

On the other hand, as described above, the synchronous state detector 90 for inputting synchronous state data output from the first, second, and third flip-flops 20-40 encodes an input signal by a logic configuration as shown in FIG. When the synchronization state data in the S3, S4, S5, S6, and S7 states are input, the frame is aligned by outputting the frame synchronization alignment state (IN-SYNC) signal in the "low" state.

The synchronization state detection unit 90 outputs a "high" signal when the synchronization search data is the synchronization pattern error state, i.e., the synchronization search data in the states S0, S1, and S3 of FIG. 4 to output out-of-sync. Indicates.

On the other hand, since the internal counter 105 is cleared by the output " high " of the synchronous state detection unit 90, the alarm circuit 100 having the configuration as shown in FIG. Remote Alarms that are detected are ignored.

However, when the alarm bits ALT (B3) of the second receiving synchronization pattern RS0 (B) without the frame arrangement pattern in the frame alignment state (In-sync) are eight or more " 1 " in succession, the counter 105 Since the output terminal QD is " high ", the monostable 106 is triggered to detect the remote alarm state of the transmitting side. At this time, the remote alarm state is detected only in the frame alignment state of FIGS.

As described above, the present invention accurately detects synchronization patterns transmitted from frame to frame and alternately stores valid data or invalid data in order to avoid copying patterns by data during data transmission. The advantage is that a digital line interface can be implemented that can only receive data.

Claims (2)

In the synchronization pattern detection circuit of the pulse code modulation and demodulation device, the serial data RD of the reception stream line 4 is shifted to the reception clock RCLK of 2.048 MHz frequency and output as parallel data. Inverted signal of one receiver sync pattern RS0 (A) and second receiver sync pattern RS0 (A) and the first and second receiver sync patterns RS0 (A) and RS0 (B)

Wow

Is a synchronization pattern extraction circuit 10 for extracting the signal, an inverter 5 for inverting the reception clock RCLK, and the first, second, and third data D0, D1, D2 First, second, and third flip-flops 20, 30, and 40 each of which is inputted to latch each of the data by a clock CP1 of a predetermined first state to generate current synchronization state data. The inverted receiving clock RCLK of the inverter 5 (hereinafter referred to as K1), the first clock K2 = 8KHZ, the second clock K2 = 4KHZ and the current synchronization state data are inputted to the current synchronization state data. Accordingly, the state clock extracting unit 50 extracts and outputs the first clock, the second clock K1, K2 and the inverted reception clock K1 to the first and second state clocks CP1 and CP2. And a first receiving sync pattern RS0 (A) of the frame sync pattern extracting circuit 10 and its inverted signal.

And the second synchronization pattern RS0 (B) and the current synchronization patterns first, second, and third data of the first, second, and third flip-flops 20, 30, and 40 are inputted. The synchronous transition state first data detection unit 60 for outputting the synchronous state transition first data D0, and the frame synchronization pattern extraction circuit 10 to receive the first received synchronization pattern RSO (A) and the second received synchronization pattern RSO. Inverted signal of (B)

Inputting current first, second and third current synchronization states of the first, second and third flip-flops 20, 30 and 40 to output the next synchronization state transition second data D1. The inversion signal of the first data synchronization pattern RSO (A) and the second data synchronization pattern RSO (B) by the second data detection unit 70 and the frame synchronization pattern extraction circuit 10.

Inputting data of the first, second, and third data of the first, second, and third data of the first, second, and third flip-flops 20, 30, and 40 to output the next data of the third sync state transition; The synchronization transition state third data detection unit 80 and the current synchronization state data of the first, second, and third flip-flops 20, 30, and 40 are encoded to detect a synchronization state, and then the synchronization detection signal unit S ) Is synchronized with the synchronization state detection unit 90 and the alarm bit B3 output from the frame synchronization pattern extraction circuit 10 and the first, second, and third flip-flops 20, 30, and 40. Frame alignment by inputting some data of the state first, second, and third data, the synchronous detection signal S of the synchronous state detection unit 90, and the output second state clock CP2 of the state clock extractor 50 And a remote alarm circuit (100) for detecting a continuous alarm bit (B3) in the state and outputting a remote alarm signal. 2. The frame synchronization pattern extraction circuit according to claim 1, wherein the serial reception data (RD) received on the reception stream line (4) is shifted to the reception clock (RCLK) of the clock line (3) and output as 8-bit parallel data. The NAND gate 12 which negatively outputs the signals of the (QA, QB, QD, QE, QH) output stages of the shift register 11, the shift register 11, and the ( An OR gate 13 for ORing and outputting the QC, QF, and QG) output terminal signals; and an e OR gate 13 for ORing the outputs of the NAND gate 12 and the oragate 13 and outputting a first reception synchronization pattern RS0 (A). An agate 14 and an inverter 15 which inverts the output of the oragate 14 and outputs an inverted signal of the first receiver synchronous pattern RS0 (A) to extract the first receiver synchronous pattern RS0 (A). The first extracting unit 18 and the remaining bits of the output stage of the shift register 11 except for the alarm bit output terminal QF NAND gate 16 for extracting the second reception synchronization pattern RS0 (B) by performing a negative logic multiplication, and inverting the output of the NAND gate 16 to output the inverted second reception synchronization pattern RS0 (B). And a second extraction unit (19).

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