KR900002461Y1 - Voltage regulating circuit of automatic gain regulating circuit in optical transmission device - Google Patents

Abstract

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Description

Voltage regulating circuit of automatic gain regulating circuit in optical transmission device

1 is a relation curve diagram of the reverse bias voltage and the multiplication gain of an Ever Ranch photodiode.

2 is a block diagram of the present invention.

3 is a detailed circuit diagram of the automatic gain control circuit of the block diagram according to the present invention of FIG.

* Explanation of symbols for main parts of the drawings

20: preamplifier 30: half-wave rectifier

40: comparator 50: voltage control circuit

60: high voltage supply source

The present invention relates to a voltage adjusting circuit in an automatic gain control circuit (AGC) used in an optical transmission device, and in particular, an Avalanche Photo Diode (hereinafter referred to as APD) as a light receiving element. A circuit for adjusting the reverse bias supply voltage of the APD in a light receiving device.

In general, in the optical transmission device, a pin diode and an APD are used as light source data.

The pin diode has good linearity but no multiplication, and it is known that APD is preferable to pin diode in a long distance pulsed light transmission method.

On the other hand, APD has a multiplication of photocurrent by Avalanche multiplication, and if the multiplication factor is changed according to the reverse bias voltage supplied to the APD, they are determined accordingly.

Therefore, when the APD is used as the light receiving element, the reverse bias voltage is supplied to both ends of the APD.

In addition, as shown in FIG. 1, increasing the reverse bias voltage supplied across the APD increases the multiplication factor M of the APD. Therefore, the gain of the APD, which photoelectrically converts the received optical signal and outputs the electrical signal, is increased, and the level of the signal output from the APD is increased. If the reverse bias voltage supplied across the APD is reduced, the level of the signal output from the APD is reduced.

By using such a relationship, an AGC circuit has been used that maintains a constant output signal level of the APD by appropriately adjusting the multiplication factor M by varying the reverse bias voltage supplied to the APD with respect to the received optical signal level variation.

The conventional AGC circuit amplifies the photoelectrically converted electrical signal in the APD in the preamplifier, peak-detects the output of the amplifier and compares it with the reference voltage of the comparator, and adjusts the high voltage source to the output DC voltage of the comparator to supply a high voltage source. By using the output direct current voltage as the reverse bias of the APD, the output signal level of the APD was kept constant.

The conventional AGC circuit as described above amplifies the electric signal photoelectrically converted in the APD in the preamplifier, peak-detects the amplified signal, and outputs it to the comparator as a DC voltage.

By comparing the level of the signal input from the comparator with the set reference voltage, the output DC voltage is increased or decreased according to the variation of the input signal level and output to the voltage adjusting circuit. Therefore, as the output DC voltage of the comparator increases or decreases, the voltage regulating circuit adjusts the magnitude of the high voltage of the constant voltage supplied from the high voltage supply source and outputs the reverse bias voltage at both ends of the APD. That is, when the output level of the APD decreases due to the reduction of the received optical signal level, the reverse bias voltage supplied to the APD is increased to increase the multiplication factor (M) to increase the output level of the APD, and the received optical signal level is increased. When the output level of the APD becomes too large, the reverse bias voltage supplied to the APD is reduced to reduce the multiplication factor M, thereby reducing the output level of the APD. Therefore, the level of the signal output from the APD is kept constant regardless of the fluctuation of the received optical signal level.

However, in the conventional AGC circuit, there is no circuit for adjusting the minimum reverse bias voltage of the APD, so that the output level of the APD and the output amplifier of the preamplifier are unstable according to the level of the received optical signal.

In other words, as shown in the relationship curve between the reverse bias voltage and the multiplication coefficient M of the APD as shown in FIG. 1, the multiplication coefficient M is constant when the reverse bias voltage is less than or equal to the minimum reverse bias voltage V1. do.

Therefore, if the reverse bias voltage supplied to the APD is adjusted to be less than or equal to the minimum reverse bias voltage (V1), even if the reverse bias voltage is increased or decreased, the multiplication factor (M) of the APD cannot be fixed. Constant amplifier output levels are not expected.

Accordingly, an object of the present invention is to provide a circuit that can easily adjust the minimum reverse bias voltage of the APD.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a block diagram of an AGC circuit of an APD in accordance with the present invention, in which an APD 10 for outputting an electrical signal by photoelectric conversion of a received optical signal, and amplifying the signal detected by the APD 10 are inputted and amplified. Half-wave rectifier 30 for inputting the pre-amplifier 20, the pre-amplifier 20 output signal and half-wave rectifying the AC signal of the output signal, and half-wave of the half-wave rectifier signal output from the half-wave rectifier 30. Comparing the peak voltage with a reference voltage that is already set, if the peak voltage is greater than the reference voltage and outputs a high DC voltage and vice versa, the comparator 40 outputs a low DC voltage; When the reverse bias voltage supplied to the APD 10 for adjusting the magnitude of a constant high voltage output to the output terminal Vout of the high voltage source 60 by the DC voltage is equal to or greater than the minimum reverse bias voltage of the APD 10. It consists of the voltage control circuit 50 such that adjustment.

When the level of the optical signal received by the component circuit of FIG. 2 increases, the signal level converted into an electrical signal from the APD 10 and output is increased. In addition, since the output of the preamplifier 20 also increases, the DC voltage level output from the comparator 40 also increases.

Therefore, the voltage regulating circuit 50 reduces and adjusts the magnitude of the constant high voltage supplied from the high voltage source 60 to supply the reverse bias voltage to the APD 10. Therefore, since the reverse bias voltage supplied to the APD 10 is reduced, the doubling coefficient M of the APD 10 is reduced, thereby reducing the output level of the APD 10.

In addition, when the level of the received optical signal decreases, the APD 10 converts the signal into an electrical signal, thereby decreasing the signal level. In addition, since the output of the preamplifier 20 is also reduced, the DC voltage level output from the comparator 40 is also reduced. Therefore, the voltage regulating circuit 50 increases by adjusting the magnitude of the constant high voltage supplied from the high voltage supply source 60 and supplies it to the APD 10 as a reverse bias voltage.

Therefore, since the reverse bias voltage supplied to the APD 10 is increased, the multiplication factor M of the APD 10 is increased to increase the output level of the APD 10.

In this case, the voltage regulating circuit 50 adjusts the reverse bias voltage supplied to the APD 10 only at least the minimum reverse bias voltage V1, thereby increasing or decreasing the reverse bias voltage supplied to the APD 10. The doubling coefficient (M) of 10) can also be increased or decreased proportionally.

Accordingly, even if the level of the received optical signal varies, the level of the signal output by photoelectric conversion from the APD 10 is constant, so that the level of the signal output from the preamplifier 20 is kept constant.

FIG. 3 shows a concrete circuit diagram of the AGC circuit 70 of FIG. 2, in which R1-R8 is a resistor, Q1 and Q2 are transistors, C1-C7 is a capacitor, and VR1 and VR2 are variable resistors. Is the operational amplifier.

In the figure, the portion composed of the capacitor C1, the resistors R1-R3 and the transistor Q1 is the half-wave rectifier 30 of FIG. 1, and the portion composed of the resistors R4 and R5, the variable resistor VR1, the capacitor C2-C4, and the operational amplifier 400 is a comparator. Corresponding to 40, a portion composed of the variable resistor VR2, the capacitors C5-C7, the resistors R6-R8, and the transistor Q2 corresponds to the voltage regulating circuit 50.

Hereinafter, an operation example of FIG. 3 according to the present invention will be described in detail. The AC signal output from the preamplifier 20 of FIG. 2 is input to the half-wave rectifier 30 of FIG. 3 through the input line 90.

Accordingly, the AC signal is input to the base of the transistor Q1 through the DC blocking capacitor C1 and the power supply voltage Vcc is supplied to the collector of the transistor Q1. Further, when the bias voltage applied to the base of the transistor Q1 due to the partial pressure of the resistor R1 between the collector and the base of the transistor Q1 and the resistor R2 in contact between the base and the ground is about 0.8 volt, the base-emi of the transistor Q1 A voltage of about 0.1 volts, except for the forward conduction voltage of about 0.7 volts, is applied to R3 in contact between the emitter and the ground of the transistor.

Therefore, assuming that the peak-to-peak voltage of the idle signal input to the input line 90 is 2Vp, the voltage appearing at the emitter of the transistor Q1 is represented by the positive polarity of the voltage of Vp + 0.1 volt and the negative signal of the AC signal is This eliminates half-wave rectification.

The half-wave rectified AC signal is input to the non-inverting terminal (+) of the operational amplifier 100 through the resistor R4, and the inverting terminal (-) is supplied with a constant reference voltage at a partial voltage of the power supply voltage Vcc by the variable resistor VR1. . Therefore, the peak value of the half-wave rectified AC signal is compared with the reference voltage, and an output proportional to the comparison difference is output from the comparator 40.

In the comparator 40, capacitors C3-C4 were used for bypass to remove the ripple and to prevent the DC voltage appearing on the output side from being sensitively changed.

Therefore, when the optical signal level received by the APD increases, the peak of the half-wave rectified signal output from the half-wave rectifier 30 increases, and the output DC voltage of the comparator 40 also increases in proportion thereto. On the contrary, the output current voltage of the comparator 40 becomes small. The output DC voltage of the comparator 40 is divided by the variable resistor VR2 and the resistor R6 of the voltage regulating circuit 50 and applied to the base of the transistor Q2 as a bias voltage.

Therefore, when the output DC voltage of the comparator 40 applied to the transistor Q2 base becomes large, the current flowing through the base of the transistor Q2 increases, and when the output DC voltage of the comparator 40 decreases, the current flowing through the base of the transistor Q2 also decreases. Lose. Therefore, as the current flowing through the base of the transistor Q2 increases or decreases, the collector current of the transistor Q2 also increases or decreases in proportion.

On the other hand, the high voltage supply source 60 is a well-known constant voltage supply circuit for outputting a high voltage of a certain size to the output terminal (Vout) is used and the maximum that can be supplied to the APD 10 according to the characteristics of the APD 10 of FIG. User-configurable to output reverse bias voltage. Therefore, if the high voltage V _H of the constant magnitude output from the high voltage source 60 and the collector current of the transistor Q2 is I _C , the reverse bias voltage V _APD supplied to the APD 10 of FIG. 2 through the line 80 is obtained. Becomes as follows.

V _APE = V _H -IC.R7. … … … (One)

Therefore, in the above formula (1), the voltage drop at the resistor R7 increases and decreases proportionally by the increase and decrease of the collector current I _C of the transistor Q2. Since the high voltage V _H output to the high voltage source 60 is constant, as shown in Equation (1), when the collector current I _C of the transistor Q2 increases, the high voltage V _H is supplied to the APD 10 of FIG. 2 through the line 80. The reverse bias voltage V _APD decreases. In addition, when the collector current I _C of the transistor Q2 decreases, the reverse bias voltage V _APD supplied to the APD 10 of FIG. 2 through the line 80 increases.

At this time, since the collector current I _C of the transistor Q2 is determined by the increase and decrease of the current flowing through the base, the current flowing through the base of the transistor Q2 by the DC voltage output from the comparator 40 by adjusting the variable resistance VR2 is less than a predetermined level. If so adjusted, the collector current I _C of the wing transistor Q2 also does not exceed a certain level. That is, the reverse bias voltage V _{APD obtained} by subtracting the voltage drop (IC.R7) from the resistor R7 by the collector current I _C of the transistor Q2 from the high voltage V _H output from the high voltage source 60 is shown in FIG. The current flowing through the base of the transistor Q2 is adjusted as the variable resistor VR2 so as not to fall below the minimum reverse bias voltage V1.

Therefore, when the designer knows the device characteristics of the APD 10 of FIG. 2, the reverse bias voltage supplied to the APD 10 by DLM adjustment of the variable resistance VR2 is greater than or equal to the minimum reverse bias voltage V1 of the APD 10. It can be set as possible. Capacitors C5-C7 are used for noise bypass.

Therefore, by adjusting the variable resistance VR2, the reverse bias voltage V _APD supplied to the APD 10 is adjusted so as not to be below the minimum reverse bias voltage V1 at which the multiplication factor M becomes constant as shown in FIG. If so, the multiplication factor M of the APD 10 becomes larger or smaller in proportion to the increase or decrease of the supplied reverse bias voltage V _APD . That is supplied to the first reverse bias voltage V multiplication factor (M) a reverse bias voltage V is the APD (10) _APD less than the minimum reverse bias voltage (V1) that does not change the APD (10) even when increasing or decreasing the _APD, as shown in FIG. In this case, the APD 10 operates in a high sensitivity proportional to the reverse bias voltage V _APD to which the multiplication factor M is supplied.

When the level of the received optical signal is increased, the signal level output from the APD 10 increases, and the signal level amplified and output from the preamplifier 20 also increases. Therefore, the peak voltage of the half-wave rectified signal output from the half-wave rectifier 30 increases, and the output DC voltage of the comparator 40 also increases in proportion.

In addition, when the output DC voltage of the comparator 40 increases, the base current of the transistor Q2 of the voltage regulating circuit 50 increases, so that the collector current I _C of the transistor Q2 also increases. Therefore, the voltage drop at the resistor R7 becomes large so that the reverse bias voltage V _APD supplied to the APD 10 can be reduced, as can be seen from Equation (1). Accordingly, the multiplication factor M of the APD 10 is reduced as shown in FIG. 1, so that the signal level output from the APD 10 is also reduced.

On the other hand, when the level of the received optical signal is smaller, the signal level output from the APD 10 is smaller, and the signal level amplified and output from the preamplifier 20 is smaller. Therefore, the peak voltage of the half-wave rectified signal output from the half-wave rectifier 30 is reduced, and the output DC voltage of the comparator 40 is also reduced in proportion.

In addition, when the output DC voltage of the comparator 40 decreases, the base current of the transistor Q2 of the voltage regulating circuit 50 decreases, so that the collector current I _C of the transistor Q2 also decreases. Therefore, the voltage drop at the resistor R7 becomes small, so that the reverse bias voltage V _APD supplied to the APD 10 increases as can be seen from the above equation (1). Accordingly, the multiplication factor M of the APD 10 is increased as shown in FIG. 1, so that the signal level output from the APD 10 is also increased.

At this time, since the resistance variable reverse bias voltage applied to the APD (10) by adjusting the VR2 V _APD so that it will not drop below the minimum reverse bias voltage (V1), said APD (10) is multiplied on the reverse bias voltage V _APD supplied coefficient The high sensitivity operation is proportional to.

Therefore, the output signal level of the APD 10 is amplified by automatically adjusting the reverse bias voltage VAPD supplied to the APD 10 even if the level of the received optical signal varies. The output of the preamplifier 20 can also be kept constant.

As described above, the reverse bias voltage of the APD in the APD bias circuit using the voltage regulation circuit of the present invention can be adjusted so as not to fall below the minimum reverse bias voltage, so that high sensitivity operation of the APD can be achieved and noise under optimum conditions. Will have the advantage of improving.

Claims (1)

A voltage adjusting circuit of an automatic gain control circuit in an optical transmission device including an ever-ranch photodiode 10 used as an optical communication light receiving element and a preamplifier 20 that amplifies the photoelectric conversion electric signal of the averche photodiode 10. A half wave rectifier 30 for half-wave rectifying the AC signal of the preamplifier 20 and a comparator for outputting a DC voltage proportional to the difference by comparing the peak voltage of the half-wave rectified signal with a preset reference voltage. 40, a high voltage supply source 60 for outputting the maximum reverse bias voltage of the aberrant photodiode 10 at a constant voltage, and the aberrant photodiode 10 according to the output DC voltage of the comparator 40; And a voltage regulating circuit 50 capable of adjusting a reverse bias voltage of the circuit and simultaneously setting a minimum operating reverse bias voltage according to device characteristics of the photodiode. Voltage adjusting circuit of automatic gain control circuit in optical transmission device.