KR900001986B1 - 다중 금속층 집적회로 제조방법 - Google Patents
다중 금속층 집적회로 제조방법 Download PDFInfo
- Publication number
- KR900001986B1 KR900001986B1 KR1019860700533A KR860700533A KR900001986B1 KR 900001986 B1 KR900001986 B1 KR 900001986B1 KR 1019860700533 A KR1019860700533 A KR 1019860700533A KR 860700533 A KR860700533 A KR 860700533A KR 900001986 B1 KR900001986 B1 KR 900001986B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- photoresist
- metal
- metal layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
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- H10W20/01—
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- H10W20/071—
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- H10W20/096—
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- H10W20/435—
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (4)
- 최소한 제1 및 제2금속층이 반도체 기질 상에 용착되고 내부 유전물질에 의해 분리되는 다중 금속층 집적회로를 제조하기 위한 방법에 있어서, 내부 유전층의 표면상에 제1내식막 층을 초기에 형성함으로써 내부 유전층 상부에 비교적 두꺼운 감광성 내식막을 형성하는 수단, 제1층에 감광성 내식막 용제가 스며들지 못하게 하는 방식으로 제1층을 처리하는 수단, 제1금속층내의 힐록크 또는 스파이크에 의해 발생되는 내부 유전층내의 수직 돌출물을 덮기에 충분한 두께로 제1감광성 내식막 층 상부에 제2감광성 내식막 층을 형성하므로 다중 감광성 내식막 층이 계속 두께를 유지하고 내부 유전층과 일치함으로써 제1금속층과 제2금속층 사이가 전기적으로 단락되는 것을 방지하여 제조 생산량을 향상시키는 수단을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 제1감광성 내식막 층이 후속인가된 제2감광성 내식막 층내의 용제가 제1감광성 내식막 층으로 스며들지 못하게 하기에 충분한 시간동안 선정된 압력 및 선정된 상승 온도에서 개스 플라즈마에 노출되는 것을 특징으로 하는 방법.
- 최소한 제1 및 제2금속층이 반도체 기질상에 용착되고 내부 유전층에 의해 분리되는 다중 금속층 집적회로를 제조하기 위한 방법에 있어서, 제1금속층 내의 힐록크 또는 스파이크에 의해 발생된 내부 유전층 내의 소정의 수직 돌출물을 덮기에 충분한 두께로 내부 유전층 상부에 네가티브와 포지티브 감광성 내식막 층을 형성함으로써 완전한 감광성 내식막을 형성하는 수단을 포함하고, 네가티브 및 포지티브 감광성 내식막 층내의 상이한 용제가 각각의 네가티브 또는 포지티브 감광성 내식막 층과 충분히 상호작용 하거나 해를 끼치지 못하므로, 합성 감광성 내식막이 계속 두께를 유지할 수 있고 내부 유전층과 일치하게 하여 제1과 제2금속층들 사이가 전기적으로 단락되지 않게 함으로써 제조 생산량이 향상되는 것을 특징으로 하는 방법.
- 제3항에 있어서, 제1감광성 내식막 층이 네가티브 내식 중합체이고, 제2감광성 내식막이 포지티브 내식막 중합체이며, 이 중합체들이 소정의 감광성 내식막 용제에 의해 부식되도록 스며들지 못하게 하기에 충분한 선정된 베이킹 시간 및 온도로 순차적으로 용착되어 베이크 되는 것을 특징으로 하는 방법.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/679,506 US4592132A (en) | 1984-12-07 | 1984-12-07 | Process for fabricating multi-level-metal integrated circuits at high yields |
| US679,506 | 1984-12-07 | ||
| PCT/US1985/002305 WO1986003622A1 (en) | 1984-12-07 | 1985-11-25 | Process for fabricating multi-level-metal integrated circuits at high yields |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR870700171A KR870700171A (ko) | 1987-03-14 |
| KR900001986B1 true KR900001986B1 (ko) | 1990-03-30 |
Family
ID=24727173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019860700533A Expired KR900001986B1 (ko) | 1984-12-07 | 1985-11-25 | 다중 금속층 집적회로 제조방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4592132A (ko) |
| EP (1) | EP0204768B1 (ko) |
| JP (1) | JPS62501321A (ko) |
| KR (1) | KR900001986B1 (ko) |
| DE (1) | DE3570555D1 (ko) |
| WO (1) | WO1986003622A1 (ko) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087267A (en) * | 1986-03-04 | 2000-07-11 | Motorola, Inc. | Process for forming an integrated circuit |
| US4786962A (en) * | 1986-06-06 | 1988-11-22 | Hewlett-Packard Company | Process for fabricating multilevel metal integrated circuits and structures produced thereby |
| US4700462A (en) * | 1986-10-08 | 1987-10-20 | Hughes Aircraft Company | Process for making a T-gated transistor |
| US4747211A (en) * | 1987-02-09 | 1988-05-31 | Sheldahl, Inc. | Method and apparatus for preparing conductive screened through holes employing metallic plated polymer thick films |
| US5298365A (en) | 1990-03-20 | 1994-03-29 | Hitachi, Ltd. | Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process |
| US5897376A (en) * | 1993-09-20 | 1999-04-27 | Seiko Instruments Inc. | Method of manufacturing a semiconductor device having a reflection reducing film |
| TW439118B (en) * | 2000-02-10 | 2001-06-07 | Winbond Electronics Corp | Multilayer thin photoresist process |
| US6713395B2 (en) * | 2001-05-15 | 2004-03-30 | Infineon Technologies Ag | Single RIE process for MIMcap top and bottom plates |
| US6979526B2 (en) * | 2002-06-03 | 2005-12-27 | Infineon Technologies Ag | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs |
| US7223612B2 (en) * | 2004-07-26 | 2007-05-29 | Infineon Technologies Ag | Alignment of MTJ stack to conductive lines in the absence of topography |
| US7442624B2 (en) * | 2004-08-02 | 2008-10-28 | Infineon Technologies Ag | Deep alignment marks on edge chips for subsequent alignment of opaque layers |
| JP2006261434A (ja) * | 2005-03-17 | 2006-09-28 | L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude | シリコン酸化膜の形成方法 |
| TWI797640B (zh) | 2020-06-18 | 2023-04-01 | 法商液態空氣喬治斯克勞帝方法研究開發股份有限公司 | 基於矽之自組裝單層組成物及使用該組成物之表面製備 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5218425B2 (ko) * | 1972-05-01 | 1977-05-21 | ||
| US3985597A (en) * | 1975-05-01 | 1976-10-12 | International Business Machines Corporation | Process for forming passivated metal interconnection system with a planar surface |
| US4176029A (en) * | 1978-03-02 | 1979-11-27 | Sperry Rand Corporation | Subminiature bore and conductor formation |
| GB1596907A (en) * | 1978-05-25 | 1981-09-03 | Fujitsu Ltd | Manufacture of semiconductor devices |
| JPS5850417B2 (ja) * | 1979-07-31 | 1983-11-10 | 富士通株式会社 | 半導体装置の製造方法 |
| US4409319A (en) * | 1981-07-15 | 1983-10-11 | International Business Machines Corporation | Electron beam exposed positive resist mask process |
| US4398964A (en) * | 1981-12-10 | 1983-08-16 | Signetics Corporation | Method of forming ion implants self-aligned with a cut |
| CA1169022A (en) * | 1982-04-19 | 1984-06-12 | Kevin Duncan | Integrated circuit planarizing process |
| FR2537779B1 (fr) * | 1982-12-10 | 1986-03-14 | Commissariat Energie Atomique | Procede de positionnement d'un trou de contact electrique entre deux lignes d'interconnexion d'un circuit integre |
| DE3344280A1 (de) * | 1982-12-21 | 1984-07-05 | Texas Instruments Inc., Dallas, Tex. | Verfahren zur herstellung einer halbleitervorrichtung und vorrichtung zur durchfuehrung des verfahrens |
| US4415606A (en) * | 1983-01-10 | 1983-11-15 | Ncr Corporation | Method of reworking upper metal in multilayer metal integrated circuits |
| US4517731A (en) * | 1983-09-29 | 1985-05-21 | Fairchild Camera & Instrument Corporation | Double polysilicon process for fabricating CMOS integrated circuits |
-
1984
- 1984-12-07 US US06/679,506 patent/US4592132A/en not_active Expired - Lifetime
-
1985
- 1985-11-25 DE DE8585906125T patent/DE3570555D1/de not_active Expired
- 1985-11-25 JP JP60505334A patent/JPS62501321A/ja active Granted
- 1985-11-25 EP EP85906125A patent/EP0204768B1/en not_active Expired
- 1985-11-25 KR KR1019860700533A patent/KR900001986B1/ko not_active Expired
- 1985-11-25 WO PCT/US1985/002305 patent/WO1986003622A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| EP0204768A1 (en) | 1986-12-17 |
| KR870700171A (ko) | 1987-03-14 |
| DE3570555D1 (en) | 1989-06-29 |
| WO1986003622A1 (en) | 1986-06-19 |
| US4592132A (en) | 1986-06-03 |
| EP0204768B1 (en) | 1989-05-24 |
| JPS62501321A (ja) | 1987-05-21 |
| JPH0320064B2 (ko) | 1991-03-18 |
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