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KR900001514Y1 - Packet address detecting circuits of teletext - Google Patents

Packet address detecting circuits of teletext Download PDF

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KR900001514Y1
KR900001514Y1 KR2019860019307U KR860019307U KR900001514Y1 KR 900001514 Y1 KR900001514 Y1 KR 900001514Y1 KR 2019860019307 U KR2019860019307 U KR 2019860019307U KR 860019307 U KR860019307 U KR 860019307U KR 900001514 Y1 KR900001514 Y1 KR 900001514Y1
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teletext
flip
buffer
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KR880013968U (en
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주필상
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삼성전자주식회사
한형수
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/025—Systems for the transmission of digital non-picture data, e.g. of text during the active part of a television frame
    • H04N7/035—Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음.No content.

Description

텔리텍스트의 패키트 어드레스 검출회로Teletext Package Address Detection Circuit

첨부도면은 본 고안의 회로도이다.The accompanying drawings are circuit diagrams of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

SR : 시프트레지스터 LA1-LA3: 래치SR: Shift register LA 1 -LA 3 : Latches

RAM : 램 ROM : 롬RAM: RAM ROM: ROM

CNT : 카운터 G1-G3: 논리게이트CNT: Counter G 1 -G 3 : Logic Gate

BF : 버퍼 CMP : 비교기BF: Buffer CMP: Comparator

F1-F5: 플립플롭F 1 -F 5 : flip-flop

본 고안은 텔리텍스트(Teletext)의 패키트 어드레스(Packet Address) 검출회로에 관한 것으로서, 특히 패키트 어드레스를 검출하여 텔리텍스트의 송신되는 데이터를 추출하기 위한 회로에 관한 것이다.The present invention relates to a packet address detection circuit of teletext, and more particularly to a circuit for extracting transmitted data of teletext by detecting a package address.

텔리텍스트 디코더에서는 송신되어 오는 신호를 해독하는데, 송신되는 신호에서 데이터를 추출하기 위해 패키트 어드레스를 검출한다.The teletext decoder decodes the transmitted signal, which detects the packet address to extract data from the transmitted signal.

종래에는 데이터전송전에 전송제어순서에 대응하는 프로토콜(Protocol)에 따라 송수신간에 데이터식별신호 및 응답신호에 전송되는 등, 그리고 패키트 어드레스의 검출을 소프트웨어로 처리하였기 때문에 처리속도가 늦는 단점이 있었다.Conventionally, the processing speed is slow because the data identification signal and the response signal are transmitted between the transmission and reception according to the protocol corresponding to the transmission control procedure before the data transmission, and the detection of the package address is performed by software.

따라서, 본 고안의 목적은 상기한 단점을 해결하기 위해 안출한 것으로서, 송신되는 신호에서 패키트 어드레스를 하드웨어로 검출하여 송신되는 데이터가 저장된 다음 시스템으로 전송되도록 제어하는 회로에 관한 것이다.Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and relates to a circuit for controlling a packet address in a transmitted signal to hardware and controlling the transmitted data to be transmitted to a next system.

이하 첨부도면에 의거하여 본 고안의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부 도면에서, 송신되는 텔리텍스트의 직렬데이터를 인가하는 시프트레지스터(SR)는 병렬로 데이터를 출력해서 래치(LA1,LA3)에 인가하고, 래치(LA1)에서 출력되는 데이터는 래치(LA2)를 통해 DMA(Direct Memory Access)용 FIFO(First in First out) 기능을 갖는 램(RAM)에 인가한다.In the accompanying drawings, data output from the serial data shift register (SR) for applying the teletext to be transmitted is applied to a latch (LA 1) in and output the data in parallel to the latch (LA 1, LA 3) is a latch ( LA 2 ) to RAM having a first in first out (FIFO) function for direct memory access (DMA).

그리고, 시프트레지스터(SR)의 출력신호를 인가하는 래치(LA3)는 수평동기신호(HS)와 바이트 동기신호(BS)에 의해 동작되는 카운터(CNT)와 이 카운터(CNT)의 출력신호를 반전게이트(G1)와 노아게이트(G2)에 의해 논리조합하여 인가된 신호로 동기되는 플립플롭(F1)으로 구성된 펄스발생부의 출력펄스로 동기되고, 이 래치(LA3)의 출력신호는 해밍디코드(Hamming Decode)화된 데이터가 저장된 롬(ROM)에 인가되며, 롬(ROM)에서 출력되는 5비트신호중 4비트의 디코딩데이터는 버퍼(BF)에 인가됨과 동시에 남은 1비트신호로 버퍼(BF)를 동기시킨다.The latch LA 3 , which applies the output signal of the shift register SR, receives the counter CNT operated by the horizontal synchronizing signal HS and the byte synchronizing signal BS, and the output signal of the counter CNT. The output signal of this latch LA 3 is synchronized with the output pulse of the pulse generator section consisting of a flip-flop F 1 , which is synchronized by a signal applied in combination by the inversion gate G 1 and the noah gate G 2 . Is applied to ROM where Hamming Decoded data is stored, and 4 bits of decoded data output from ROM is applied to buffer BF and the remaining 1 bit signal is used as buffer (BF). BF) is synchronized.

상기한 버퍼(BF)의 출력신호는 시스템의 중앙처리장치에서 출력되는 패키지 어드레스와 함께 비교기(CMP)에 인가되고 비교되고, 이 비교기(CMP)에서 비교되어 출력되는 신호는 오아게이트(G3)의 한 입력단과 플립플롭(F2,F4)의 입력단에 인가되며, 이 플립플롭(F4)의 출력단 신호는 오아게이트(G3)이 다른 입력단에 인가되고, 플립플롭(F2)의 출력단 신호는 플립플롭(F3)에 입력되어서 출력단을 통해 오아게이트(G3)의 또다른 입력단에 인가한다.The output signal of the buffer BF is applied to and compared with the comparator CMP together with the package address output from the central processing unit of the system, and the signal compared and output from the comparator CMP is the oragate G 3 . Is applied to one input of the input and the input of the flip-flop (F 2 , F 4 ), the output terminal signal of the flip-flop (F 4 ) is the OA gate (G 3 ) is applied to the other input, the flip-flop (F 2 ) The output stage signal is inputted to the flip-flop F 3 and applied to another input terminal of the oragate G 3 through the output stage.

또한, 상기한 오아게이트(G3)의 출력단신호는 시스템에 인터럽트신호로 인가함과 동시에 플립플롭(F5)을 동기시켜서 플립플롭(F5)에서 출력되는 신호에 의해 램(RAM)이 인에이블된다.In addition, the output terminal signal of the OA gate G 3 is applied as an interrupt signal to the system and the flip-flop F 5 is synchronized with the output signal from the flip-flop F 5 . Is enabled.

상기한 램(RAM)에 저장된 데이터는 입력되는 순서로 먼저 출력되어서 텔리텍스트버퍼에 입력된다.The data stored in the RAM is first output in the order of input and is input to the teletext buffer.

이상과 같이 구성되는 본 고안인 텔리텍스트의 패키트 어드레스 검출회로의 동작을 설명한다.The operation of the package address detection circuit of the teletext of the present invention configured as described above will be described.

송신신호중 패키트 어드레스는 해밍 인코드(Hamming Encode)화된 데이터이고 3바이트로 되어 있어서 시스템에서 요구하는 패키트 어드레스와 일치하면 송신 데이터를 입력하게 된다.The packet address of the transmission signal is Hamming Encoded data, and it is 3 bytes. If the packet address matches the packet address required by the system, the transmission data is input.

도면에서 수신되어진 방송신호에서 추출된 텔리텍스트 직렬데이터는 시프트레지스터(SR)에 의해 병렬로 출력되고, 이 병렬데이터는 래치(LA1,LA2)로 구성된 데이터파이프라인(Pipeline)을 통과하여서 램(RAM)에 인가된다.The teletext serial data extracted from the broadcast signal received in the figure is output in parallel by the shift register SR, and the parallel data is passed through a data pipeline composed of latches LA 1 and LA 2 . Is applied to (RAM).

한편, 시프트레지스터(SR)의 병렬출력신호는 래치(LA3)에 인가되는데, 카운터(CNT)에서 출력되는 신호에 의해 동기되는 플립플롭(F1)의 출력신호가 래치(LA3)를 동기시킨다. 이때, 래치(LA3)의 출력신호가 롬(ROM)에 인가됨에 따라 롬(ROM)에서 해밍코드에 대응되는 4비트 디코딩 데이터가 버퍼(BF)에 인가됨과 동시에 1비트 제어신호가 버퍼(BF)에 인가되어서 정확한 디코딩데이터가 버퍼(BF)에 저장되도록 한다.Meanwhile, the parallel output signal of the shift register SR is applied to the latch LA 3 , and the output signal of the flip-flop F 1 synchronized with the signal output from the counter CNT synchronizes the latch LA 3 . Let's do it. At this time, as the output signal of the latch LA 3 is applied to the ROM, 4-bit decoded data corresponding to the hamming code is applied to the buffer BF while the 1-bit control signal is applied to the buffer BF. ), So that the correct decoding data is stored in the buffer (BF).

즉, 롬(ROM)에서 출력되는 1비트 제어신호가 논리 "0"(로우레벨) 신호일 때에만 롬(ROM)의 4비트 디코딩 데이터가 버퍼(BF)에 저장된다.That is, 4-bit decoded data of the ROM is stored in the buffer BF only when the 1-bit control signal output from the ROM is a logic "0" (low level) signal.

상기한 디코딩데이터는 시스템의 중앙처리장치에서 요구하는 패키트어드레스와 함께 비교기(CMP)에 의해 비교되는데, 이 비교기(CMP)에 입력되는 두 신호가 일치하면 논리 "1"(하이레벨)신호가 출력되어서 오아게이트(G3)와 플립플롭(F2,F4)에 입력된다.The decoded data is compared by the comparator (CMP) together with the packet address required by the central processing unit of the system. When the two signals input to the comparator (CMP) match, a logic "1" (high level) signal is The output is input to the oragate G 3 and the flip-flops F 2 and F 4 .

상기한 논리 "1"신호를 입력하는 플립플롭(F2,F4)은 수평동기신호(HS)가 발생할 때마다 클리어 되므로 첫 해밍코드신호가 일치되어 논리 "1"신호를 입력하여도 오아게이트(G3)에 인가되는 신호만 논리 "1"이 된다.The flip-flops F 2 and F 4 for inputting the logic " 1 " signal are cleared each time the horizontal synchronization signal HS is generated. Therefore, even if the first Hamming code signal is matched and the logic " 1 " Only the signal applied to (G 3 ) becomes logic "1".

그리고, 플립플롭(F4)의 출력신호는 두번째 해밍코드가 입력될때 논리 '1"이 되어서 오아게이트(G3)에 인가되고, 플립플롭(F2)가 연결된 플립플롭(F3)은 세번째 해밍코드가 입력될때 논리 "1"신호를 출력하여서 오아게이트(G3)에 인가된다.When the second hamming code is input, the output signal of the flip-flop F 4 becomes a logic '1' and is applied to the oragate G 3 , and the flip-flop F 3 to which the flip-flop F 2 is connected is the third. When the Hamming code is input, a logic "1" signal is output and applied to the oragate G 3 .

따라서, 오아게이트(G3)에서 출력되는 논리 "1"신호는 송신데이터의 선단부 매칭(Matching) 인터럽트 신호로서 시스템에 인가됨과 동시에 수평동기신호(HS)에 의해 클리어되는 플립플롭(F5)을 동기시킨다.Accordingly, the logic " 1 " signal outputted from the oragate G 3 is applied to the system as a matching interrupt signal of the transmission data and clears the flip-flop F 5 which is cleared by the horizontal synchronization signal HS. Motivate

상기한 플립플롭(F5)의 출력단()에는 동기될 때마다 논리 "0"신호가 나타나서 램(RAM)을 인에이블시킨다.The output terminal of the flip-flop (F 5 ) ( ), A logic " 0 " signal appears every time that synchronization is made, enabling RAM.

이와 같이 램(RAM)이 인에이블됨에 따라 송신되어 온 텔리텍스트 데이터가 시스템의 텔리텍스트버퍼로 전송된다.As the RAM is enabled, the transmitted teletext data is transmitted to the system's teletext buffer.

따라서, 모든 회로는 바이트 동기의 기준신호로 동작되므로 카운터(CNT)와 논리게이트(G1,G2) 및 플립플롭(F1)에 의해 3바이트의 패키트어드레스가 입력될 때에만 래치(LA3)를 동작시켜서 패키트 어드레스를 비교하여 검출하는 것이다.Therefore, since all circuits operate with the reference signal of byte synchronization, the latch LA only when the 3-byte packet address is inputted by the counter CNT, the logic gates G 1 and G 2 , and the flip-flop F 1 . 3 ) is operated to compare and detect the package address.

이상과 같이 본 고안에 의하면 수신되는 텔리텍스트 데이터중에서 패키트 어드레스를 하드웨어로 검출함에 따라 패키트 어드레스 검출신호를 인터럽트신호로 처리하여 독립적으로 수행될 수 있을 뿐만 아니라 처리속도를 향상시킬 수 있다.As described above, according to the present invention, as the package address is detected in the received teletext data by hardware, the package address detection signal may be processed as an interrupt signal to be independently performed, and the processing speed may be improved.

Claims (1)

송신되는 텔리텍스트 데이터를 시프트 레지스터(SR)를 통해 입력하여 저장하는 램(RAM)등으로 구성되는 텔리텍스트 디코더에 있어서, 수평동기신호(HS)와 바이트동기신호(BS)를 인가하여 패키트어드레스 영역만이 입력되도록 카운터(CNT)와 논리게이트(G1,G4) 및 플립플롭(F1)에 의해 발생되는 동기신호에 따라 시프트 레지스터(SR)의 병렬출력신호를 일시 저장하는 래치(LA3)와, 상기 래치(LA3)의 출력신호에 따라 대응되는 해밍코드신호를 출력하는 롬(ROM)과 상기한 롬(ROM)의 정확한 해밍코드의 출력신호를 일시 저장하는 버퍼(BF)와, 상기 버퍼(BF)를 통해 입력되는 해밍코드신호와 시스템의 중앙처리장치에서 출력되는 요구의 패키트 어드레스와의 일치여부를 비교하는 비교기(CMP)와, 상기한 비교기(CMP)의 출력신호를 인가하여 3번째 입력시 논리 "1"신호를 모두 출력하도록 논리동작되게 하는 플립플롭(F1-F4)과 상기한 비교기(CMP)와 플립플롭(F3,F4)의 출력신호를 논리합하는 오아게이트(G3)와, 상기한 오아게이트(G3)의 출력신호에 따라 동기되어서 램(RAM)을 인에이블시켜 시스템의 텔리텍스트 버퍼로 입력된 텔리텍스트 데이터가 전송되도록 제어하는 플립플롭(F5)을 포함하여 이루어진 것을 특징으로 하는 텔리텍스트의 패키트 어드레스 검출회로.In a teletext decoder comprising RAM for inputting and storing transmitted teletext data through a shift register SR, a packet address is applied by applying a horizontal synchronization signal HS and a byte synchronization signal BS. A latch LA for temporarily storing the parallel output signal of the shift register SR in accordance with a synchronization signal generated by the counter CNT, the logic gates G 1 and G 4 , and the flip-flop F 1 so that only the region is input. 3 ) and a buffer (BF) for temporarily storing the output Hamming code signal corresponding to the output signal of the latch (LA 3 ) and the output signal of the correct Hamming code of the ROM (ROM); A comparator (CMP) comparing the Hamming code signal inputted through the buffer (BF) with a packet address of a request output from the central processing unit of the system, and the output signal of the comparator (CMP). By applying a logic "1" signal on the third input. Flip-flops F 1 -F 4 for logic operation to output all, an oragate G 3 for ORing the output signals of the comparators CMP and flip-flops F 3 , F 4 , and the above-mentioned OR And a flip-flop (F 5 ) for synchronizing according to the output signal of the gate (G 3 ) to enable the RAM and to control the transmission of the teletext data input to the teletext buffer of the system. Teletext package address detection circuit.
KR2019860019307U 1986-12-03 1986-12-03 Packet address detecting circuits of teletext Expired KR900001514Y1 (en)

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KR2019860019307U KR900001514Y1 (en) 1986-12-03 1986-12-03 Packet address detecting circuits of teletext

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KR900001514Y1 true KR900001514Y1 (en) 1990-02-28

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