KR900005897B1 - Microprocessor Systems and Their Memory Operations - Google Patents

Abstract

The microprocessor system contains a segmenting mechanism to provide conversion of the virtual address into a second linear address, as well as providing testing and control of the data memory segment attributes. The microprocessor chip (10) is coupled to a main read/ write memory (13). The microprocessor is a 32 bit type and operates with a physical address of 32 bits that is generated by the management system that converts 48 bit virtual addresses using either a segmenting or paying method. The address translation unit (20) has separate modules for the two techniques with one unit having a segment descriptor register and the other a page descriptor cache memory (22).

Description

Microprocessor Systems and Their Memory Operations

1 is a block diagram showing the overall configuration of a microprocessor according to the present invention.

2 is a block diagram showing the partitioning mechanism for the microprocessor of FIG.

3 is a block diagram showing an example of mapping page fields to hit or match in page cache memory.

4 is a block diagram of an example of mapping page fields that are not hit or matched in the page cache memory of FIG. 3, wherein the page directory and page table in the main memory are used.

5 is a diagram showing the attributes stored in the page directory and page table of the page cache memory.

Fig. 6 is a diagram showing the structure of a content address assignable memory and a data storage device for the stored contents contained in the page cache memory.

FIG. 7 is a schematic circuit diagram of a content addressable memory shown in FIG.

FIG. 8 is a schematic logic circuit diagram related to the detector shown in FIG.

* Explanation of symbols for main parts of the drawings

10: microprocessor 13: RAM (main memory)

13A: Page Directory 13b: Page Table

14 bus interface device 16 command decoding device

18: execution device 20: address translation device

22: page apparatus 26: adder

27: comparator 30: page field mapping block

31: output line

34: Content addressable memory (CAM); Contents Addressable Memory

35: page data (reference) memory 40, 41, 42: summer

46,47: AND gate 53: detector

55: multiplexer 56: maintenance and override circuit

57: VUDW logic circuit 75: control logic circuit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to memory operations of microprocessors, and more particularly, to a microprocessor system and a memory operation apparatus related to a address translation apparatus.

Conventional Technology and Issues

Various mechanisms for the conventional memory operation method are widely known. According to one system, a large address (virtual address) can be translated into a smaller entity address, and according to another system. In other words, as a small address using bank switching, a large address space can be accessed. The present invention relates to the former technique in which a virtual address is translated into a small entity address, where the large virtual address is used to access a limited entity address.

It is also well known for the various protection mechanisms of the memory management system, for example, it is possible to prevent the user from writing into the operating system or reading from the operating system to an external port in any system. As will be described in detail, the present invention seeks to provide a protective mechanism, such as part of a peripheral control device, which assigns "attributes" to data at two levels.

The most recent application filed by the applicant is published in US Pat. No. 4,442,484, which describes a memory operating method and protection mechanism incorporating a microprocessor for commercial use such as Intel 286. The microprocessor has a segmentation descriptor register that includes a basic segment address that defines information and attributes (eg, protection bits). The segment descriptor table and the segment descriptor registers both have various control mechanisms such as constraint level and protection type. Bits for determining the number of bits, and the technical details of such a control mechanism are described in detail in US Pat. No. 4,442,484.

One problem with the Intel 286 is that the segment offset is limited to 64K bytes. A series of locations in the physical memory is required for segments that are not always easy to maintain. As can be seen below, one advantage of the system of the present invention is that although the segment offset is as large as the physical address space, It is compatible with the existing segmentation mechanism installed in 286.

[Purpose of invention]

The present invention has been invented in view of the above, and while further improving a microprocessor having a microprocessor and a data memory, the microprocessor translates a virtual memory address into a second memory address (linear address; actual address). It is an object of the present invention to provide a microprocessor system having a segmentation mechanism for measuring and controlling attributes of data memory segments and having a page cache memory.

Further, in the present invention, when page mapping data, particularly page directory and page table, are stored in the data memory and certain hits are not made in the page cache memory, the page information field accesses the page directory and the page table, and the page cache memory. The output of the page table feeds the entity reference address for one page into memory, another field of the linear address feeds the offset into the page, and the page cache memory and page mapping data in the data memory store data on a particular page. It stores a signal indicating the attribute of, which has read protection and write protection that indicate whether the page has already been written and has other information, and especially for data in memory separate from the segment attribute. Level protection To provide a memory management unit of the microprocessor to supply a second layer of the air it is an object.

[Configuration of Invention]

In order to achieve the above object, the present invention provides a microprocessor system including a microprocessor (10) and a RAM (13) having a segmentation mechanism for translating a virtual address into a real address and controlling data according to attributes. And a page cache memory 22 for comparing the page information fields of the real addresses to provide a displacement field under a predetermined state while being integrated with the microprocessor 10 to receive the page information fields of the real addresses. The RAM 13 includes a storage device in which page mapping data according to the real page information field is connected to select an attribute field from page data when a predetermined state of the page cache memory 22 is not bonded. The microprocessor system includes a displacement field to provide a seal for the ram 13. By comprising a circuit for coupling one of the last name field of the offset field of the virtual address it is characterized in that the chamber so as to improve the address of the screen RAM 13.

EXAMPLE

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings. Here, the mechanism of the microsystem, in particular the memory operation method, is as follows. In order to facilitate a full understanding of the present invention, the specific bits are shown in detail as numbers, but the present invention may be practiced without these specific numbers. It is also to be understood that the structure is well known in order to avoid duplication.

The microprocessor system according to the embodiment of the present invention is provided with a microprocessor 10 as shown in FIG. 1. The microprocessor 10 is manufactured by using a CMOS process on a single silicon substrate, and the CMOS Not only is it manufactured, but it can be realized with other technologies such as n-channel, bipolar, SOS, etc.

Under certain conditions in the present invention, it is necessary to access a table stored in the main memory in a memory operation mechanism. FIG. 1 shows a RAM 13 functioning as a main memory in the system, in which a RAM is generally used as a dynamic memory.

As shown in FIG. 1, the microprocessor 10 has a 32-bit physical address, and the microprocessor 10 itself is a 32-bit processor. Although not shown in FIG. 1, a driver and a mathematical processing unit are generally used. In addition, the memory management apparatus according to the present invention utilizes segmentation and paging, wherein a segment is determined by a series of segment descriptor tables that separate a page table used to describe page translation. Wherein the two mechanisms are completely separate and independent. The virtual address is translated into a real address through two different steps using two separate mapping mechanisms, the segmentation technique is used in the first translation stage, and the paging technique is used in the second translation stage. do. Here paging translation can be turned off for one-step translation of segmentation only compatible with Intel 286.

Segmentation (first translation step) translates a 48-bit virtual address into a 32-bit linear address, which consists of a 16-bit segment selector and a 32-bit offset within the segment.

The 16-bit segment selector is used to recognize the segment and access the record list from the segment descriptor table. The record list of the segment includes the segment reference address, the segment size (limit), and various attributes of the segment. In the translation step, the 32-bit offset of the virtual address is added to the segment reference address to obtain the 32-bit linear address, and the 32-bit offset in the virtual address is compared with the segment size, and the access type is checked for the segment attribute. If the 32-bit offset is outside the segment size or the access type is not accepted by the segment attribute, no address processing is performed.

On the other hand, paging (second translation step) translates a 32-bit linear address into a 32-bit real address using two levels of paging tables as in the process described in detail below.

The above two steps are completely independent, where one (large) segment is allowed to consist of several pages, or one page is allowed to consist of several (small) segments. The segment can be any size and can start at any boundary, and is not limited to start at the page boundary, and can be configured to be an exact multiple of the page. In this case, it is possible to separately record the memory protection area starting at an arbitrary address, allowing the segment to be arbitrarily sized.

In segmentation, multiple small segments, each with a single protection attribute and a predetermined size, can be grouped into one single page, in which case segmentation provides protection attributes and paging must be protected separately from virtual memory. It provides a convenient way to map a group of related devices.

In practice, the use of paging to split very large segments into smaller units for memory operations requires the use of a single identifier (segment selector) and a single descriptor (segment) for separate memory protection rather than requiring the use of multiple page descriptors. Descriptor). Paging in segments here has an additional mapping level that allows mapping large segments to split pages that do not need to be in close proximity to real memory.

In fact, paging allows large segments to be mapped so that only a few pages remain in real memory with the remaining segments mapped to disk. Paging also supports the clarity of the substructure for recording protection of large segments, such as certain pages of large segments, while other pages can be recorded.

And segmentation is a very comprehensive protection model that operates on "natural" devices used by programmers, that is, memory of any size that is linearly addressed, and paging is stored back in the main and disk memory of the processor system. The present invention, which is a combination of the two methods, is a very flexible and powerful memory protection model.

As shown in FIG. 1, the microprocessor 10 includes a bus interface device 14. The bus interface device 14 transmits and sends 32-bit data by allowing a 32-bit address signal to be transmitted. It includes a buffer that can be used to exchange signals through the internal bus 19, and to fetch a command from the RAM 13, and a command device in the command decode device 16. It consists of a pre-fetchqueue (a prefetch queue) that sends and receives signals. Here, the queued command includes a 32-bit register file and is processed by an execution unit 18 (arithmetic logic unit), which executes a signal through an internal bus 19 like the decoding unit 16. Receive.

The present invention focuses on the address translation apparatus 20, wherein the address translation apparatus 20 relates to two functions, one related to the segment descriptor register, and the other related to the page descriptor cache memory. Segment registers are mostly well known and described in detail in FIG. The page cache memory, the interaction between the page cache memory and the page directory, and the page table stored in the main memory 13 will be described below with reference to FIGS. 3 to 7 corresponding to the main parts of the present invention.

The segmentation apparatus of FIG. 1 receives a virtual address from the execution device 18 to access segmentation information of an appropriate register, and the register is coupled to the page apparatus via line 23 according to the offset of the virtual address. It contains a basic address.

2 shows an example of accessing a table in main memory when loading a segment register that maps information for a new segment. The segment field constitutes an index of a segment descriptor table in main memory 13. In addition, the contents of the table are supplied to the reference address and additionally related to the data of the segment. The reference address and offset are compared by the comparator 27 to the segment limit, and the output of the comparator 27 provides a bad signal. On the other hand, the adder 26, which is a part of the microprocessor 10, is connected with a reference address and an offset for outputting the real address on the output line 31, and the real address is used as a real address in the microprocessor or used in a paging device. Which is compatible with any program recorded by a conventional microprocessor (Intel 286).

Segment attributes of descriptors, such as various privilege levels, are described in detail in US Pat. No. 4,442,484.

On the other hand, on the left side of the dotted line 28 in FIG. 2, a conventional segmentation mechanism is shown, and the page directory and page table stored in the main memory, the page directory and page table, and the page apparatus shown in FIG. An interaction relationship with the containing page field mapping block 30 is shown in FIGS. 3 to 7.

In the segmentation mechanism of this embodiment, by using a shadow register, the segmentation mechanism can be improved as a cache memory as performed as a paging mechanism.

The dotted line 22a in FIG. 3 shows the page descriptor cache memory of the page device 22 shown in FIG. 1. The memory includes two arrays, namely, addressable memory 34 (CAM) for the contents of the storage. And page data (reference) memory 35. Here, the memory 34, 35 is an improvement on the static memory cell, the structure of which is shown in FIG. 6, and the specific circuit used in the CAM 34 with a single mask feature is shown in FIG. Is shown.

The linear address of the segment apparatus 21 shown in FIG. 1 is connected to the page apparatus 22. The linear address is composed of two fields, namely, a page information field (20 bits) and a displacement field (12 bits). In addition, there is a 4-bit page attribute field supplied by the microcode. The 20-bit page information field is compared with the contents of the CAM 34, and four attribute bits ("dirth", "valid", "U / S", "W / R") are read before the CAM 34 is hit. Must match the attribute bits in) (except when used as masking).

For the hit state, the page data memory 35 supplies a 20-bit reference word combined with the 12-bit displacement field of the linear address, as indicated by the summer 36 of FIG. 3, and the 4K byte page of the main memory 13. Select the composite address from the frame.

The page directory 13a and the page table 13b shown in FIG. 4 are stored in the main memory 13. The reference address for the page directory 13a is supplied from a microprocessor such as the page directory base (38) shown in FIG. 10 bits of the page information field are input into the page directory 13a (after multiplying by a factor of 4) as indicated by the summer 40 of FIG. 4, and the page directory 13a is a 32-bit word. 20 bits of the word are used as a reference for the page table. The other 10 bits of the page information field are again multiplied by a factor of 4, and then stored in the page table 13b through the summer 41 as an index. The page table 13b provides a 30-bit word, of which 20 bits are the page reference addresses of the actual addresses, which are combined with a 12-bit displacement field by the summer 42 and then 32. It is a bit thread address.

In the page directory 13a and in the 12-bit displacement field of the page table 13b, five bits are particularly five attributes ("dirty", "access", "U / S", "R / W", "Present"). Used to indicate This function is described in detail with reference to FIG. The remaining bits of the displacement field are not allocated.

The attribute data stored in the page directory 13a and the page table 13b are input to the control logic circuit 75 according to the 4-bit attribute information included in the linear address. Details of the control logic circuit 75 are described. The matters will be described in detail with reference to the following drawings.

FIG. 5 shows a page directory word, a page table word, and a CAM word. The protection / control attribute data allocated to 4 bits of the page directory word is enclosed and written in parentheses 43. Five protection / control attribute data to which one attribute data is added are added in parentheses 44 for the page table word. The protection / control attribute data for CAM words is enclosed and displayed in parentheses 45, which are used for the following purposes.

1. Dirty (DIRTY); This bit is a bit indicating whether or not a page has been written. The bit is changed once a page is written. The purpose of the use of the bits is to inform the operating system, for example, that the page has not been completely emptied. The storage location of the bits is the page table 13b and the CAM 34, not the page directory 13a. When written, it is set in the page table 13b by the processor.

2. ACCESSED; This bit is stored in the page directory 13a and the page table 13b (not stored in the CAM) and is used to indicate that one page has been accessed. Once a page is accessed, the bit is accessed by the processor into memory, which, unlike dirty bits, is used to indicate whether access to a page is complete when writing or reading. Will be.

3. User / Supervisor (U / S); The state of this bit indicates whether the contents of the page can be accessed by the user and the supervisor (binary 1) or only by the supervisor (binary 0).

4. R / W; This read / write protect bit must be binary 1 when the page is written by the user program.

5. PRESENT; The bit in page table 13b indicates whether the associated page is currently in real memory, while the bit in page directory 13a indicates whether the associated page table is currently in real memory.

6. VALID; The bits stored only in the CAM 34 are used to indicate that the contents of the CAM 34 are valid, which bits are set to an initial state for initial setting and then changed when a valid CAM word is loaded. do.

The five bits of page directory 13a and page table 13b are connected to control logic circuit 75 to supply an appropriate fault signal to the microprocessor.

The user / supervisor bits of the page directory 13a and the page table 13b are supplied by the gate 46 to the U / S bits stored in the CAM 34 shown in FIG. The read / write bits R / W of the page directory 13a and the page table 13b are provided as R / W bits stored by the gate 47 and stored in the CAM 34, and the page table 13b. Is stored in the CAM 34 as a dirty bit, and the gate 46 and 47 are part of the control logic circuit 75 shown in FIG.

The attribute data stored in the CAM 34 are automatically tested and then processed as part of the address and matched for 4 bits from the microcode. If the linear address is R / W = 0, indicating that a "user" recording cycle is occurring in the page, a fault condition occurs even when the valid page reference address is stored in the CAM 34.

The logical end of the U / S bits that are the outputs of the page directory 13a and the page table 13b is to ensure that they are stored in the "worst case" cache memory. Similarly, the R / W bits The logic is to prepare for the worst case of cache memory.

The CAM 34 shown in FIG. 6 consists of eight sets of four sets of four words each, with 21 bits (17 bits for address and 4 bits for attribute data) for matching the array. Used.

Here, four comparator lines of four memory words in each set are connected to the detector, for example, a comparator line for four words of the first set is connected to the detector 53. Similarly, a comparator line for four words from the second set to the eighth set is also connected to the corresponding detector. The detector senses the comparator lines to determine which words in the set match the input (21 bits) to the CAM array. Each detector is hardware connected to select one of the detectors according to the state of 3 bits of the 20 bit page information field coupled to the detector, and the other 17 bits of the page information field are coupled to the CAM array.

Eight detectors for illustration of the present invention are shown in FIG. 6, where three bits selecting one set of four lines for coupling to the detector are used for only one detector, and the detector is shown in FIG. It is.

The data storage area of the cache memory is composed of four arrays such as the arrays 35a to 35d. The data words (reference addresses) corresponding to each set of the CAM 34 are in the array 35a, the data words selected by hitting the second word in the first set are in the array 35b, and the like. The three bits used to select the detector are also used to select the words in each array. As such, words are selected from each of the four arrays at the same time. The final selection of the words output from the array is performed by the multiplexer 55 (MUX) controlled by the four comparator lines of the detector.

When the memory cache is accessed, each of the low-speed matching stages begins by using 21 bits, and the other three bits can instantly select one set of four lines so that the detector can drop the potential on the comparator line. (Compared below, all comparator (thermal) lines pre-charge selected (hit) lines that remain charged while the unselected lines are discharged.)). At the same time, four words output from the selected set are accessed into the arrays 35a to 35d.

If a match is found and the detector can identify the words in the set, the words are transmitted to the multiplexer 55 according to the selection of the data words, which can improve the access time of the cache memory. will be.

FIG. 7 shows that 17 bits of the 21 bits connected to the CAM array are connected to the maintenance generation and override circuit 56, and four attribute data bits are connected to the VUDW logic circuit 57. See FIG. The three bits related to the detector selection among those described above are not shown in FIG.

)을 위해 복수로 되어 있다.The complement generation and override circuit 56 generates a mutual complement signal for the address signal and connects the two complement signals to parallel lines of a CAM array such as lines 59 and 60. Similarly, the VUDW logic circuit 57 generates a mutual complement signal for the attribute data bits and connects the mutual complement signal to parallel lines of the CAM array. The lines 59 and 60 are each complementary bit line (that is, 21 pairs of bit lines BIT and bit lines).

) For plural.

)(행사)사이에 접속됨과 더불어 상기한 한쌍의 열라인(68)(70)과 관련된 것이다.Each of the 32 columns of the CAM array consists of a pair of parallel column lines, such as lines 68 and 70, and a static memory cell, such as a normal cell 67, has a bit line (BIT) and a bit line (

In addition to being connected between the (event) and the pair of column lines 68 and 70 described above.

)에 접속되도록 허용된다. 다른 방법으로는 메모리셀의 내용이 행라인의 데이터와 비교된 다음에 비교결과가 적중라인(68)에 접속된다. 상기한 비교는 각 셀에 관련된 것중의 하나인 비교기에 의해 실행되고, 상기 비교기는 n챈널트랜지스터로 구성된 것으로, 각 쌍의 비교기중 트랜지스터, 예컨대 트랜지스터(61)(62)는 메모리셀의 일단과 반대쪽 비트라인(

)사이에 접속되어 있다.The memory cell according to the embodiment of the present invention is composed of a conventional flip-flop static cell using a P-channel transistor. One line (line 70) of each pair of column lines indicates that the memory cell has a bit line (BIT) and a bit line (data) when data is written into the array.

Is allowed to access Alternatively, the contents of the memory cells are compared with the data in the row lines and then the comparison results are connected to the hit line 68. The comparison is performed by a comparator, which is one of those associated with each cell, and the comparator is composed of n channel transistors, in which transistors of each pair of comparators, for example, transistors 61 and 62 are opposite to one end of the memory cell. Bitline (

) Is connected.

Assuming that the node of the cell closest to the bit line 59 (BIT) while data is stored in the memory cell 67 is high, the first hit line 68 is the transistor (when the contents of the CAM 34 are retrieved). Pre-charged via 69, and then the signal connected to CAM 34 is input on a row line. Since the line 59 is initially assumed to be high, the transistor 62 is not operated because the line 60 is low, and the transistor 63 is connected to the side of the cell connected to the low line. Because it does not work. While in this state, the line 68 indicating that the cell has been matched is not discharged, and the hit line 68 supplies an end condition of the comparison action occurring along the thermal line, where if the cell is not matched, One or more comparators will discharge the hit line.

))이 로우레벨로 되도록 오버라이드신호를 발생시키는데, 이러한 작용에 의해 비교동작이 시작되기 전에 비교기가 전하를 유출하는 것이 방지되게 된다.On the other hand, while the maintenance generation and override circuit 56 and the VUDW logic circuit 57 are precharged, all the row lines (bit line (BIT) and bit line (

An override signal is generated such that)) becomes a low level, which prevents the comparator from draining charges before the comparison operation is started.

)이 하이상태라면, 트랜지스터(61)(62)가 비교동작을 제어하게 된다. 이러한 비교기의 특성은 셀이 무시되는 것을 허용하는 것이다. 이와같이 한 워드가 CAM(34)에 접속되어질 때 비트라인(BIT)(

)을 로우상태로 만듬으로써 정합과정에서 소정 비트들을 마스크시킬 수 있게 되는데, 이것은 셀의 내용이 행라인상의 정합되어짐을 나타나도록 한다. VUDW논리회로(57)는 위와 같은 특성을 이용한 것이다.The search is made when the comparator is in the " binary 1 " state and is ignored if the comparator is in the " binary 0 " state, for example, if the gate of the transistor 64 is high (line 59 is high). If so, the transistors 63 and 64 control the comparison operation described above. Similarly, if bit line 60;

Is high, the transistors 61 and 62 control the comparison operation. The nature of this comparator is to allow the cell to be ignored. In this way, when a word is connected to the CAM 34, the bit line BIT (

By lowering), it is possible to mask certain bits in the matching process, which indicates that the contents of the cell are matched on the row line. The VUDW logic circuit 57 utilizes the above characteristics.

)을 로우상태로 만드는 역할을 한다. 그리하여 마이크로코드비트와 관련된 속성데이터가 무시되어진다. 이러한 특성이, 예컨대 슈퍼바이저리모드(supervisory mode)에서 U/S비트를 무시하기 위해 사용된다. 즉 슈퍼바이저리모드에서는 사용자데이터를 억세스할 수 있게 된다. 이와 마찬가지로 독출/기록비트는 독출중인 때나 슈퍼바이저리모드가 동작가능상태일 때 무시될 수 있다. 더티비트도 독출중일 때 무시된다. (상기 특성은 배리드비트에서 사용되지 않는다)The microcode signal connected to the above VUDW logic circuit 57 is a function of the microcode bits to select one of the attribute data bits.

) To a low state. Thus, attribute data related to microcode bits are ignored. This property is used to ignore the U / S bits, for example in supervisory mode. In other words, the user data can be accessed in the supervisor mode. Similarly, the read / write bit can be ignored when being read or when the supervisory mode is enabled. Dirty bits are also ignored when reading. (The above properties are not used in buried bits)

)을 강제로 로우상태로 만드는 것은 속성데이터비트의 비트패턴이 정합되지 않을지라도 정합을 허가함으로써(또는 장애를 방지함으로써) 예비논리를 공급한다.When the attribute data bits are stored in the main memory, the bits can be accessed or retrieved, and a logic circuit can be used to control access based on the 1 state or 0 state of the U / S bit, for example. However, the cache memory does not use separation logic. Bitline (BIT) and bitline (

Forcing low) supplies the preliminary logic by allowing the match (or by preventing a failure) even if the bit pattern of the attribute data bits does not match.

The detector shown in FIG. 6 has a number of noble gates consisting of gates 81-84 as shown in FIG. Three hit lines of the set selected from the CAM 34 lines are connected to the gate 81, as shown by lines A, B, and C. FIG. Different combinations of the CAM 34 lines are connected to each other noah gate. For example, the hit line D (A) (B) is connected to the noah gate 84. The output of each NOR gate is input to a NAND gate such as NAND gate 86. One hit line (any one of A, B, C, or D) of the hit line that is not input to the noah gate is supplied as one input of each NAND gate. The hit line is a bit line of the set record list to be selected. For example, gate 86 should select a set associated with hit line D. In other words, in the case of the NOR gate 81, the hit line D is connected to the NAND gate 86. Similarly, the hit line C added to the output of the gate 84 with respect to the NAND gate 90 is input to the NAND gate 90. The read enable signal is connected to the NAND gate to prevent the output of this logic circuit from being enabled for writing. The output of the NAND gate, such as line 87, is used to control the multiplexer 55 shown in FIG. 6, and substantially the output signal of the NAND gate, such as the signal on line 81, is passed through the P channel transistor. The multiplexer is controlled, for which purpose an inverter 88 is shown on the output line 89.

The advantage of such a detector is that the precharge line used in the multiplexer can be made operational. While static arrays can be used, this requires a lot of power. In the arrangement as shown in FIG. 8, the outputs of the inverters remain the same until a voltage drop occurs on one of the hit lines, and only when the voltage drop occurs on one hit line, the multiplexer outputs the correct word. A voltage drop will occur that will cause the selection.

[Effects of the Invention]

As described above, according to the present invention, by providing a single address translation apparatus using two levels of cache memory for segmentation and paging, independent data attribute control can be supplied to each level.

Claims (25)

A microprocessor system comprising a microprocessor 10 and a RAM 13 having a segmentation mechanism for translating a virtual address into a real address and controlling data according to attributes, for receiving a page information field of the real address. And a page cache memory 22 for comparing the page information field of the real address to provide a displacement field under a predetermined state while being integrated with the microprocessor 10, wherein the RAM 13 includes the page And a memory device in which the page mapping data according to the real page information field is connected to select an attribute field from the page data when a predetermined state of the cache memory 22 is not matched. 13) one of the displacement field or the attribute field to provide a real address for the virtual address. And a circuit for coupling to a preset field to improve the actual addressing of the RAM (13). 2. The microprocessor system according to claim 1, wherein said page cache memory (22) and said storage device for page data include attribute information of a memory page. 3. The microprocessor system of claim 2, wherein the storage for the page mapping data comprises at least one page directory (13a) and one or more page tables (13b). 4. The microprocessor system of claim 3, wherein attribute data for the memory page is stored in the page directory (13a) and the page table (13b). 5. A microprocessor system according to claim 4, wherein at least some of the attribute data stored in the page directory (13a) and the page table (13b) are logically coupled to and stored in the page cache memory (22). 2. A microprocessor system according to claim 1, wherein the microprocessor (10) is adapted to provide a page directory reference address for the page directory (13a). 2. A microprocessor system according to claim 1, wherein the first zone of the page information field is adapted to supply an index into the page directory reference (38) according to the position of the page directory (13a). 8. The microprocessor system according to claim 7, wherein the position of the page directory 13a storing the page table reference address and the second area of the page information field supply the index in the page table 13b. . 9. A microprocessor system according to claim 8, wherein a position in the page table (13b) is adapted to supply a reference address for a page in the RAM (13). 3. The page reference memory (35) according to claim 2, wherein the page cache memory (22) includes a content addressable memory (34) and a page reference memory (35), and the output of the content addressable memory (34) is stored in the page reference memory (35). Microprocessor system for selecting the page reference address for the RAM (13). 11. The microprocessor system according to claim 10, wherein said content addressable memory (34) is arranged to store attribute data of a data memory page. 12. The microprocessor system of claim 11, comprising means for selectively masking at least one attribute while said content addressable memory is performing a comparison function. And a RAM 13 having a segmentation mechanism for translating the virtual address into a real address and retrieving the attributes of the data memory segment, and a RAM 13 connected to the microprocessor 10. Page cache memory for comparing the page information field of the real address so that the microprocessor 10 is integrated with the microprocessor 10 to receive the page information field of the real address and provides a displacement field under a predetermined state. (22), and the RAM (13) is connected with page mapping data according to the real page information field so as to select an attribute field from the page data when a predetermined state of the page cache memory (22) is not matched. And a microprocessor system to provide a real address for the RAM 13. Group is constituted by a circuit for coupling one of the displacement field or attribute field to the offset field of the virtual address, it characterized in that the microprocessor systems so as to improve the room screen address of the RAM 13. 14. The segment descriptor table (25) according to claim 13, wherein said segmentation mechanism is accessed by a segment descriptor register (21) integral with the microprocessor (10) to provide a segment reference, and by a segment field of said virtual address. Memory operating device of the microprocessor system, characterized in that consisting of the RAM (13) including. 15. The memory operating apparatus according to claim 14, wherein the page cache memory (22) for the page data and the storage device contain information on the attributes of the memory page. 16. The apparatus of claim 15, wherein the storage for the page mapping data comprises a page directory (13a) and a page table (13b). 17. The apparatus of claim 16, wherein each page directory (13a) and page table (13b) are configured to store attribute data for the memory page. 18. The memory operation of a microprocessor system according to claim 17, wherein at least part of the attribute data stored in the page directory (13a) and the page table (13b) are logically combined to be stored in the page cache memory (22). Device. The address translation device 20 formed as part of the microprocessor 10 to operate with the RAM 13 includes a segment descriptor register 21 for receiving a virtual address and providing a reference address of the segment. The processor 10 provides the address to the RAM 13 to allow addressing of the segment descriptor table 25 that provides the segment reference address of the RAM 13 and the second reference address to provide a real address. And a page cache memory 22 adapted to receive and compare a page information field of the actual address to supply a displacement field under a second predetermined state, and to compare the contents with the contents. The processor 10 passes the page data table of the RAM 13 to supply the displacement field when the predetermined second state is not matched. Pieces of information, characterized in that the microprocessor system serves to provide a field, the field so that the displacement can be improved to address room screen of said ram (13) by supplying the page base address for the RAM 13. 20. The address descriptor of claim 19, wherein the segment descriptor register 21 is configured to store the attribute of the segment data, and the page cache memory 22 includes the address translation apparatus 20 configured to store the attribute of the page data. Microprocessor system. A complement generation and override circuit 56 for receiving a first signal and supplying a first signal and a second signal that is a complement of the first signal, and a plurality of signals for receiving one of the first and second signals. Parallel lines 59 and 60 of two parallel pairs, a plurality of memory cells 67 connected between the parallel lines 59 and 60 and arranged in a column perpendicular to the parallel lines 59 and 60; One of the comparator lines is connected between a plurality of column comparators lines associated with the columns of each cell, memory cells 67 on each parallel line and one end of the comparator lines, and binary state information stored in the memory cells 67 and the first and And a plurality of comparators 27 configured to compare second signals, and load means 70 for loading data from the parallel lines 59 and 60 to the memory cells 67. 59) 60 becomes inoperable when the comparator 27 remains in a predetermined binary state In addition, at least part of the maintenance and override circuit 56 supplies the predetermined binary state with respect to the first and second signals so that the selected cell can ignore the comparison operation. 34) microprocessor system comprising: a. 22. The microprocessor system of claim 21, wherein the thermal comparator line comprises a addressable memory (34) of precharged lines. 23. The content addressable memory (34) according to claim 22, wherein data is accessed simultaneously in all of the above-mentioned zones, consisting of a plurality of zones, and output from any one of each zone is selected through the above-described column line. Microprocessor system comprising a. 24. The detector 53 according to claim 23, further comprising a detector 53 connected to correspond to a predetermined number of the parallel lines 59 and 60 and detecting which one of a predetermined number of lines remains charged. And a content addressable memory (34) provided. 25. The microprocessor system of claim 24, comprising a addressable memory (34) configured to select any one of the zones by the detector (53).

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