KR900005006B1 - Stereoscopic tv - Google Patents

Abstract

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Description

Stereoscopic tv

1 is a schematic diagram of the present invention.

2 is a block diagram according to the present invention.

3 is a detailed circuit diagram of a scanning conversion unit used in the present invention.

4 is a detailed circuit diagram of the shutter logic portion used in the present invention.

5 is a control pulse generation circuit diagram used in the present invention.

6 is an input / output waveform diagram of the circuit of the present invention.

* Explanation of symbols for main parts of the drawings

A1, A2: A / D converter B1, B2: Scan type converter

C: Shutter logic part D: D / A conversion part

E: Monitor F: Shutter Glasses

According to the present invention, the right (R) picture signal and the left (L) picture signal transmitted are stored in memory by A / D conversion and read out at a frequency twice the transmission rate, and then converted into D / A by the shutter logic unit. The present invention relates to a circuit in which a right (R) and a left (L) screen are alternately displayed for each field on a monitor (CRT) and a stereoscopic screen can be viewed with synchronized shutter glasses.

In a three-dimensional stereoscopic TV configured to view a stereoscopic image, an image formed on a screen itself using a longitudinal lens is configured to have binocular disparity of left and right eyes.

However, in order to be able to separate the left and right screens with the vertical lens described above, two projection devices capable of projecting the left and right screens, respectively, must be installed, and the resolution is determined by the pitch of the vertical lens. There was a problem that is restricted.

In addition, in order to increase the resolution using the vertical lens, the pitch of the lens itself should be configured to be as small as possible, but it was very difficult in manufacturing the lens.

On the other hand, as a means for eliminating the problems described above, three-dimensional images can be reproduced by using a shutter method using glasses, but flicker occurs on the screen displayed by the frequency of the scanning method of the left and right screens. There was a big disadvantage that reduced vision.

Therefore, the present invention solves the above-mentioned shortcomings, and doubles the frame frequency by using a scanning method conversion by storing a frame that scans left and right screen signals on a monitor and shutters the shutter. The main purpose is to provide a circuit for viewing a stereoscopic screen with glasses with a shutter by alternately displaying the left and right screens on a monitor every field.

Another object of the present invention is to provide a circuit that protects the viewer's vision since flicker does not occur on the screen as the frame frequency is doubled.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, the right (R) and left (L) screen signals are displayed on the monitor (CRT) after the frame frequency is converted by the scanning conversion circuit, and the stereoscopic screen displayed on the monitor can be viewed using the shutter glasses. It is a figure which shows the schematic diagram of a three-dimensional circuit.

2 is a diagram showing the configuration of a stereoscopic TV, and means for storing an analog signal of a right (R) and a left (L) screen in a scanning method converting unit (B1), (B2) as a means for storing the frame frequency. The frame frequencies of the right (R) and left (L) screen signals are doubled in the A / D converters A1 and A2 for converting the signals into digital signals, and the scanning method converters B1 and B2. And the shutter logic unit C to reproduce the stereoscopic image on the monitor E at the output frame frequency, and convert the digital signal output from the shutter logic unit C into an analog signal and apply it to the monitor E. The shutter glasses F are synchronized with the synchronization signal of the D / A converter D and the shutter logic unit C.

)에서 출력된 신호를 인에이블신호로 하며 A/D 콘버터(1)에서 출력된 디지탈신호(n)를 입력으로 하는 버퍼(5),(6)와, 버퍼(5),(6)에서 출력된 프레임을 기수 및 우수 필드에 따라 이를 기입, 독출하도록 필드검출회로(7)의 출력단자(Q1),(

)에서 출력된 신호를 기입 및 독출신호로 함과 동시에 클럭선택회로(9),(12)에서 선택된 클럭에 의해서 신호를 기입할때는 클럭주파수(CK1)주기와 같으며 독출할 때는 클럭주파수(CK2)주기와 같도록 구성된 기수필드메모리(8) 및 우수필드메모리(11)와, 상기한 클럭선택회로(9),(12)에서 선택된 클럭에 따라 기수필드메모리(8)와 우수필드메모리(11)에 어드레스 번지수를 지정하는 어드레스 발생회로(10),(13)으로 구성된다.The second intermediate scanning method converting unit B1 and the scanning method converting unit B2 convert the frame scan, that is, the frequency, output through the projection device for projecting the right screen and the left screen, respectively. As shown in FIG. 3, the scanning method converting unit B1 includes a synchronization separating circuit 2 for separating the horizontal video signal H and the vertical synchronization signal V from the composite video signal of the right (R) picture signal. The horizontal synchronization signal H separated by the separation circuit 2 is used as one input, and the other input is a vertical synchronization signal V delayed for a predetermined time by a time constant through the monostable multivibrator 3 as an input. The output of the NAND gate 4, which is exclusively logically multiplied, as a clear signal, and a pulse detection circuit 7 and a pulse detection circuit which input the vertical synchronization signal V among the signals separated by the synchronous separation circuit 2. Output terminal (Q1) of 7), (

Output from the buffers (5) and (6), and from the buffers (5) and (6), the signal output from the () is an enable signal and the digital signal (n) output from the A / D converter (1) is input. The output terminal Q1 of the field detection circuit 7 to read and write the frame according to the odd and even fields;

In addition, the signal output from the clock signal is a write and read signal, and at the same time, when the signal is written by the clock selected by the clock selection circuits 9 and 12, the clock frequency is the same as the clock frequency CK1 period. Radix field memory 8 and even field memory 11 configured to have the same period, and odd field memory 8 and even field memory 11 according to the clock selected by the clock selection circuits 9 and 12 described above. Address generation circuits 10 and 13 which designate an address address number.

)에서 출력된 신호와 후술하는 콘트롤펄스발생회로의 출력(Q2),(

)을 입력으로 한다.FIG. 4 is a detailed circuit diagram of the shutter logic unit C used in the present invention. The data D1-D4 output from the scanning method converting units B1 and B2 are respectively input and NAND gates N1- described later. Data outputted with the output of N4) as the enable signal is transmitted to the monitor E from the radix field of the right (R) image to the radix field of the left (L) image → right (R) via the D / A converter D. (3) The buffer (ad) allows a stereoscopic screen to be displayed in order from the even field of the image to the even field of the left (L) image, and the inputs of the NAND gates N1 to N4 are input to the pulse detection circuit 7. Output terminal (Q1), (

Signal output from the control pulse generating circuit (Q2), (

) As the input.

5 is a clock pulse generation circuit diagram used in the present invention, m counter R 'that counters the clock pulse CK2 equal to twice the sampling frequency clock pulse CK1 of the A / D converter 1, 2 m counter T, n counter S, U, 4 m counter V ', and flip-flop FF. FIG. 6 is an input / output waveform diagram of the circuit of the present invention.

The circuit operation of the present invention having the configuration as described above will be described in detail.

In FIG. 3, the composite video signal, which is the signal of the right (R) screen, is inputted to the one side input terminal of the horizontal synchronization signal H separated by the synchronization separation circuit 2, and is separated from the synchronization separation circuit 2. When the synchronization signal V is input to the other input terminal through the monostable multivibrator 3, the output of the NAND gate 4 exclusively multiplied by it is output like the CLR of FIG. Is applied to the clear terminal of the pulse detection circuit 7 with the input vertical synchronization signal V as input.

) 각각에서 출력된 제6도의 Q1과

와 같은 펄스가 버퍼(5),(6)의 인에이블단자에 인가되어 출력된 프레임을 기수 및 우수필드에 따라 저장하는 기수필드메모리(8)와 우수필드메모리(11)의 입력단자에 각각 인가되며, 이때 상기 기수필드메모리(8)과 우수필드메모리(11)에 데이터를 기입 및 독출하는 것은 필드검출회로(7)의 출력단자(Q1),(

)에서 출력된 제6도의 Q1과

와 같은 펄스에 의해서 행해지며, 또한 이때 각 필드메모리에 데이터를 기입 및 독출하는 어드레스번지를 후술하는 제5도와 같은 클럭펄스 발생회로에서 발생된 각각의 카운터 리플 케리(Ripple Carry)의 출력(H1,H2,V1,V2)과 필드검출회로(7) 출력단자 (Q1),(

)의 출력을 받아 클럭펄스(CK1),(CK2)를 선택하는 클럭선택회로(9),(12)의 출력을 받아 이에 대응한 어드레스 번지를 발생하는 어드레스 발생회로(10),(13)의 출력에 따르므로 각 필드메모리에 데이터를 저장할 때는 A/D 콘버터(1)에서 샘플링주파수로 사용된 클럭펄스(CK1)의 주기와 같으며, 데이터를 독출할때는 기입되는 속도 클럭펄스(CK1)의 주기 2배인 클럭펄스(CK2)의 주기에 해당된다.A digital signal through the A / D converter 1 is input to the input terminals of the buffers 5 and 6, and at this time, the output terminals Q1 of the pulse detection circuit 7 and (

Q1 of FIG.

Pulses are applied to the enable terminals of the buffers 5 and 6, respectively, and applied to the input terminals of the radix field memory 8 and the even field memory 11, which store the output frames according to the odd and even fields. In this case, writing and reading data into the odd field memory 8 and the even field memory 11 is performed by the output terminal Q1 of the field detection circuit 7, (

Q1 of Figure 6 and

The output of each counter ripple carry (H1) generated by a clock pulse generating circuit as shown in FIG. 5, which is performed by a pulse as shown in FIG. , H2, V1, V2 and field detection circuit 7 output terminals Q1, (

Of the address generation circuits 10 and 13 which receive the output of the clock pulses CK1 and CK2 and select the clock pulses CK1 and CK2. As it is output, the period of clock pulse (CK1) used as sampling frequency in A / D converter (1) when storing data in each field memory is the same. It corresponds to the cycle of the clock pulse CK2 which is twice.

)에서 각각 출력된 제6도의 Q2,

와 같은 신호와 제3도의 필드검출회로(7)에서 출력된 제6도의 Q1,

와 같은 신호를 입력으로 하여 제6도의

와 같은 펄스를 출력하는 낸드게이트(N1),(N2),(N3),(N4)의 각각 출력을 인에이블신호로 하여 각각의 버퍼(a-d)에서 출력된 데이터가 D/A 변환부(D)를 통하여 우측(R)영상의 기수필드→좌측(L)영상의 기수필드→우측(R)영상의 우수필드→좌측(L)영상의 우수필드 순으로 모니터에 입체화면이 디스플레이된다.In this way, the data (D1), (D2) and right (R) screen signals output from the input / output ports (I / O) of the odd field memory (8) and the even field memory (11) are left (L) as described above. The buffer of the shutter logic section C of FIG. 4 in which the screen signal is inputted with the data D3 and D4 outputted from the input / output port I / O of the odd field memory 17 and the even field memory 18. (ad) is the flip-flop (FF) output terminal Q of the clock pulse generating circuit of FIG.

Q2 of FIG. 6 respectively output from

Q1 of FIG. 6 outputted from the field detection circuit 7 of FIG.

With the same signal as in Figure 6

Data output from the respective buffers (ad) using the outputs of the NAND gates (N1), (N2), (N3), and (N4) outputting the same pulse as the enable signal is a D / A converter (D). The stereoscopic screen is displayed on the monitor in the order of the radix field of the right (R) image → the radix field of the left (L) image → the even field of the right (R) image → the even field of the left (L) image.

콘트롤펄스를 제4도의 낸드게이트(N1-N4)의 일측 입력단자에 각각 인가한다.The control pulse generating circuit of FIG. 5 includes n counters S and 2m counters which count by inputting the clock pulse CK2 which is twice the clock pulse CK1 used as the sampling frequency in the A / D converter 1. T), a flip-flop that uses the data V2, H2, H1, V1 output from the 4m counter (V ') and the n counter (U) as clock pulses and the output of the NAND gate 4 in FIG. 3 as a clear signal. Q2 output from (FF),

The control pulse is applied to one input terminal of the NAND gates N1-N4 of FIG.

And the value of m and n of the said counter is calculated | required by the following formula.

Where f _H = horizontal frequency of the input video signal, F _V = vertical (field) frequency of the input video signal.

In this way, the stereoscopic screen displayed on the monitor E can be viewed by wearing matched shutter glasses F, such as the synchronization of the shutter logic unit C. FIG.

As described above, the frame frequency corresponding to the right (R) and left (L) screen signals is doubled, so that a three-dimensional screen without flicker can be enjoyed by wearing shutter glasses.

Claims (4)

A / D converters A1 for converting analog signals into digital signals by inputting right (R) and left (L) video signals, respectively, and a scanning method converter (B1) for converting scans by receiving the output of A2. ), (B2) and the outputs of the scanning conversion unit (B1), (B2) as input, alternately D / A conversion unit (D) one by one without the flicker of the conversion scan corresponding to the left and right images. And a shutter logic unit (C) configured to be displayed on the monitor (E) and to view the stereoscopic screen by wearing the shutter glasses (F). 2. The synchronizing separation circuit (2) according to claim 1, wherein the scanning method converting section (B1) comprises: a synchronizing separation circuit (2) for separating a composite video signal as a right (R) picture signal into a horizontal synchronizing signal (H) and a vertical synchronizing signal (V); Among the synchronization signals separated by the synchronization separation circuit 2, the vertical synchronization signal V and the horizontal synchronization signal H through the monostable multivibrator 3, which are delayed and output for a time determined by the time constant, are exclusive. In the pulse detection circuit 7 and the pulse detection circuit 7, the output of the NAND gate 4 multiplied as a clear signal and the vertical synchronization signal V separated from the synchronization separation circuit 2 are input. The radix and even fields output from the buffers 5 and 6 and the buffers 5 and 6 that use the output signal as the enable signal and the digital signal output from the A / D converter 1 as an input. The clock selection circuit 9 sets the output signal of the field detection circuit 7 as a write and read signal so as to write and read the period. Radix field memory 8 and even field memory 11 which operate by receiving the output of address generating circuits 10 and 13 which output address addresses by clock pulses CK1 and CK2 selected in (12). Stereo TV characterized in that consisting of). 2. The shutter logic section (C) according to claim 1, wherein the shutter logic section (C) inputs data (D1-D4) output from the scanning method converting sections (B1) and (B2), respectively, and outputs the output Q1 of the field detection circuit (7). , (

) And output of control pulse generator (Q2), (

And a buffer (ad) which uses the outputs of the NAND gates (N1-N4) respectively as input signals. 4. The control pulse generating circuit according to claim 3, wherein the control pulse generating circuit counts a clock pulse CK2 equal to twice the sampling frequency of the A / D converter 1 to output pulse signals H1, H2, and V1, V2. The pulse signal Q2 using the m counter (R '), 2 m counter (T), n counter (S), (U), 4 m counter (V'), and the output pulses of the n counter (S) as clock signals. ,

Stereoscopic TV, characterized in that consisting of a flip-flop (FF) for outputting.

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