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KR900004875Y1 - PIP Horizontal Window Signaling Circuit - Google Patents

PIP Horizontal Window Signaling Circuit Download PDF

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Publication number
KR900004875Y1
KR900004875Y1 KR2019870017125U KR870017125U KR900004875Y1 KR 900004875 Y1 KR900004875 Y1 KR 900004875Y1 KR 2019870017125 U KR2019870017125 U KR 2019870017125U KR 870017125 U KR870017125 U KR 870017125U KR 900004875 Y1 KR900004875 Y1 KR 900004875Y1
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gate
signal
cnt
input
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KR890009813U (en
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송광섭
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삼성전자 주식회사
안시환
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Priority to JP1988124638U priority patent/JPH0753336Y2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4438—Window management, e.g. event handling following interaction with the user interface
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information
    • H04N5/45—Picture in picture, e.g. displaying simultaneously another television channel in a region of the screen

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Studio Circuits (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

내용 없음.No content.

Description

PIP의 수평 윈도우 신호발생 회로PIP Horizontal Window Signaling Circuit

제1도는 PIP의 화면 구성도.1 is a screen configuration diagram of a PIP.

제2도는 본 고안의 회로도.2 is a circuit diagram of the present invention.

제3a∼n도는 본 고안에서의 설명을 위한 신호파형도.3a to n are signal waveforms for explanation in the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

L/R : 좌,우측 제어신호단: 메인 수평동기 신호단L / R: Left and right control signal stage : Main horizontal synchronous signal stage

FSC : 주파수 클록신호단 HWD : 수평윈도우 신호단FSC: Frequency clock signal stage HWD: Horizontal window signal stage

HRE : 수평리드신호단: 수평경계 인에이블신호단HRE: Horizontal lead signal stage : Horizontal boundary enable signal stage

CNT1,CNT2: 카운터 NOR1-NOR2: 노어게이트CNT 1 , CNT 2 : Counter NOR 1 -NOR 2 : NORGATE

A1-A4: 앤드 게이트 N1,N2: 낸드 게이트A 1 -A 4 : End gate N 1 , N 2 : NAND gate

OR1: 오어게이트 I1: 인버터OR 1 : Orgate I 1 : Inverter

FF1: D플립플롭FF 1 : D flip flop

본 고안은 PIP(Picture In Picture)의 수평 윈도우(window) 신호 및 경계(border)신호를 발생시킬 수 있도록 한 회로에 관한 것이며, 특히, 2화면을 디스플레이하는 VTR, TV, 모니터 등에서 주화면상에 소화면을 삽입시키고자 할때 윈도우 신호를 좌,우측 위치에 따라 발생시키는데 적용 가능하게한 것이다.The present invention relates to a circuit capable of generating a horizontal window signal and a border signal of a picture in picture (PIP). When inserting the screen, the window signal is generated according to the left and right positions.

종래의 수평 윈도우 신호발생 회로에 있어서는, 카운터의 계산값을 해독하여 윈도우 스타트 엔드포인트(window Start End Point)로부터 윈도우 신호를 발생시키도록 되어있고, 또 카운터 이외의 논리 게이트도 매우 복잡하게 되어 있으며, 경계신호도 해독값을 이용하였기 때문에 많은 논리 게이터가 필요하게 되었던 것이다.In a conventional horizontal window signal generation circuit, a window signal is generated from a window start end point by decoding a calculated value of a counter, and a logic gate other than the counter is also very complicated. Because the boundary signal also uses the readout value, many logic gates are needed.

그러나, 본 고안에서는 이러한 문제점을 해결하기 위해 카운터의 자리올임수(Carry)와 카운터의 해독값 1개를 이용하여서 윈도우 신호 및 경계신호를 효과적으로 발생시킬 수 있도록 하고, 또 논리 게이트 등을 이용하여 정확한 윈도우 신호를 발생시킬 수 있도록 PIP의 수평 윈도우 신호발생 회로를 제공하고자 함에 그 목적이 있다.However, in order to solve this problem, the present invention can effectively generate the window signal and the boundary signal by using the carry-count of the counter and the readout value of the counter. An object of the present invention is to provide a horizontal window signaling circuit of a PIP to generate a window signal.

이를 첨부한 제2도에 의하여 상세히 설명하면 다음과 같다.Referring to Figure 2 attached to this in detail as follows.

좌,우측 제어신호단 L/R에 인버터(I1)를 통하여 카운터(CNT1)의 입력단자(D)·(A)를 각각 연결하고, 메인 수평동기 신호단()과 주파수 클록신호단(FSC)에는 카운터(CNT1),(CNT2)의 입력 로드단자(LD)와 클록단자(CK)를 각각 연결함과 더불어 상기 카운터(CNT1)(CNT2)의 리플 캐리단자(RC1),(RC2)에는 낸드게이트(N2)의 일측 및 타측 입력단을 각각 연결하고, 카운터(CNT1)과 (CNT2)의 출력단자(QA-QD)에는 노어게이트(NOR1), 앤드게이트(A1)의 입력단과 노어게이트(NOR2)(NOR3)의 입력단을 각각 연결 구성하고, 상기 노어게이트(NOR1), 앤드게이트(A1)의 출력단과 노어게이트(NOR2)(NOR3)의 출력단에는 낸드게이트(N1),(N3)의 입력단이 연결된 그의 출력단에는 오어게이트(OR1)의 입력단을 통하여 상기 오어게이트(OR1)의 출력단에는 앤드게이트(A3)의 타측(②)입력단과 D플립플롭(FF1)의 입력클록단자(CK)를 연결하고 상기 D플립플롭(FF1) 출력단자(Q)에는 앤드게이트(A4)의 일측(③)입력단과 수평 윈도우 신호단(HWD)을 연결한다. 상기 낸드게이트(N2)의 출력단에는 앤드게이트(A3)의 일측(①)입력단을 통하여 그의 출력단에는 앤드게이트(A4)의 타측(④)입력단과 수평경계 인에이블 신호단()을 연결하여서 구성한 것이다.Left, connect the input terminal (D) · (A) of the counter (CNT 1) via an inverter (I 1) to the right end control signal L / R, respectively, the main horizontal synchronization signal end ( ) And the frequency clock signal end (FSC), the counter (CNT 1), (CNT 2 ) and the counter (CNT 1) (CNT 2), with also respectively connected to the input load terminal (LD) and the clock terminal (CK) of Ripple carry terminals RC 1 and RC 2 are connected to one side and the other input terminal of the NAND gate N 2 , respectively, and the output terminals Q A -Q D of the counters CNT 1 and CNT 2 are respectively connected. An input terminal of the NOR gate NOR 1 and the AND gate A 1 and an input terminal of the NOR gate NOR 2 NOR 3 are connected to each other, and an output terminal of the NOR gate NOR 1 and the AND gate A 1 is connected. And an output terminal of NOR 2 (NOR 3 ) and an output terminal of NAND gates (N 1 ) and (N 3 ) are connected to an output terminal of NOR gate (OR 1 ) through an input terminal of OR gate (OR 1 ). an output terminal, the aND gate (a 3), the aND gate (a other side (②) input terminal and a D flip-flop connected to the input clock terminal (CK) of (FF 1) and the D flip-flop (FF 1) an output terminal (Q) of 4 ) One side (③) Connect the input terminal with the horizontal window signal terminal (HWD). The output terminal of the NAND gate N 2 is connected to the input terminal of one side (①) of the AND gate A 3 , and the output terminal of the other side ④ of the AND gate A 4 to the output terminal thereof and the horizontal boundary enable signal terminal ( ) By connecting them.

이와같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.

우선, PIP화면은 메인 화면상에서 제1도에서와 같이 화면을 4각에 위치할 수가 있고, 그중 좌,우측의 화면위치는 메인 수평동기 신호에 의해 제어된다. 또 PIP화면은 윈도우 신호 및 FSC(주파수 클록)로 계산하는 값에 의해 수평사이즈가 결정된다. 그러나 본 고안에서는 FF-30신호까지 즉 32Hex=50번까지 카운터에서 계산하여 사이즈를 약로 설정하였으며, 또 윈도우의 좌,우측 위치에 따라서 카운터의 초기 적재량 값이 변화하도록 되어 있고, 수평측 경계신호는로 하였다.First, the PIP screen can be positioned at four angles on the main screen as shown in FIG. 1, and the screen positions on the left and right sides are controlled by the main horizontal synchronization signal. In addition, the horizontal size of the PIP screen is determined by the value calculated by the window signal and the FSC (frequency clock). However, in the present design, the size is calculated by counting up to FF-30 signal, that is, 32Hex = 50 at the counter. The initial load value of the counter changes according to the left and right positions of the window. It was set as.

그럼 제2도에 따라서 설명하여 보면, 메인 수평동기 신호단()의 수평동기 신호(제3a도)는 카운터(CNT1)과 (CNT2)의 로드(LD)단자에 각각 입력하여 좌측 선정시에 제3도에서와 같이 EA(11101010)가 로오딩(loading)되도록 하고, 또 우측 선정시에는 제3도에서와 같이 7A(01111010)가 로오딩 되도록 좌,우측 제어신호단(L/R)의 제어신호를 인버터(I1)에 입력하여 입력된 신호는 카운터(CNT1)의 데이타(A)단자로 입력된다. 이때 카운터(CNT1)의 데이타(A-D)입력에는 1010로 로오딩하게 되고 주파수 클록신호단(FSC)의 클록신호는(제3b도)는 카운터(CNT1)(CNT2)의 클록(CK)단자로 입력되어 상기 카운터(CNT1)(CNT2)에서는 제3c도와 같은 계산이 진행되므로 카운터(CNT1)(CNT2)로부터 발생한 자리올림수(Carry)신호는 카운터(CNT1)과 (CNT2)출력단의 리플캐리(RC1)(RC2)단자를 통해 낸드게이트(N2)에 입력되어 낸드게이트(N2)의 출력단에서는 제3d도와 같은 신호를 얻어낸다. 또한 제3도에서와 같이 MHCT(7÷0)에서 30HexMF 해독하기 위해 카운터(CNT1)의 자리올림수 신호는 상기 카운터(CNT1)의 출력단자(QA-QD)를 통해 노어게이트(NOR1)와 앤드게이트(A1)의 입력단에 각각 입력하고 입력된 신호는 노어게이트(NOR1)와 앤드게이트(A1)의 출력단을 통하여 낸드게이트(N1)에 입력된다.Then, referring to FIG. 2, the main horizontal synchronization signal stage ( The horizontal synchronization signal (Fig. 3a) is input to the load (LD) terminals of the counters CNT 1 and CNT 2 , respectively, and the EA 11101010 is loaded as shown in Fig. 3 at the left selection. In addition, when selecting the right side, as shown in FIG. 3, the control signal of the left and right control signal terminals L / R is input to the inverter I 1 so that 7A (01111010) is loaded. The data A terminal of the counter CNT 1 is input. At this time, the data AD input of the counter CNT 1 is loaded at 1010. The clock signal of the frequency clock signal stage FSC (Fig. 3B) is the clock CK of the counter CNT 1 (CNT 2 ). Since the counter CNT 1 (CNT 2 ) is input to the terminal and the calculation as shown in FIG. 3c is performed, the carry signal generated from the counter CNT 1 (CNT 2 ) is generated by the counters CNT 1 and CNT. 2) through a ripple carry (RC 1) (RC 2) of the output terminal is input to the NAND gate (N 2) the output terminal of the NAND gate (N 2) the 3d also Get the same signal as Also can carry digit of the counter (CNT 1) in order to decrypt 30HexMF in MHCT (7 ÷ 0) as in the third NOR gate is a signal via the output terminal (Q A -Q D) of the counter (CNT 1) ( NOR 1 ) and input signals are respectively input to the input terminals of the AND gate A 1 , and the input signals are input to the NAND gate N 1 through the output terminals of the NOR 1 and AND gates A 1 .

또 카운터(CNT2)의 자리올림수 신호는 상기 카운터(CNT2) 출력단자(QA-QD)를 통해 노어게이트(NOR2)(NOR3)의 입력단에 각각 입력하여 입력된 신호는 그의 출력단을 통하여 낸드게이트(N3)에 입력된다. 이와같이 게이트(N3)에 입력된 신호와 낸드게이트(N1)에 입력된 신호는 오어게이트(OR1)에 입력하여 상기 오어게이트(OR1)의 출력단에서는 제3e도와 같은 30해독펄스 신호가 발생한다.Also can carry digit of the counter (CNT 2) signal and the counter (CNT 2) the output terminal (Q A -Q D) a NOR gate (NOR 2) to each input to an input terminal of the input signal (NOR 3) is through his It is input to the NAND gate N 3 through the output terminal. In this way, the gate (N 3) signal and a NAND gate (N 1) the signals are OR gate with the input to (OR 1) The output terminal of the OR gate (OR 1) of claim 3e help 30 decode the pulse signal as input to an input to the Occurs.

이와같이 발생된 30해독펄스 신호와 제3d도의 RC신호는 앤드게이트(A3)에 입력되어 상기 앤드게이트(A3)의 출력단에서는 제3f도와 같은신호를 수평경계 인에이블 신호단()으로 출력하여 경계신호로 사용한다. 다음에 수평 윈도우 신호단(HWD)으로는 낸드게이트(N2)에 입력된 리플캐리(RC)신호는 상기 낸드게이트(N2)의 출력단을 통해 D플립플롭(FF1)의 세트(SET)단자에 입력하여가 "로우"로 되는 순간 D플립플롭(FF1)의 출력(Q)는 세팅되며는 계속 "하이"상태로 유지하다가 오어게이트(OR1)의 출력이 펄스 30의 상승에지에서 D플립플롭(FF1)의 출력단자(Q)는 "로우"상태이므로 HWD는 다시 0로 된다.In this way the generated pulse signal and a decode 30 degrees 3d RC signal is the AND gate (A 3) The output terminal of the AND gate (A 3) is input to the same 3f help Signal to the horizontal boundary enable signal stage ( Output as) to use as boundary signal. Next the horizontal window signal end (HWD) is a ripple input to the NAND gate (N 2) carry (RC) signal is set (SET) of D flip-flop (FF 1) via the output terminal of the NAND gate (N 2) Input to the terminal Is set to "low", the output of the D flip-flop (FF 1 ) (Q) is set Keeps being "high", HWD goes back to zero because the output terminal Q of the D flip-flop (FF 1 ) is "low" when the output of the OR gate OR 1 is the rising edge of the pulse 30.

이와같이 하여 D플립플롭(FF1)의 출력단자(Q)에서 제3g도와 같은 HWD신호가 발생하여 수평 윈도우 신호단(HWD)으로 출력된다. 이와같이 출력된 신호는 HWD(수평 윈도우 신호) 수평경계 인에이블() 신호는 앤드게이트(A4)에 입력하여 실제 데이타 리드 인에이블 신호인 제3h도와 같은 HRE신호를 수평 리드 신호단(HRE)으로 출력하게 된다. 다음에 우측시에는 카운터의 로우딩의 제3i도에서와 같이 7A로 되어 우측 위치를 훨씬길게 계수한 후에 카운터로부터 자리올림수 신호가 발생하며 좌측시와 같이 제3i도 내지 제3n도와 같은 신호가 수평 리드 신호단(HRE)으로 출력하여 수평 윈도우 신호를 발생시키게 되는 것이다.In this manner, the HWD signal as shown in FIG. 3g is generated at the output terminal Q of the D flip-flop FF 1 and output to the horizontal window signal terminal HWD. The signal output in this way is HWD (Horizontal Window Signal) horizontal boundary enable ( ) Signal is inputted to the AND gate A 4 to output an HRE signal such as 3h, which is an actual data read enable signal, to the horizontal read signal terminal HRE. Next, on the right side, as shown in Fig. 3i of the counter's loading, it becomes 7A, and after counting the right position much longer, a digit signal is generated from the counter. The horizontal lead signal terminal HRE is output to generate a horizontal window signal.

이상에서와 같이 동작되는 본 고안은, 좌,우측 경계신호 발생시에 논리게이트를 모두 해독하지 않고 좌측 해독은 카운터의 자리올림수 신호를 이용하여 윈도우 신호 및 경계신호를 효과적으로 발생시킬 수 있도록 하였으며, 또 좌,우측의 위치를 별도로 해독하지 않고 함께 사용할 수 있도록 설계하였다. 그리고 수평 윈도우 신호, 경계신호, 데이타 리드 인에이블 신호는 30해독펄스신호에 의해서 간단하게 설계할 수 있도록 하였으므로 기존의 제반 문제점들을 해결할 수 있는 효과가 있다.The present invention, which operates as described above, is capable of effectively generating window signals and boundary signals by decoding the left and right boundary signals without generating both logic gates, and using the digits of the counter. The left and right positions are designed to be used together without deciphering. In addition, the horizontal window signal, the boundary signal, and the data read enable signal can be simply designed by the 30 read pulse signal, thereby solving the conventional problems.

Claims (1)

좌,우측 제어신호단 L/R에 인버터(I1)를 통하여 카운터(CNT1)의 입력단자(D)(A)를 각각 연결하고, 메인 수평동기 신호단()과 주파수 클록신호단(FSC)에는 카운터(CNT1)(CNT2)의 입력 로드단자(LD)와 클록단자(CK)를 각각 연결하고, 상기 카운터(CNT1),(CNT2)의 리플 캐리단자(RC1)(RC2)에는 낸드게이트(N2)의 입력단을 연결함과 더불어 상기 카운터(CNT1)(CNT2)의 출력단자(QA-QD)에는 노이게이트(NOR1), 앤드게이트(A1)의 출력단과 노어게이트(NOR2)(NOR3)의 출력단에는 낸드게이트(N1)와 낸드게이트(N3)의 입력단이 연결된 그의 출력단에는 오어게이트(OR1)의 입력단을 연결하고, 상기 오어게이트(OR1)의 출력단에는 앤드게이트(A3)의 타측(②)입력단과 D플립플롭(FF1)의 입력클록단자(CK)를 연결하며, D플립플롭(FF1)의 출력단자(Q)에는 앤드게이트(A4)의 일측(③)입력단과 수평 윈도우 신호단(HWD)을 각각 연결하고 낸드게이트(N2)의 출력단에는 앤드게이트(A3)의 일측(①)이 연결된 그의 출력단에는 수평경계 인에이블 신호단()을 연결함과 더불어 접속점(A)에는 앤드게이트(A4)의 타측(④)입력단이 연결된 그의 출력단에는 수평리드 신호단(HRE)을 연결하여 구성된 PIP의 수평 윈도우 신호발생 회로.Left, connect the input terminal (D) (A) of the counter (CNT 1) via an inverter (I 1) to the right end control signal L / R, respectively, the main horizontal synchronization signal end ( ) And ripple of the counter (CNT 1) (the input load of the CNT 2) terminal (LD) and the clock terminal (respectively connected to the CK), said counter (CNT 1), (CNT 2 ) frequency clock signal end (FSC) The input terminal of the NAND gate N 2 is connected to the carry terminal RC 1 (RC 2 ), and the gate NOR 1 is connected to the output terminals Q A -Q D of the counter CNT 1 (CNT 2 ). ), The output terminal of the AND gate (A 1 ) and the output terminal of the NOR gate (NOR 2 ) (NOR 3 ), the output terminal of the NAND gate (N 1 ) and the input terminal of the NAND gate (N 3 ) is connected to the or gate (OR 1 ). The input terminal of the OR gate (OR 1 ), and the other terminal (②) of the AND gate (A 3 ) and the input clock terminal (CK) of the D flip-flop (FF 1 ), D flip-flop An output terminal Q of the (FF 1 ) is connected to an input terminal (③) of the AND gate A 4 and a horizontal window signal terminal (HWD), respectively, and an AND gate (A 3 ) to the output terminal of the NAND gate (N 2 ). One side of (①) Connected the enable signal only its output terminal a horizontal boundary ( ) And a horizontal window signal generation circuit of a PIP configured by connecting a horizontal lead signal terminal (HRE) to an output terminal to which the other end (④) input terminal of the AND gate (A 4 ) is connected to the connection point (A).
KR2019870017125U 1987-10-02 1987-10-02 PIP Horizontal Window Signaling Circuit Expired KR900004875Y1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR2019870017125U KR900004875Y1 (en) 1987-10-02 1987-10-02 PIP Horizontal Window Signaling Circuit
JP1988124638U JPH0753336Y2 (en) 1987-10-02 1988-09-22 PIP horizontal window-signal generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870017125U KR900004875Y1 (en) 1987-10-02 1987-10-02 PIP Horizontal Window Signaling Circuit

Publications (2)

Publication Number Publication Date
KR890009813U KR890009813U (en) 1989-05-31
KR900004875Y1 true KR900004875Y1 (en) 1990-05-31

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KR (1) KR900004875Y1 (en)

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KR890009813U (en) 1989-05-31
JPH0753336Y2 (en) 1995-12-06

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