KR890002168Y1 - Drive circuit of using semiconductor devices - Google Patents
Drive circuit of using semiconductor devices Download PDFInfo
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- KR890002168Y1 KR890002168Y1 KR2019860009187U KR860009187U KR890002168Y1 KR 890002168 Y1 KR890002168 Y1 KR 890002168Y1 KR 2019860009187 U KR2019860009187 U KR 2019860009187U KR 860009187 U KR860009187 U KR 860009187U KR 890002168 Y1 KR890002168 Y1 KR 890002168Y1
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- wave generator
- square wave
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
- H02P23/26—Power factor control [PFC]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2207/00—Indexing scheme relating to controlling arrangements characterised by the type of motor
- H02P2207/01—Asynchronous machines
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P2209/00—Indexing scheme relating to controlling arrangements characterised by the waveform of the supplied voltage or current
- H02P2209/09—PWM with fixed limited number of pulses per period
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S388/00—Electricity: motor control systems
- Y10S388/907—Specific control circuit element or device
- Y10S388/912—Pulse or frequency counter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S388/00—Electricity: motor control systems
- Y10S388/907—Specific control circuit element or device
- Y10S388/915—Sawtooth or ramp waveform generator
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S388/00—Electricity: motor control systems
- Y10S388/907—Specific control circuit element or device
- Y10S388/917—Thyristor or scr
- Y10S388/92—Chopper
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
내용 없음.No content.
Description
제1도는 펄스폭 변조식 초퍼회로의 전력 변환회로.1 is a power conversion circuit of a pulse width modulation chopper circuit.
제2도는 종래의 펄스폭 변조식 초퍼회로의 제어회로.2 is a control circuit of a conventional pulse width modulation chopper circuit.
제3도는 본 고안의 회로도.3 is a circuit diagram of the present invention.
제4도는 제2도 회로도의 각부 파형도.4 is a waveform diagram of each part of the circuit diagram of FIG.
제5도는 본 고안 회로도의 각부 파형도.5 is a waveform diagram of each part of the present invention circuit diagram.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
CP1-CP6: 비교기 B1-B3: 버퍼CP 1 -CP 6 : Comparator B 1 -B 3 : Buffer
I1-I3: 인버터 N1-N3: 낸드게이트I 1 -I 3 : Inverter N 1 -N 3 : NAND Gate
A1,A2: 앤드게이트 PC : 포토카플러A 1 , A 2 : Endgate PC: Photocoupler
T : 트랜스 VR1-VR3: 가변저항T: Trans VR 1- VR 3 : Variable resistor
C1-C3: 콘덴서 R1-R6: 저항C 1 -C 3 : Capacitor R 1 -R 6 : Resistance
D1-D3: 다이오드 5 : 지연구형파 발생부D 1 -D 3 : Diode 5: Delayed Square Wave Generator
6 : 제로크로싱 구형파발생부6: zero crossing square wave generator
7 : 리드구형파발생부7: lead square wave generator
8 : 베이스드라이브 10 : 펄스폭 변조파 발생부8: base drive 10: pulse width modulated wave generator
20 : 베이스 드라이브 구동회로20: base drive driving circuit
본 고안은 유도부하의 역율을 개선하기 위한 펄스폭 변조식 초퍼회로의 드라이브 제어회로에 관한 것이다.The present invention relates to a drive control circuit of a pulse width modulated chopper circuit for improving the power factor of an inductive load.
종래에도 유도전동기의 부하 역율을 개선하기 위하여 제1도와 같이 전력 변환회로를 구성하고 제2도의 펄스폭 변조식 초퍼회로의 제어회로를 구성함으로써 디지탈 신호로써 구동되도록 하였으나 유도전동기의 부하에 흐르는 전류와 전압과의 위상차가 생기기 때문에 전력 변환회로에 역기전력이 발생되어 전력 변환소자가 파괴되는 원인이 되는 것이였다.Conventionally, in order to improve the load power factor of the induction motor, the power conversion circuit is configured as shown in FIG. 1 and the control circuit of the pulse width modulation chopper circuit of FIG. 2 is used to drive the digital signal. Because of the phase difference with the voltage, back electromotive force is generated in the power conversion circuit, causing the power conversion element to be destroyed.
본 고안은 이와 같은 점을 감안하여 교류전원이 제로크로싱 시점을 통과하는 순간에 전력 변환소자가 구동할 수 있는 드라이브 제어회로를 제공하고자 하는 것으로 교류전원의 위상과 동일한 출력을 얻은 제로크로싱 구형파 발생부와 교류전원의 위상보다 앞서는 리드구형파 발생부 및 위상이 뒤진 지연구형파 발생부의 출력이 논리소자를 통하여 베이스 드라이브 회로를 제어하게 구성한 것이다.The present invention is to provide a drive control circuit capable of driving the power conversion element at the moment when the AC power passes the zero crossing point in view of the above point, and a zero crossing square wave generator having the same output as the phase of the AC power. And the outputs of the lead square wave generation unit that precedes the phase of the AC power source and the delayed square wave generation unit of the phase retardation are configured to control the base drive circuit through the logic element.
이를 제3도에 의하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to FIG. 3 as follows.
제3도는 본 고안의 회로도로서 트랜스(T) 2차측 인덕턴스 코일(L1)(L2)(L3)에 위상 선택용 가변저항(VR1-VR3) 및 콘덴서(C1-C3)를 통하여 양 전원(VCC)(-VCC)이 인가되는 비교기(CP1)(CP3)(CP5)에 인가되게 구성시키고 저항(R1-R6) 및 다이오드(D1-D3)를 통하여 비교기(CP2)(CP4)(CP6)와 연결되게 지연구형파 발생부(5), 제로크로싱 구형파 발생부(6), 리드구형파 발생부(7)를 구성하며 버퍼(B1-B3) 및 인버터(I1-I3)를 통하여 낸드게이트(N1-N3), 앤드게이트(A1)(A2) 펄스폭 변조파 발생부(10)에 연결된 오아게이트(OR1)로 전력변환부의 제어회로(8)를 구성시킨후 각각의 포토카플러(PC)로 구성된 베이스 드라이브 구도회로(20)를 통하여 베이스 드라이브(9)에 인가되게 구성시켜 제1도의 전력 변환회로(1)를 제어하게 구성시킨 것이다.The third turning a circuit diagram of the subject innovation transformer (T) 2 primary inductance coil (L 1) (L 2) for the variable resistor in the selected phase (L 3) (VR 1 -VR 3) and a condenser (C 1 -C 3) It is configured to be applied to the comparator (CP 1 ) (CP 3 ) (CP 5 ) to which both power sources (V CC ) (-V CC ) are applied, and resistors (R 1 -R 6 ) and diodes (D 1 -D 3) The delayed square wave generator 5, the zero crossing square wave generator 6, and the lead square wave generator 7 are configured to be connected to the comparator CP 2 (CP 4 ) (CP 6 ) through the buffer B 1. -O 3 connected to the NAND gates (N 1 -N 3 ) and the end gates (A 1 ) (A 2 ) and the pulse width modulated wave generator 10 through the inverters I 1 -I 3 . 1 ) the control circuit 8 of the power conversion unit is configured and then applied to the base drive 9 through the base drive composition circuit 20 composed of each photocoupler PC, thereby converting the power conversion circuit of FIG. 1) is configured to control.
제1도의 전력 변환회로는 각각의 트랜지스터(Q1-Q4)의 콜렉터측에 다이오드(D11-D14)를 구성시킨후 트랜지스터(Q1-Q4)의 베이스측(T1-T4)에 인가되는 상태신호로써 변류기(CT)와 연결된 모우터(M)의 구동을 제어하게 구동시키며 트랜지스터(Q1)(Q2)에 병렬로 아날로그 스위치(SW)를 구성시켜 된 것으로 아날로그 스위치(SW)는 초기전원 인가시 마이콤의 출력에 의하여 연결되어 초기 구동상태를 차단하고 수초후 아날로그 스위치가 개방되어 정상적인 동작을 수행할 수 있게 구성한 것이다.The power conversion circuit of FIG. 1 configures diodes D 11 -D 14 on the collector side of each transistor Q 1 -Q 4 , and then the base side T 1 -T 4 of the transistors Q 1 -Q 4 . ) Is a state signal applied to the drive to control the drive of the motor (M) connected to the current transformer (CT), and the analog switch (SW) is configured in parallel to the transistor (Q 1 ) (Q 2 ) SW) is connected to the output of the microcomputer when the initial power is applied and blocks the initial driving state, and after a few seconds, the analog switch is opened to perform normal operation.
이를 종래의 회로와 비교하여 설명하면 제2도에서 변류기(CT)로 유도된 전류는 펄스폭 변조파 발생부(4)의 전압변환부(11)에서 일정한 전압으로 변환된후 아날로그 디지탈 콘버터(12)에서 일정한 직류전압으로 바뀌어 기준전압 제어부(13)에 인가하게 되고 기준전압 제어부(13)의 출력이 기준전압 발생부(14)를 통하여 PWN 발생부(15)에 인가되므로 삼가파 발진부(16)의 출력에 따라 발생되는 변조파가 전력변환부의 제어회로(2)의 낸드게이트(N4-N7)의 일측으로 인가하게 된다.In comparison with the conventional circuit, the current induced by the current transformer CT in FIG. 2 is converted into a constant voltage by the voltage converter 11 of the pulse width modulated wave generator 4 and then the analog digital converter 12. ) Is converted into a constant DC voltage and applied to the reference voltage control unit 13, and the output of the reference voltage control unit 13 is applied to the PWN generation unit 15 through the reference voltage generation unit 14. The modulated wave generated according to the output of is applied to one side of the NAND gates N 4 -N 7 of the control circuit 2 of the power converter.
그리고 전력변환부의 제어회로(2)는 트랜스(T) 2차측으로 유기된 전원이 비교기(CP7) 및 저항(R7), 제너다이오드(ZD)를 통하여 낸드게이트(N4-N7)에 인가되며 인버터(I7)를 통한 출력이 낸드게이트(N5)에 인가되어 베이스 드라이브(3)에서 출력신호(T1-T4)가 제1도의 전력 변환회로(1)에 인가되어 트랜지스터(Q1-Q4)의 베이스측에 인가되는 출력에 따라 모우터(M)를 구동시키게 된다.In addition, the control circuit 2 of the power converter has a power source induced to the transformer (T) secondary side to the NAND gate (N 4 -N 7 ) through a comparator (CP 7 ), a resistor (R 7 ), and a zener diode (ZD). And an output through the inverter I 7 is applied to the NAND gate N 5 so that an output signal T 1 -T 4 is applied to the power conversion circuit 1 of FIG. The motor M is driven according to the output applied to the base side of Q 1 -Q 4 ).
그러나 이와 같은 회로에서는 교류전원(AC)의 제로크러싱 시점에서 전력 변환소자인 트랜지스터(Q1)(Q2)가 구동되고 트랜지스터(Q3)(Q4)가 구동되어 모우터를 동작시키는 유도부하에 흐르는 전류 및 전압은 제5도의 파형도(AC)와 같이 위상차(θ)가 생기므로 상호 교차시 역기 전력이 생기어 전력 변환소자가 파괴되는 원인이 되는 것이다. 그러나 본 고안은 이와 같이 전력 변환소자가 파괴되는 것을 방지할 수가 있는 것으로 교류전원(AC)이 트랜스(T)의 2차측을 통하여 제로크로싱 구형파 발생부(6), 지연 구형파 발생부(5), 리드(LEAD)구형파 발생부(7)에 인가하게 되면 제로크로싱 구형파 발생부(6)는 교류전원(AC)과 동위상인 제로크로싱 신호를 출력하게 되며 (제5도 a) 지연 구형파 발생부(5)는 교류전원의 위상보다 지연된(θ) 지연구형파(제5도 b)를 출력시키게 되고 리드구형파 발생부(7)는 교류전원의 위상보다 앞선(θ) 구형파를 출력시키게 되는 것으로(제5도의 C) 각 제로크로싱 구형파 발생부(6), 지연구형파 발생부(5), 리드구형파 발생부(7)의 가변저항(VR1-VR3) 및 콘덴서(C3)의 시정수로 원하는 위상의 구형파를 얻을 수가 있으며 각 회로의 비교기(CP1)(CP3)(CP5)는 양전원(VCC)(-VCC)을 사용하여 응답속도를 최단 시간으로 줄일 수 있는 동시에 제로크로싱 시점을 정확하게 검출시킬 수가 있게 되고 각 저항(R1-R6) 및 다이오드(D1-D3)에 비교기(CP2)(CP4)(CP6)를 연결 구성시켜 제로크로싱 출력이 통과하게 함으로써 출력측에 음의 전압(-)이 발생되지 않게 된다. 그리고 이 출력이 전력변환부의 제어회로(8)의 버퍼(B1-B3) 및 버퍼용 인버터(I1-I3)를 통하여 제5도의 각도(a-c)()와 같은 파형을 출력시켜 낸드게이트(N1)는 버퍼(B1) 및 인버터(I2)의 출력을 합성하여 출력(제5도의 d도)하며 낸드게이트(N2)는 인버터(I1) 및 버퍼(B2)의 출력이 합성된 파형(제5도의 e)를 형성하고 낸드게이트(N3)는 낸드게이트(N1)(N2)의 파형을 합성된 출력(제5도의 f)을 오아게이트(OR1)의 일측에 인가시킨다.However, in such a circuit, at the time of zero crushing of the AC power source AC, transistors Q 1 and Q 2 , which are power conversion elements, are driven and transistors Q 3 and Q 4 are driven to operate the motor. Since the current and voltage flowing in the load have a phase difference θ as shown in the waveform diagram AC of FIG. 5, back electromotive force is generated when they cross each other, causing a power conversion element to be destroyed. However, the present invention can prevent the power conversion element from being destroyed in this way. The AC power source AC crosses the zero crossing square wave generator 6, the delayed square wave generator 5, through the secondary side of the transformer T. When applied to the lead square wave generator 7, the zero crossing square wave generator 6 outputs a zero crossing signal in phase with the AC power source AC (FIG. 5 a). ) Outputs a delayed square wave (Fig. 5b) delayed from the phase of the AC power supply (Fig. 5B), and the lead square wave generator 7 outputs a square wave preceding the phase of the AC power supply (θ). C) The phase constants of the variable resistors VR 1 to VR 3 and the capacitor C 3 of each of the zero crossing square wave generators 6, the delayed square wave generators 5, and the lead square wave generators 7 possible to obtain a square wave, and a comparator (CP 1) (CP 3) (CP 5) it is yangjeonwon (V CC) of each circuit - buy (V CC) To make possible to accurately detect the zero-crossing point, the response speed at the same time to reduce the minimum time, and each resistance (R 1 -R 6) and diode comparator (CP 2) (CP 4) to (D 1 -D 3) ( CP 6 ) is connected so that the zero crossing output is passed so that a negative voltage (-) is not generated at the output side. This output is then passed through the buffers B 1- B 3 and the buffer inverters I 1- I 3 of the control circuit 8 of the power converter to the angle ac of FIG. NAND gate (N 1 ) by outputting a waveform such as) synthesizes the output of the buffer (B 1 ) and inverter (I 2 ) output (d in Fig. 5), NAND gate (N 2 ) is the inverter (I 1) ) And the output of the buffer B 2 form a synthesized waveform (e of FIG. 5), and the NAND gate N 3 forms the synthesized waveform of the NAND gate N 1 (N 2 ) (f of FIG. 5). ) Is applied to one side of the oragate (OR 1 ).
오아게이트(OR1)는 펄스폭 변조파 발생부(10)의 변조신호(PWM)와 낸드게이트(N3)의 출력을 합성시킨 출력(g)이 앤드게이트(A1)(A2)의 일측에 인가되고 버퍼(B3) 및 인버터(I3)의 출력이 합성되어 버퍼(B2) 및 인버터(I3)의 출력과 함께 제5도의 h-k과 출력이 베이스 드라이브 구동회로(20)의 각 포토카플러(PC)에 인가되어 베이스 드라이브(9)를 통하여 제어신호(T1-T4)가 제1도의 트랜지스터 베이스측에 인가되어 구동되는 것으로 교류전원(AC)의 양이 전원(+) 구간에서 희생 전력을 패스시켜주는 전력 변환소자인 트랜지스터(Q2)를 위상(θ)만큼 일찍 도통시켜 교류전원이 제로크로싱을 통과하는 시점에서 바이패스시켜주고 교류전원의 음의 전원(-)구간에서도 전력 변환소자인 트랜지스터(Q2)를 위상(θ)만큼 일찍 도통시켜 주므로써 전압과 전류의 위상차에 기인한 교류전원이 제로크로싱 시점에서 역기 전력이 생기어 전력 변환소자가 파괴되는 것을 방지할 수가 있는 것이다.The OR gate OR 1 has an output g obtained by combining the modulated signal PWM of the pulse width modulated wave generator 10 and the output of the NAND gate N 3 , with the AND gate A 1 and A 2 . applied on one side and the buffer (B 3) and an inverter (I 3) and outputs a composite of buffer (B 2) and an inverter (I 3) of claim 5 degrees hk and the output 20 to the base drive driver circuit with the output of The control signal T 1 -T 4 is applied to each photo coupler PC and is applied to the transistor base side of FIG. 1 through the base drive 9 to drive the amount of AC power (+). Transistor Q 2 , a power conversion element that passes the sacrificial power in the section, conducts as early as phase (θ), bypasses the AC power when it passes zero crossing, and negative power (-) section of AC power. in the power conversion device is a transistor (Q 2) of the phase (θ) as a phase difference of voltage and current to the main meurosseo early conduction Which it will be to prevent the AC power supply due to a counter electromotive force which the animation control the power conversion device is destroyed in the zero-crossing point.
이상에서와 같이 본 고안은 교류전원과 동일한 위상 및 위상이 앞서거나 늦은 출력을 이용하여 논리소자를 통하여 전력 변환소자를 제어함으로써 유도전동기의 부하에서 전압과 전류의 위상차에 의하여 전력 변환소자가 파괴되는 것을 방지할 수 있는 효과가 있는 것이다.As described above, according to the present invention, the power conversion element is destroyed by the phase difference of voltage and current in the load of the induction motor by controlling the power conversion element through the logic element by using the same phase and phase or the same output as the AC power source. There is an effect that can be prevented.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860009187U KR890002168Y1 (en) | 1986-06-27 | 1986-06-27 | Drive circuit of using semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860009187U KR890002168Y1 (en) | 1986-06-27 | 1986-06-27 | Drive circuit of using semiconductor devices |
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| Publication Number | Publication Date |
|---|---|
| KR880001428U KR880001428U (en) | 1988-03-15 |
| KR890002168Y1 true KR890002168Y1 (en) | 1989-04-12 |
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| KR2019860009187U Expired KR890002168Y1 (en) | 1986-06-27 | 1986-06-27 | Drive circuit of using semiconductor devices |
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| KR (1) | KR890002168Y1 (en) |
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