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KR850005166A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR850005166A
KR850005166A KR1019840008171A KR840008171A KR850005166A KR 850005166 A KR850005166 A KR 850005166A KR 1019840008171 A KR1019840008171 A KR 1019840008171A KR 840008171 A KR840008171 A KR 840008171A KR 850005166 A KR850005166 A KR 850005166A
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circuit
semiconductor device
diffusion layer
layer
electrostatic protection
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KR930001564B1 (en
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히테도시 이와이 (외 4)
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마쓰다 가쓰기계
가부시기가이샤 히다찌세이사꾸쇼
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Priority to KR1019920018775A priority Critical patent/KR930001563B1/en
Priority to KR1019920018776A priority patent/KR930006139B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having significant overlap between the lightly-doped extensions and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)

Abstract

내용 없음No content

Description

반도체 장치와 이의 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 정전기 보호 회로와 내부 회로가 같은 반도체 서브스트레이트 (substrate)에 있는 DRAM의 칩(chip)패턴(pattern)의 실시예의 평면도.4 is a plan view of an embodiment of a chip pattern of a DRAM in which a static protection circuit and an internal circuit are in the same semiconductor substrate.

제5도와 제7도는 본 발명의 실시예에 따른 제조방법을 나타낸 반도체 장치의 단면도.5 and 7 are cross-sectional views of a semiconductor device showing a manufacturing method according to an embodiment of the present invention.

제9도와 제10도는 각각 제8도의 보호 회로와 내부 회로의 도식적인 평면도.9 and 10 are schematic plan views of the protection circuit and the internal circuit of FIG. 8, respectively.

Claims (21)

적어도 한개의 MIS소자를 구비한 첫번째 회로와 전기적으로 상기 첫번째 회로와 연결된 두번째 회로, 그리고 이러한 첫번째와 두번째 회로가 같은 반도체 서브스트레이트 위에 만들어지고, 상기 첫번째 회로는 이중 확산된 드레인 구조를 갖고, 상기 두번째 회로는 단일 확산된 드레인 구조를 갖는 반도체 장치.A first circuit having at least one MIS element, a second circuit electrically connected to the first circuit, and these first and second circuits are made on the same semiconductor substrate, the first circuit having a double diffused drain structure, and the second circuit The circuit has a single diffused drain structure. 상기 첫번째 회로는 내부 회로이고 두번째 회로는 정전기 보호 회로이고, 정전기 보호회로가 비정상적인 외부 신호로부터 내부 회로를 보호하기 위하여 추가된 것을 특징으로 하는 특허청구의 범위 제1항의 기재의 반도체 장치.The semiconductor device according to claim 1, wherein the first circuit is an internal circuit and the second circuit is an electrostatic protection circuit, and an electrostatic protection circuit is added to protect the internal circuit from abnormal external signals. 상기 정전기 보호회로가 적어도 하나의 확산 저항과 적어도 하나의 클램핑 MIS소자를 포함하는 것을 특징으로 하는 특허청구의 범위 제2항 기재의 반도체 장치.The semiconductor device according to claim 2, wherein the static electricity protection circuit comprises at least one diffusion resistor and at least one clamping MIS element. 상기 확산 저항이 단일 확산된 드레인 구조를 갖는 것을 특징으로 하는 특허청구 범위 제3항 기재의 반도체 장치.The semiconductor device according to claim 3, wherein the diffusion resistor has a single diffusion drain structure. 입력 본딩 패드를 갖고, 상기 저항이 전기적으로 내부회로와 상기 본딩 패드와 연결된 것을 특징으로 하는 특허청구 범위 제3항 기재의 반도체 장치.A semiconductor device according to claim 3, having an input bonding pad and wherein said resistor is electrically connected to an internal circuit and said bonding pad. 출력본딩 패드를 갖고, 정전기 보호회로가 전기적으로 출력 본딩 패드에 연결된 것을 특징으로 하는 특허청구 범위 제2항 기재의 반도체 장치.A semiconductor device according to claim 2, having an output bonding pad, wherein an electrostatic protection circuit is electrically connected to the output bonding pad. 상기 내부 회로가 다이내믹(dynamic) RAM소자를 갖는 것을 특징으로 하는 특허청구 범위 제2항 기재의 반도체 장치.The semiconductor device according to claim 2, wherein the internal circuit has a dynamic RAM element. 상기 내부 회로가 다이내믹 RAM소자를 갖는 것을 특징으로 하는 특허청구 범위 제3항 기재의 반도체 장치.The semiconductor device according to claim 3, wherein the internal circuit has a dynamic RAM element. 첫번째와 두번째 회로가 같은 반도체 서브스트레이트 위에 만들어지고, 적어도 하나의 MIS소자를 구비한 첫번째 회로와, 전기적으로 상기 첫번째 회로와 연결된 두번째 회로를 갖는 반도체 장치의 제조방법. 상기 두번째 회로위에 마스크를 형성하여, 상기 MIS소자에 대한 첫번째 확산 층을 만들고, 상기 마스크를 제거한 후에 상기 MIS소자에 대한 두번째 확산 층과 상기 두번째 회로에 대한 확산 층을 만들어, 상기 첫번째 회로는 이중 확산된 드레인 구조를 갖게하고, 상기 두번째 회로는 단일 확산된 드레인 구조를 갖게하는 공정을 포함하는 상기 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, wherein a first circuit and a second circuit are formed on the same semiconductor substrate, and have a first circuit having at least one MIS element and a second circuit electrically connected to the first circuit. A mask is formed over the second circuit to form a first diffusion layer for the MIS device, and after removing the mask, a second diffusion layer for the MIS device and a diffusion layer for the second circuit are made, wherein the first circuit is double diffusion. And a second diffused circuit having a single diffused drain structure. 상기 첫번째 회로는 내부 회로이고, 상기 두번재 회로는 정전기 보호회로이고, 정전기 보호 회로가 비정상적인 외부 신호로 부터 내부 회로를 보호하기 위하여 추가된 것을 특징으로 하는 특허청구 범위 제9항 기재의 반도체 장치의 제조방법.The first circuit is an internal circuit, the second circuit is an electrostatic protection circuit, and the electrostatic protection circuit is added to protect the internal circuit from abnormal external signals. Manufacturing method. 상기 마스크가 광저항 필름으로 만들어진 것을 특징으로 하는 특허청구 범위 제9항 기재의 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 9, wherein the mask is made of a photoresist film. 상기 첫번째와 두번째 층과, 상기 두번째 회로의 상기 확산 층이 각각 이온 주입에 의하여 만들어진 것을 특징으로 하는 특허청구 범위 제9항 기재의 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 9, wherein the first and second layers and the diffusion layer of the second circuit are each made by ion implantation. 상기 첫번째 확산층이 P-이온의 이온 주입에 의하여 만들어진 N-층이고, 상기 정전기 보호층의 상기 확산층과 상기 두번째 확산층이 As-이온의 이온 주입에 의하여 만들어진 N+층인 것을 특징으로 하는 특허청구 범위 제12항 기재의 반도체 장치의 제조방법.Claim 1 wherein the first diffusion layer is an N - layer made by ion implantation of P - ions, the diffusion layer and the second diffusion layer of the electrostatic protection layer is an N + layer made by ion implantation of As - ions The manufacturing method of the semiconductor device of Claim 12. 상기 두번째 확산층과 상기 두번째 회로의 상기 확산층이 동시에 만들어지는 것을 특징으로 하는 특허청구 범위 제9항 기재의 반도체 장치의 제조방법.A method for manufacturing a semiconductor device according to claim 9, wherein the second diffusion layer and the diffusion layer of the second circuit are made at the same time. 상기 첫번째와 두번째 회로가 같은 반도체 서브스트레이트 위에 만들어지고, 적어도 하나의 MIS소자를 구비하는 첫번째 회로와, 상기 첫번째 회로와 전기적으로 연결된 두번째 회로를 갖는 반도체 장치의 제조방법. 상기 MIS소자에 대한 첫번째 확산층을 만들기 위하여 단지 상기 반도체 장치의 상기 첫번째 회로에만 이온 주입 주사를 하고, 상기 두번째 회로에 대한 확산층과 상기 MIS소자에 대한 두번째 확산층을 만들기 위하여 상기 반도체 소자의 모든 표면에 다시 이온 주입주사를 하여, 상기 첫번째 회로는 이중 드레인 구조를 갖게하고, 상기 두번째 회로는 단일 드레인 구조를 갖게하는 공정을 포함하는 상기 반도체 장치의 제조방법.Wherein said first and second circuits are formed on the same semiconductor substrate and have a first circuit having at least one MIS element and a second circuit electrically connected to said first circuit. An ion implantation scan is made only in the first circuit of the semiconductor device to make a first diffusion layer for the MIS device, and again on all surfaces of the semiconductor device to make a diffusion layer for the second circuit and a second diffusion layer for the MIS device. And ion implantation scanning, wherein the first circuit has a double drain structure, and the second circuit has a single drain structure. 상기 첫번째 회로는 내부 회로이고, 상기 두번째 회로는 정전기 보호 회로이고, 정전기 보호회로가 비정상적인 외부 신호로부터 내부 회로를 보호하기 위하여 추가된 것을 특징으로 하는 특허청구 범위 제15항 기재의 반도체 장치의 제조방법.The first circuit is an internal circuit, and the second circuit is an electrostatic protection circuit, wherein the electrostatic protection circuit is added to protect the internal circuit from abnormal external signals. . 상기 정전기 보호회로가 오프셋(offset)배열에서의 상기 반도체 서브스트레이트의 주변 부분에 위치한것을 특징으로 하는 특허청구 범위 제16항 기재의 반도체 소자의 제조방법.16. The method of claim 16 wherein the electrostatic protection circuit is located at a peripheral portion of the semiconductor substrate in an offset arrangement. 상기 첫번째 확산층이이온의 이온 주입에 의하여 만들어진 N-층이고, 상기 두번째 확산층과 상기 정전기 보호층의 상기 확산층이 As-이온의 이온 주입에 의하여 만들어진 N+층인 것을 특징으로 하는 특허청구 범위 제15항의 기재의 반도체 장치의 제조방법The first diffusion layer A layer, wherein the diffusion layer of the second diffusion layer and the antistatic layer As - - N made by ion implantation of ions semiconductor device as recited in the claims of Part 15 of the substrate, characterized in that N + layer made by ion implantation of ions Manufacturing Method 상기 첫번째 확산층의 P-이온의 이온 주입에 의하여 만들어진 N-층이고, 상기 두번째 확산 층과 상기 정전기 보호층의 상기 확산층이 As-이온의 이온 주입에 의하여 만들어진 N+층인 것을 특징으로 하는 특허청구 범위 제1항의 기재의 반도체 장치의 제조방법Claims characterized in that the N - layer made by ion implantation of P - ions of the first diffusion layer, the diffusion layer of the second diffusion layer and the electrostatic protection layer is an N + layer made by ion implantation of As - ions. The manufacturing method of the semiconductor device of Claim 1 특허청구 범위 제9항 기재의 공정에 의하여 만들어진 반도체 장치.The semiconductor device made by the process of Claim 9. 특허청구 범위 제15항 기재의 공정에 의하여 만들어진 반도체 장치.The semiconductor device made by the process of Claim 15. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019840008171A 1983-12-26 1984-12-20 Semiconductor integrated circuit device Expired - Fee Related KR930001564B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920018775A KR930001563B1 (en) 1983-12-26 1992-10-13 Semiconductor integrated circuit device
KR1019920018776A KR930006139B1 (en) 1983-12-26 1992-10-13 Manufacturing method of semiconductor ic device

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JP58243801A JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device
JP58-243801 1983-12-26

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KR1019920018775A Division KR930001563B1 (en) 1983-12-26 1992-10-13 Semiconductor integrated circuit device
KR1019920018776A Division KR930006139B1 (en) 1983-12-26 1992-10-13 Manufacturing method of semiconductor ic device

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KR850005166A true KR850005166A (en) 1985-08-21
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KR (1) KR930001564B1 (en)
DE (1) DE3446928A1 (en)
FR (1) FR2561042B1 (en)
GB (2) GB2152284B (en)
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US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
JPS57188364U (en) * 1981-05-25 1982-11-30
JPS57211272A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
GB2186426A (en) 1987-08-12
FR2561042B1 (en) 1988-11-10
HK41790A (en) 1990-06-08
GB2152284A (en) 1985-07-31
GB8432417D0 (en) 1985-02-06
IT1179545B (en) 1987-09-16
FR2561042A1 (en) 1985-09-13
IT8424246A0 (en) 1984-12-24
GB8702881D0 (en) 1987-03-18
GB2152284B (en) 1988-01-06
JPS60136374A (en) 1985-07-19
KR930001564B1 (en) 1993-03-04
HK48090A (en) 1990-06-29
DE3446928A1 (en) 1985-07-04
JPH0646662B2 (en) 1994-06-15
GB2186426B (en) 1988-01-06

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