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KR830009836A - Self Clocking Data Transmission System - Google Patents

Self Clocking Data Transmission System Download PDF

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Publication number
KR830009836A
KR830009836A KR1019820001282A KR820001282A KR830009836A KR 830009836 A KR830009836 A KR 830009836A KR 1019820001282 A KR1019820001282 A KR 1019820001282A KR 820001282 A KR820001282 A KR 820001282A KR 830009836 A KR830009836 A KR 830009836A
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signal
binary
state
data
return
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KR880001023B1 (en
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파울 바른스 존
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빈센트 죠셉 라우너
모토로라 인코포레티드
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Priority to KR8201282A priority Critical patent/KR880001023B1/en
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Priority to KR1019880004874A priority patent/KR880001024B1/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

내용 없음No content

Description

셀프 클록킹 데이터 전송 시스템Self Clocking Data Transmission System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명을 실시한 셀프클록킹 데이터 전송 시스템의 계략구성도.1 is a schematic configuration diagram of a self-clocking data transmission system according to the present invention.

제2도는 제1도의 데이터 전송 시스템용 데이터 송신기의 개략구성도.2 is a schematic structural diagram of a data transmitter for a data transmission system of FIG.

제3도는 제1도의 데이터 전송 시스템용 데이터 수신기의 개략구성도.3 is a schematic configuration diagram of a data receiver for a data transmission system of FIG.

Claims (5)

각각 2진 0 상태와 2진 1 상태를 가지는 복수개의 비트를 포함하는 데이타 신호를 송신장치와 제1 및 제2의 2진 신호가 공통결합되는 적어도 한 수신장치간에 통신하기 위한 시스템에 있어서,A system for communicating a data signal including a plurality of bits each having a binary 0 state and a binary 1 state between a transmitter and at least one receiver in which the first and second binary signals are commonly coupled, 데이타 신호를 전송하는 송신장치에는 데이타 신호를 공급하는 신호원과, 데이타 신호의 전후에 제1 및 제2신호의 제1의 2진 상태를 발생하는 제1수단과, 각각의 데이타 신호 비트에 대해 2진 1상태를 가진 한 비트에 대해서는 제2 신호의 제1의 2진 상태와 제1 신호의 제2의 2진상태를 발생하고 2진 0상태를 가진 한 비트에 대해서는 제2신호의 제2의 2진상태와 제1 신호의 제1의 2진상태를 발생하여 데이타신호의 연속비트간에 제1 및 제2신호의 제2의 2진상태를 발생하는 제2수단이 설치되고, 송신장치에서 전송된 데이타 신호를 수신하는 수신장치에는, 제1 및 제2신호의 제2상태에 응답하여 클럭신호를 발생하는 제3수단과, 제1 및 제2신호가 공급되어 제1신호의 제2의 2진상태와 제2신호의 제1의 2진상태에 응답하여 2진 1상태가 되고, 제1 신호의 제1의 2진 상태 및 제2신호의 제2의 2진 상태에 응답하여 2진 0상태가 되는 출력신호를 기억시키는 제4수단이 설치되어 있는 것을 특징으로 하는 셀프클록킹 데이터 전송시스템.A transmitter for transmitting a data signal includes a signal source for supplying a data signal, first means for generating a first binary state of the first and second signals before and after the data signal, and for each data signal bit. Generating a first binary state of the second signal and a second binary state of the first signal for one bit with a binary one state and a second of the second signal for a bit with a binary zero state. Second means for generating a binary state of the first signal and a first binary state of the first signal to generate a second binary state of the first and second signals between successive bits of the data signal; In the receiving device for receiving the transmitted data signal, third means for generating a clock signal in response to the second states of the first and second signals, and the first and second signals are supplied to supply the second signal of the first signal. In response to the binary state and the first binary state of the second signal, a binary one state is obtained, and the first binary state of the first signal And fourth means for storing an output signal in a binary zero state in response to a second binary state of the second signal. 제1항에 의한 데이타 통신 시스템에 있어서, 상기 송신장치가 또한 클럭신호를 발생하는 수단을 포함하여 상기 제2신호의 각각의 2진상태를 발생하는 것을 특징으로 하는 셀프클록킹 데이터 전송 시스템.2. A self-clocking data transmission system according to claim 1, wherein said transmitting device also generates a respective binary state of said second signal, including means for generating a clock signal. 제2항에 의한 데이타 통신 시스템에 있어서, 상기 수신장치가 또한 복수 개의 2진 비트를 가진 송신장치와 수신장치간의 2진 복귀데이타 신호를 공급하는 신호원과, 제3수단의 클럭신호에 응답하여 복귀데이타 신호의 연속 비트에 대해 복귀신호의 대응하는 2진상태를 발생하는 제7수단을 포함하며, 송신장치에는 또한 제6수단의 클럭신호에 응답하여 복귀신호의 연속 2진상태를 기억하기 위해 복귀신호가 공급되는 제8수단이 설치되어 있는 것을 특징으로 하는 셀프클록킹 데이터 전송시스템.3. A data communication system according to claim 2, wherein the receiving device is further adapted in response to a signal source for supplying a binary return data signal between a transmitting device having a plurality of binary bits and the receiving device, and a clock signal of the third means. A seventh means for generating a corresponding binary state of the return signal with respect to the successive bits of the return data signal, wherein the transmitting device also stores the continuous binary state of the return signal in response to the clock signal of the sixth means. A self-clocking data transmission system, characterized in that an eighth means for supplying a return signal is provided. 제3항에 의한 데이타 통신시스템에 있어서, 상기 수신장치에는 또한 복귀신호의 맥동 2진상태를 발생하여 복귀데이타 신호가 전송용으로 사용될 수 있다는 것을 표시하는 제9수단이 설치되고, 송신장치에는 또한 복귀신호가 공급되어 맥동 2진 상태를 검출하고 송신장치를 작용시켜 데이타 신호를 전송하는 제10수단이 설치되어 있는 것을 특징으로 하는 셀프클록킹 데이터 전송시스템.A data communication system according to claim 3, wherein the receiving device is further provided with a ninth means for generating a pulsating binary state of the return signal and indicating that the return data signal can be used for transmission. And a tenth means for detecting a pulsating binary state by supplying a return signal and actuating a transmitting device to transmit a data signal. 제3항에 의한 데이타 통신시스템에 있어서, 각각 제1 및 제2 신호와 복귀신호가 공급되는 복수개의 상기 수신장치가 설치되어 있는 것을 특징으로 하는 셀프클록킹 데이터 전송시스템.A data clock system according to claim 3, wherein a plurality of said receiving devices are provided to which first and second signals and a return signal are supplied, respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8201282A 1982-03-25 1982-03-25 Self-clocking data transmission system Expired KR880001023B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR8201282A KR880001023B1 (en) 1982-03-25 1982-03-25 Self-clocking data transmission system
KR1019880004874A KR880001024B1 (en) 1982-03-25 1988-04-28 Data transmission method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR8201282A KR880001023B1 (en) 1982-03-25 1982-03-25 Self-clocking data transmission system

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1019880004874A Division KR880001024B1 (en) 1982-03-25 1988-04-28 Data transmission method

Publications (2)

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KR830009836A true KR830009836A (en) 1983-12-23
KR880001023B1 KR880001023B1 (en) 1988-06-14

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KR8201282A Expired KR880001023B1 (en) 1982-03-25 1982-03-25 Self-clocking data transmission system

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