KR800001124B1 - Semiconductor device - Google Patents

Abstract

No content.

Description

Semiconductor devices

1 is a schematic enlarged cross-sectional view of a semiconductor device according to the present invention.

2 and 3 are schematic enlarged plan views and enlarged cross-sectional views of an example of a semiconductor device according to the present invention, respectively.

4 is a flowchart showing an example of the manufacturing method of the apparatus of the present invention, respectively.

The present invention relates to a novel semiconductor device having normal bipolar transistor operation but low noise.

Conventional bipolar transistors are obtained by a double diffusion method, and emitter impurity concentrations are selected considerably larger than those of the base to obtain high current amplification by increasing the emitter injection efficiency.

That is, h _FE (emitter ground current amplification factor), which is used as one of the parameters of the specific evaluation of the transistor, is when α is the current amplification factor of the base ground.

Is given by Thus α is

Is given by Where α ^* is the collector amplification rate, β is the base transport efficiency, and γ is the emitter injection efficiency. Now let's consider the emitter injection efficiency of NPN transistor about γ, where γ is

Given by However, J _n is the current density by electrons injected into the base at the emitter, and J _p is the current density by the rate of injection injected into the emitter at the base.

Where J _n and J _p are each

Because of

Where L _n is the diffusion distance of the minority carriers in the base,

n _p : Equilibrium minority carrier concentration in the base,

L _p : Diffusion distance of minority carriers in emitters,

P _n : equilibrium minority carrier concentration in the emitter,

D _n : Diffusion constant of minority carriers in base

V: applied voltage to emitter junction,

D _p : Diffusion constant of minority carriers in the emitter.

는

로 치환할 수 있고, 또 L_n은 베이스폭 W로 제한되므로,If the impurity concentration of the emitter is N _p and the impurity concentration of the base is N _A ,

Is

And L _n is limited to the base width W,

It becomes The diffusion constant is a correlation between carrier mobility and temperature and is considered to be almost constant.

As apparent from the above-described equations, in order to increase the h _FE of the transistor, the smaller δ is preferable.

Here, in the normal transistor, since this δ is made small, the impurity concentration N _D of the emitter is sufficiently increased.

However, if the impurity concentration of the emitter is large enough, for example, about 10 ¹⁹ atoms / cm ³ or more, lattice defects, dislocations, and the like, crystal integrity cannot be obtained, and emitters having good properties can be obtained. It is difficult to obtain such defects.

If the impurity concentration of the emitter is high, the lifetime of the minority carriers injected from the base is shortened,

From the equation, the diffusion length L _p of this minority carrier (hole) becomes short, and as can be seen from the equation (7), δ cannot be made small, and the injection efficiency γ cannot be too high.

The applicant has proposed in Japanese Patent Application No. 48-82819, which filed on July 23, 1973, a semiconductor device LEC which eliminated such defects.

Referring to FIG. 1, the semiconductor device LEC (Low Enitter Concentration Transistor) is described as follows. An example of the illustration is a case of configuring an NPN transistor, in which case the semiconductor body S has a collector region, that is, an N-type first region 1, and a base region disposed adjacent thereto, that is, a P-type second. The area | region 2 and the emitter area | region arrange | positioned adjacent to this, ie, the N type 3rd area | region 3, are comprised. In addition, the fourth region 4 is formed by opposing the PN junction J _e formed between the second and third regions 2 and 3 by connecting the third region 3 to the second region 2. . J _c is a PN junction formed between the first and second regions (1) and (2).

5c, 5b, and 5e are the electrodes of the first, second, and third regions 1, 2, and 3, that is, the collector, base, and emitter electrodes, respectively. (6) is an insulating layer such as SiO ₂ formed on the surface of the base S.

The second and third regions (2) and (3) are each selected as a region whose impurity concentration is selected at a sufficiently low concentration as compared with the conventional one of 10 ¹⁵ atomic number / cm ³ order and is good in crystallinity. .

In addition, the fourth region 4 is selected at a relatively high concentration. (3 ') is a low-resistance region with a high impurity concentration formed in the portion where the electrode 5e of the third region 3 is deposited, and (1') is a high region provided away from the junction J _c of the first region (1). Low resistance region of impurity concentration.

In such a configuration, a forward bias is applied to the emitter junction J _e to each of the electrodes 5e, 5b, and 5c, and a voltage is applied to the collector junction J _c . This allows the first, second and third respective regions 1, 2 and 3 to operate as transistors, as base angle and emitter. In this case, the hole injected from the base region 2 into the emitter region 3 has a long life due to the low impurity concentration of the emitter region 3, the good crystallinity, and the like. In the region 3, the diffusion length L _p of the hole becomes long. Therefore, it is possible to increase the emitter injection efficiency γ as evident in equations (6) and (3).

However, the diffusion length L _p is a greatly different from the actual injection Whole if there is anything to discard surface recombination to reach the substrate surface, substantially diffusion length L _p is not longer supported.

By the way, in the above-described configuration, since the fourth region 4 having a relatively high concentration is disposed to face the emitter junction J _e , the surface recombination is small, so that the diffusion length L _p is sufficiently large and the emitter injection efficiency γ is increased.

In addition thereto, according to this structure a fourth region 4 is installed, so there is a current density J _p is the effect of reducing a Whole injecting emitter region 3 from the base region (2).

That is, in this apparatus, the same potential as that of the base region 2 is given to the fourth region 4, and the PN junction J _s formed between the region 4 and the emitter region 3 is forward biased, so that the emitter region is The density | concentration of the hole of the pole of this area | region 4 of (3) becomes high. As a result, the gradient of the concentration distribution of the hole between the junctions J _e and J _s of the emitter region 3 becomes smooth and the diffusion current J _p becomes smaller from the base region 2 to the emitter region 3 ( As is apparent from Equation 3, the value of the emitter injection efficiency γ increases.

Therefore, the ratio of the electron current reaching the collector among the current components passing through the emitter junction increases and h _FE increases.

As described above, according to the low-concentration emitter type semiconductor device LEC, since the impurity concentrations of the base and emitter regions are selected sufficiently low, the crystallinity of the emitter junction is good, so that the SN with low noise can be constituted. Furthermore, since the fourth region 4 is provided on the surface of the substrate opposite to the emitter junction J _e , a device having a good h _FE can be obtained.

However, in such a configuration, the base expansion resistance rbb 'becomes relatively large. In particular, when the extraction portion of the emitter electrode 5e is made large in order to form a transistor for charging, the length from the center portion of the emitter junction J _b facing the electrode 5e to the base electrode 5b becomes large. Since distribution resistance γ shown in 1 degree becomes large, rbb 'increases.

The present invention aims to reduce the base expansion resistance rbb 'in such a semiconductor device.

Referring to FIG. 2 and FIG. 3, one embodiment of the present invention will be described with the same reference numerals in FIG.

In the present invention, the fourth region having a relatively high impurity concentration is opposed to the junction J _e formed between the second region 2 and the third region 3 operating as an emitter junction with the third region 3 interposed therebetween. For example, the region 4 is configured to be connected to the periphery of the second region 2 in the periphery thereof, and in particular, the fourth region 4 is formed in a lattice or mesh shape as viewed from the back of the base S. Openings 7 are formed. In this way, a part of the third region 3 is brought into contact with the surface of the base S through each opening 7 to form the low resistance region 3 '. For example, an electrode of the second region, i.e., the base electrode 5b, is deposited ohmicly on the peripheral portion of the fourth region 4, and the other portion is covered by the insulating layer 6, and the other openings 7 are not included. The electrode for the third region 3, that is, the emitter electrode 5e, is deposited ohmic over the low resistance region 3 'of.

The interval l between the second region 4 and the fourth region 4, which face each other with the third region 3 interposed therebetween, is from the second region 4 and the fourth region 4 to the third. It is selected to be smaller than the diffusion distance of the minority carrier injected into the region 3.

According to the above-described apparatus, when the forward bias is applied to the PN junction, that is, the emitter junction J _e , formed between the third region 3 of the second region 2, the fourth region 4 and the third region 3 are applied. The forward voltage is also applied to the junction J _e ′ between, and furthermore, the distance l between the second and fourth regions 2 and 4 is selected less than the minority carrier spreading distance in the third region 3. Therefore, the impedance between the opposing parts of the second region 2 and the fourth region 4 is extremely small. Therefore, even in the part J _ea of the emitter junction J _e which mainly faces the emitter electrode 5e disposed in the opening 7, even if the emitter operation is performed, the relatively high impurity concentration, i.e., low resistance, is made near this part. Since the four regions 4 are disposed to face each other, the resistance between the portion J _ea and the electrode 5b is also reduced, resulting in a decrease in base expansion resistance rbb '.

Thus, according to the device of the present invention, it was confirmed that the base expansion resistance rbb 'can be reduced to about 1/2 of that shown in FIG.

In addition, an example of a method of manufacturing the apparatus of the present invention will be described with reference to FIG.

First, as shown in FIG. 4A, a semiconductor substrate having an N-type relatively high impurity concentration, for example, a silicon substrate 1 'having a resistivity of 0.008 to 0.012 µm is provided.

As shown in FIG. 4B, the first region 1 is formed of silicon having a relatively low impurity concentration and having a relatively low impurity concentration on the substrate 1 'such as N ^- type. The first semiconductor layer 8 is epitaxially grown to a thickness of 10 mu. Subsequently, the P-type low impurity concentration second semiconductor layer 9 constituting mainly the second region 2, for example, epitaxially grows a silicon layer having a resistivity of 3 μm to a thickness of 3 to 4 μm. . Gas S is formed by epitaxially growing a third semiconductor layer 10 having a low impurity concentration such as N-type, for example, a silicon layer having a specific resistance of 2 μm and a thickness of 5 to 7 μm. Here, each of these semiconductor layers 8, 9, and 10 is epitaxially grown in the same furnace.

Moreover, the insulating layer 6 which forms a diffusion mask by the well-known technique is formed in the surface of the base | substrate S. As shown in FIG. The insulating layer 6 may be formed of a SiO ₂ layer, for example, by heating the surface of the gas S by heating at 1,130 ° C. for 30 minutes in oxygen.

Photoetching is performed on the insulating layer 6 to form a window having a desired width as an annular shape (the shape is not limited to a circular shape), and an N-type impurity is selectively selected through this window. Diffuses into a length across the third and second semiconductor layers 10 and 9, and surrounds part of the second semiconductor layer 9 by this diffusion region 11 as shown in FIG. The second region 2 is formed here. This diffusion is performed at 1,240 DEG C for 100 minutes, for example, to form the diffusion region 11 having a sheet resistance of 10 k? / ?.

In the portion surrounded by the diffusion region 11, the insulating layer 6 is drilled into an annular shape (in this case, the shape is not limited to a circular shape), but through a window having a desired width. As shown, a P-type impurity is diffused to the depth which touches the 2nd semiconductor layer 9 across the 3rd semiconductor layer 10, and this diffusion area | region 12 has a part of 3rd semiconductor layer 10. FIG. The third region 3 is formed by enclosing. This diffusion can be performed at 1,240 DEG C for 50 minutes, for example, to form the diffusion region 12 having a sheet resistance of 6 mA / ?.

Next, a diffusion window is drilled in the insulating layer 6 over the diffusion area 12 in the other areas, leaving only a portion above the third area 3, and through this window, as shown in FIG. 2) and the fourth region (4) facing the second region (2) by diffusing the diffusion region (12) and the P-type impurity of the same conductivity type and continuing with the second region (2) through the P ⁺ region (12). ) Is formed into a lattice or mesh like forming a plurality of openings 7. The diffusion of this region 4 can be formed so as to have a sheet resistance of 180 k? /? By, for example, diffusion treatment at 1,100 캜 for 10 minutes.

Further, a diffusion window is drilled through the insulating layer 6 on the opening 7 of the fourth region 4 above the third region 3 and through the window, as shown in FIG. 4F on the third region 3. Such conductive N-type impurities are diffused with high concentration to form the low resistance N ^* region 3 '. The diffusion of this region 3 'can be formed so as to have a sheet resistance of about 10 GPa / square by diffusion treatment at 1,000 DEG C for 35 minutes, for example.

Next, an electrode window is drilled through the insulating layer 6, and the emitter electrode 5e is ohmic deposited over each of the low resistance regions 3 'as shown in FIG. 5b) is deposited as ohmic. In the illustrated example, the collector electrode 5c is ohmic deposited on the low resistance region 1 'on the back surface of the substrate S. As shown in FIG.

In this way, a semiconductor device having the configuration as described with reference to FIGS. 2 and 3 according to the present invention is obtained.

The example described with reference to FIG. 2 is a case where the second region 2 is formed by the semiconductor layer 7 by epitaxial growth, but can also be formed by the buried region by diffusion or ion implantation.

In addition, the above-described device of the present invention is a case where the fourth region 4 and the second region 2 are connected by the respective semiconductor regions, and the electrode 5b may be used as the structure electrically connected externally. .

Claims (1)

A first region of the first conductive type and a second region of the second conductive type, a third region of the first conductive type, and a fourth region of the second conductive type partially connected to the second region, A plurality of carriers in three regions are configured to reach the first region through the second region, and the fourth region faces the second region with the third region therebetween, Having an opening, and through the opening, an electrode with respect to the third region is deposited ohmic, and a distance between the second region and the fourth region is selected smaller than the minority carrier diffusion distance in the third region. Semiconductor device.

Images